JPH01144140A - Allocation system for memory board - Google Patents

Abstract

PURPOSE:To easily extend the memory boards by delivering plural address designating signals supplied to the memory boards with delays given by an extent equal to a signal line corresponding to the capacity of the memory board respectively and at the same time connecting these memory boards in a daisy chain. CONSTITUTION:An information processing system, e.g., a personal computer contains a CPU 211 which performs the overall control of the system, three memory boards 231, 241 and 251 which contain the memories storing the programs for the data processed by the CPU 211, and an address decoder 221 which produces the address designating signal for selection of the memory board used by the CPU 211. Then the address designating signals supplied to the memory boards 231, 241 and 251 are delivered with delays given by an extent equal to a signal line corresponding to the capacity of each memory board. Furthermore the boards 231, 241 and 251 are connected in a daisy chain. In such a way, the memory boards can be extended.

Description

[Detailed Description of the Invention] [Summary] Regarding a memory board allocation method for a device that operates using multiple memory boards, the purpose of this invention is to daisy chain multiple memory boards for the purpose of facilitating the addition of memory boards. In the memory board allocation method of a connected device, a memory board among a plurality of memory boards has a plurality of addressing signals specifying a memory area of a predetermined capacity, and a plurality of addressing signals are introduced to determine whether the built-in memory is valid. This is determined based on a part of the address designation signal, and the address designation signal is shifted by a signal line corresponding to the capacity of the memory and output.

[Industrial application field]

The present invention relates to a memory board allocation method,
In particular, the present invention relates to a memory board allocation method for a device that operates using a plurality of memory boards.

[Conventional technology]

Generally, an information processing system such as a personal computer has a main storage device consisting of ROM and RAM that can be directly read and written by its central processing unit (hereinafter referred to as CPU). Particularly in recent years, the capacity of main storage devices has been increasing rapidly as the performance of CPUs has improved. Therefore, the main memory device is composed of multiple memory boards, and initially the memory board containing programs and data areas essential to the system is provided, and other expansion memory boards may be provided as optional parts. .

In this case, the user of the system prepares a memory board as an optional component depending on the required processing power and capacity, and inserts the memory board into an expansion slot for use.

[Problems to be Solved by the Invention] By the way, in the conventional method described above, when adding a memory board, it is necessary to set an address for the memory board assignment, and the address assignment is set by setting a jumper switch. However, the problem was that erroneous operations were likely to occur and adding memory boards was complicated.

In particular, in order to add memory boards and allocate memory without any gaps starting from the side with the smallest address, it is necessary to set the jumper switch keeping in mind the memory capacity and the first address.If operated incorrectly, the CPU may receive unexpected data. or access two or more memories with the same address data.

The present invention was created in view of these points, and an object of the present invention is to provide a memory board allocation method that facilitates the addition of memory boards.

[Means for solving problems]

In the memory board allocation method of the present invention,
A memory board with a device including multiple memory boards connected in a daisy chain has multiple addressing signals that designate a memory area of a predetermined capacity, and one of the addressing signals determines whether the built-in memory is valid. The address designation signal is output after being shifted by a signal line corresponding to the capacity of the memory.

Therefore, the overall configuration is such that a plurality of addressing signals input to the memory board are output after being shifted by a signal line corresponding to the capacity of the memory board, and a plurality of memory boards are connected in a daisy chain.

[For production]

A plurality of addressing signals specifying a memory area of a predetermined capacity are introduced into the memory board, and whether or not the built-in memory is valid is determined based on some of the address assignment signals.

Further, this memory board outputs the address designation signal by shifting it by a signal line corresponding to the capacity of the built-in memory.

A plurality of such memory boards are connected in a daisy chain.

In the present invention, a plurality of address designation signals input to a memory board are shifted by a signal line corresponding to the capacity of the memory board and outputted, and a plurality of memory boards are connected in a daisy chain. Expansion becomes easier.

〔Example〕

Hereinafter, embodiments of the present invention will be described in detail based on the drawings.

FIG. 1 shows the configuration of a memory board to which the memory board allocation method of the present invention is applied and the connection relationship between the memory boards. Further, FIG. 2 shows the overall configuration of an embodiment of the present invention.

In FIG. 2, an information processing system to which the memory board allocation method of the present invention is applied, for example a personal computer, has a CPU 21 that performs overall control and processing.
1, and three memory boards 231 each containing a built-in memory for storing data and programs processed by the CPU 211.
．． 241, 251, and an address decoder 221 that generates an address designation signal for selecting a memory board to be used by the CPU 211.

The personal computer also includes a keyboard 265 for inputting data and instructions, a display 263 for displaying data and processing results, and a keyboard 265 for inputting data and instructions.
65 and display 263, a disk device 273 for holding programs and data when the power is turned off, and a disk device 273.
and a disk control section 271 that controls the.

CPU211. Memory board 231, 241° 251,
I10 adapter 261. The disk control unit 271 is connected via an address bus 291 and a data bus 293. Further, address data is introduced to the address decoder 221 via the address bus 291, and the output of the address decoder 221 is supplied to the memory board 231. The memory boards 231, 241, and 251 are connected in a daisy chain, and the signal supplied from the address decoder 221 to the memory board 231 is supplied to the memory boards 241, 251 in order.

Further, the I10 adapter 261 is connected to a display 263 and a keyboard 265. Disk control unit 2
71 is connected to a disk device 273.

Now, assume that the capacity of the memory board 231 is 128 bytes, the capacity of the memory board 241 is 64 bytes, and the capacity of the memory board 251 is 256 bytes.

The address decoder 221 receives the 16th bit (Al4) to the 18th bit (AIs) of the address bus 291.
The 3-bit data up to
, , negative logic) is obtained.

The table below shows the correspondence between input and output data of the address decoder 221.

The 8-bit data (Vd.~ππ,) output from the address decoder 221 described above is first sent to the memory board 23.
1 (see Figure 1).

The lower 2-bit data πT6, [1 of the 8-bit data input to the memory board 231 is the OR gate 1
A negative logic signal is input to each of the two input terminals of 31.

The output of OR gate 131 is used to determine whether memory board 231 is valid.

Follow me, signal π-ding. Alternatively, when either one of the signals ππ1 is “0”, the memory board 231 is selected. Note that in the memory board 231, bits 0 to 15 of the address data via the address bus 291 are selected.
Since up to 64 bytes of memory space can be specified by up to 64 bits, those address data and signals π
Ding. .

In combination with πd, it is possible to address 128 bytes.

Further, the signals after the signal π are output from the memory board 231 after being shifted by the signal line segments (πτ0 and π71) used to determine whether the memory board 231 is valid.

For example, signal π-ding. The terminal into which is input is the O-th input terminal,
If the terminal into which the signal n is input is the first input terminal, the 0th output terminal corresponding to the Oth input terminal and the second input terminal are connected, and the signal ππ2 is output from the 0th output terminal. .

From the first output terminal onwards, signals ππ2. MT4+
Outputs... Further, the fixed data "°1" is output from the sixth output terminal and the seventh output terminal.

Similarly, the memory board 241 determines whether or not the memory board 241 is valid based on the signal Vπ2 input to the 0th input terminal, and outputs the signal Vπ and subsequent signals after shifting the signal by two times. Fixed data "1" is output from the seventh output terminal.

Next, in the memory board 251, the four signals V-d, ~ V-d, input in order from the 0th input terminal are sent to the OR gate 15.
1 (negative logic), and it is determined whether the memory board 251 is valid or not based on the output of the OR gate 151. From the output terminal of the memory board 251, the four signals π, .about.f are shifted and the signals ππ and subsequent signals are output. Fixed data "1" is output from the four output terminals from the fourth output terminal to the seventh output terminal (as a result, all signal terminals after the first signal terminal except the O-th signal terminal Fixed data “1” is output).

Note that all address data including 3-bit data from the 16th bit to the 18th bit of the address data introduced into the address decoder 221 is input in parallel to all memory boards (memory boards 231, 241, 251), In a memory board that has been validated by the above-described determination operation, it is used as a memory chip select signal or address designation data.

FIG. 3 shows the address space when each memory board is set as shown in FIG.

The CPU 211 sends address data “000001(” to “IFFFFH” (H is 16) via the address bus 291.
When outputting a subscript representing a decimal number, memory board 2
31 becomes valid, and the memory within the memory board 231 is addressed. Similarly, address data "20000H" to "2FFFFH" are used to address the memory in the memory board 241, and address data "30000H" to "'6FFFFH"
is used for addressing within the memory board 251.

In this way, for example, in the memory board 231, the input signal [. , π-dong, ... signal V-dong. The validity of the memory board 231 is determined using the signals V and , and the signal Vπ used for the determination. , [Output by shifting the signal by 1 minute. By connecting such memory boards in a daisy chain, it becomes possible for the CPU 211 to access the memory in any memory board.

According to the wooden sword method, there is no need to set switches etc.
Furthermore, since it is sufficient to simply insert the memory board into the slot without being aware of the memory address, it is possible to easily add memory boards and reduce erroneous operations.

Note that the memory boards 231, 241, and 251 used in the embodiment of the present invention described above may be arranged in any order as long as they are connected in a daisy chain.

〔Effect of the invention〕

As described above, according to the present invention, a plurality of addressing signals input to a memory board are shifted by a signal line corresponding to the capacity of the memory board and outputted, and a plurality of memory boards are connected in a daisy chain. This is extremely useful in practical terms because it facilitates the addition of memory boards.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of a memory board in an embodiment to which the memory board allocation method of the present invention is applied, Fig. 2 is an overall configuration diagram of an embodiment of the present invention, and Fig. 3 is an explanatory diagram of a memory map of the embodiment. It is. In the figure, 131.151 is the OR gate, and 211 is the CPU. 221 is the address decoder, 231, 241.251 is the memory board, 261 is I1
0 adapter, 263 a display, 265 a keyboard, 271 a disk control unit, 273 a disk device, 291 an address bus, and 293 a data bus. Patent Applicant: PfN Co., Ltd.

Claims (2)

[Claims] (1) In a memory board allocation method for a device equipped with multiple memory boards connected in a daisy chain, one memory board among the multiple memory boards is introduced with multiple addressing signals that designate a memory area of a predetermined capacity. and determines whether or not the built-in memory is valid based on some of the addressing signals, and
An allocation method for a memory board, characterized in that the addressing signal is shifted by a signal line corresponding to the capacity of the memory and output. (2) A certain memory board among the plurality of memory boards outputs addressing signals other than the addressing signal used to determine whether the built-in memory is valid or not, shifted by the addressing signal used for the determination. The memory board allocation method according to claim 1, characterized in that: