JPH02503124A - 周辺装置コントローラ - Google Patents

周辺装置コントローラ

Info

Publication number
JPH02503124A
JPH02503124A JP63508087A JP50808788A JPH02503124A JP H02503124 A JPH02503124 A JP H02503124A JP 63508087 A JP63508087 A JP 63508087A JP 50808788 A JP50808788 A JP 50808788A JP H02503124 A JPH02503124 A JP H02503124A
Authority
JP
Japan
Prior art keywords
data
peripheral device
buffer memory
peripheral
data transfer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63508087A
Other languages
English (en)
Japanese (ja)
Other versions
JPH0519181B2 (cg-RX-API-DMAC7.html
Inventor
ギリダー　ランガスワミイ　パーササラシイ
リーベ　ジエフリイ　トーマス
Original Assignee
ユニシス　コーポレーシヨン
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US07/099,447 external-priority patent/US4905184A/en
Priority claimed from US07/099,448 external-priority patent/US4864532A/en
Application filed by ユニシス　コーポレーシヨン filed Critical ユニシス　コーポレーシヨン
Publication of JPH02503124A publication Critical patent/JPH02503124A/ja
Publication of JPH0519181B2 publication Critical patent/JPH0519181B2/ja
Granted legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/10—Program control for peripheral devices
    • G06F13/12—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor
    • G06F13/122—Program control for peripheral devices using hardware independent of the central processor, e.g. channel or peripheral processor where hardware performs an I/O function other than control of data transfer
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
    • G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
    • G06F3/0601—Interfaces specially adapted for storage systems
    • G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
    • G06F3/0655—Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
    • G06F3/0656—Data buffering arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Human Computer Interaction (AREA)
  • Bus Control (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
JP63508087A 1987-09-21 1988-09-12 周辺装置コントローラ Granted JPH02503124A (ja)

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US099,448 1987-09-21
US099,447 1987-09-21
US07/099,447 US4905184A (en) 1987-09-21 1987-09-21 Address control system for segmented buffer memory
US07/099,448 US4864532A (en) 1987-09-21 1987-09-21 Small computer systems interface--data link processor

Publications (2)

Publication Number Publication Date
JPH02503124A true JPH02503124A (ja) 1990-09-27
JPH0519181B2 JPH0519181B2 (cg-RX-API-DMAC7.html) 1993-03-16

Family

ID=26796114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63508087A Granted JPH02503124A (ja) 1987-09-21 1988-09-12 周辺装置コントローラ

Country Status (5)

Country Link
EP (1) EP0331720B1 (cg-RX-API-DMAC7.html)
JP (1) JPH02503124A (cg-RX-API-DMAC7.html)
KR (1) KR920007949B1 (cg-RX-API-DMAC7.html)
DE (1) DE3885266T2 (cg-RX-API-DMAC7.html)
WO (1) WO1989002633A1 (cg-RX-API-DMAC7.html)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0398523A3 (en) * 1989-05-19 1991-08-21 Hitachi, Ltd. A device for data i/o and execution support in digital processors
EP0412269A3 (en) * 1989-08-11 1992-02-26 International Business Machines Corporation Channel and extender unit operable with byte mode or non-byte mode control units
JP4524912B2 (ja) * 2000-12-20 2010-08-18 セイコーエプソン株式会社 端末装置及びその制御方法

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4423480A (en) * 1981-03-06 1983-12-27 International Business Machines Corporation Buffered peripheral system with priority queue and preparation for signal transfer in overlapped operations
US4644463A (en) * 1982-12-07 1987-02-17 Burroughs Corporation System for regulating data transfer operations

Also Published As

Publication number Publication date
KR920007949B1 (ko) 1992-09-19
KR890702154A (ko) 1989-12-23
DE3885266T2 (de) 1994-02-17
DE3885266D1 (de) 1993-12-02
WO1989002633A1 (en) 1989-03-23
EP0331720A1 (en) 1989-09-13
EP0331720B1 (en) 1993-10-27
JPH0519181B2 (cg-RX-API-DMAC7.html) 1993-03-16

Similar Documents

Publication Publication Date Title
US4905184A (en) Address control system for segmented buffer memory
US4864532A (en) Small computer systems interface--data link processor
US6564271B2 (en) Method and apparatus for automatically transferring I/O blocks between a host system and a host adapter
WO1992015053A1 (en) Data transfer within a data storage subsystem
JP2001051802A (ja) ディスク記憶システムの論理セクタと物理セクタを揃える回路
US6148366A (en) Storage system which transfers a command and data corresponding to said command subsequent to said command
JPS62119626A (ja) 磁気デイスクの多重制御方式
US5734918A (en) Computer system with an input/output processor which enables direct file transfers between a storage medium and a network
JPH02503124A (ja) 周辺装置コントローラ
CN1155895C (zh) 管理对scsi总线的再选择的方法和系统
JP2523715B2 (ja) 磁気ディスク装置
US6112278A (en) Method to store initiator information for SCSI data transfer
US20030145133A1 (en) SCSI - handling of I/O scans to multiple LUNs during write/read command disconnects
JPH01309117A (ja) 磁気デイスク装置
JPS63180153A (ja) キヤツシユ記憶のラインバツク制御方式
JP2003005916A (ja) ディスク制御装置、および、そのデータアクセス方法
JPH06301607A (ja) マルチアクセスｉ／ｏ制御方式
JPH06259374A (ja) 入出力バス制御装置
JPH07281994A (ja) バス中継装置
JPH0578859B2 (cg-RX-API-DMAC7.html)
JPS6167124A (ja) 磁気デイスク制御装置
JP3184406B2 (ja) ディスクアレイ装置
JPH0836542A (ja) Ｄｍａコントローラ
JPH04326163A (ja) 記憶装置の制御装置
JPH0235515A (ja) バス管理方法