JPH0248142B2 - - Google Patents
Info
- Publication number
- JPH0248142B2 JPH0248142B2 JP58184986A JP18498683A JPH0248142B2 JP H0248142 B2 JPH0248142 B2 JP H0248142B2 JP 58184986 A JP58184986 A JP 58184986A JP 18498683 A JP18498683 A JP 18498683A JP H0248142 B2 JPH0248142 B2 JP H0248142B2
- Authority
- JP
- Japan
- Prior art keywords
- region
- wiring
- polysilicon
- memory cell
- doped
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 27
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 13
- 239000000758 substrate Substances 0.000 claims description 11
- 239000004065 semiconductor Substances 0.000 claims description 9
- 230000000295 complement effect Effects 0.000 claims description 4
- 238000006880 cross-coupling reaction Methods 0.000 claims description 2
- 238000009792 diffusion process Methods 0.000 description 11
- 239000010410 layer Substances 0.000 description 10
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000000034 method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 3
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000969 carrier Substances 0.000 description 2
- 238000005468 ion implantation Methods 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052698 phosphorus Inorganic materials 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000005260 alpha ray Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 238000005234 chemical deposition Methods 0.000 description 1
- 238000004140 cleaning Methods 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000007257 malfunction Effects 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 239000005368 silicate glass Substances 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
- 239000002344 surface layer Substances 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8232—Field-effect technology
- H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
- H01L21/8238—Complementary field-effect transistors, e.g. CMOS
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Semiconductor Memories (AREA)
- Semiconductor Integrated Circuits (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
Description
【発明の詳細な説明】
この発明は相補型MOS半導体装置（以下
CMOSと略称する）に関する。[Detailed Description of the Invention] This invention relates to a complementary MOS semiconductor device (hereinafter referred to as
(abbreviated as CMOS).
従来のCMOS製造法では、一つの半導体基板
上にｐチヤネル及びｎチヤネルのソース・ドレイ
ン領域をそれぞれ形成するためにｐ型拡散用マス
クとｎ型拡散用のマスクを交互に使用して、互い
に異なる領域へのドープ時にはCVD法（気相化
学析出法）によるSiO2（二酸化シリコン）膜の上
記マスクを被着することで異なる不純物が他の領
域の半導体基板にドープされるのを防止する方法
がとられている。この方法によればポリシリコ
ン・ゲートと共に形成した他のポリシリコン配線
は、ソース・ドレイン部拡散と同時に不純物ドー
プが行なわれるため不純物が高濃度にドープさ
れ、低抵抗の導体部として利用される。ところ
で、MOSICにおいては回路構成の一部として高
抵抗素子を必要とする場合、この高抵抗素子のた
めに従来は不純物ドープのないポリシリコン形成
工程を別に用意するため工程数が増加することに
なつた。 In conventional CMOS manufacturing methods, p-type diffusion masks and n-type diffusion masks are alternately used to form p-channel and n-channel source/drain regions on a single semiconductor substrate. When doping a region, there is a method to prevent different impurities from being doped into the semiconductor substrate in other regions by applying the above mask of SiO 2 (silicon dioxide) film by CVD (vapor phase chemical deposition). It is taken. According to this method, the other polysilicon wiring formed together with the polysilicon gate is doped with impurities at the same time as the source/drain region diffusion, so that it is doped with impurities at a high concentration and is used as a low-resistance conductor. By the way, in MOSICs, when a high resistance element is required as part of the circuit configuration, a separate polysilicon formation process that is not doped with impurities has traditionally been prepared for this high resistance element, which increases the number of steps. Ta.
本発明においては前記ｐ型及びｎ型拡散用のマ
スクを積極的に利用し、どちらの不純物もドープ
されないポリシリコン領域をつくり、それを高抵
抗素子として利用しようとするものである。 The present invention actively utilizes the masks for p-type and n-type diffusion to create a polysilicon region that is not doped with either impurity, and uses it as a high-resistance element.
したがつて、本発明の目的はCMOSICに適合
したスタテイツク・ランダム・アクセス・メモリ
（SRAMと略称）を提供することにある。 SUMMARY OF THE INVENTION It is therefore an object of the present invention to provide a static random access memory (abbreviated as SRAM) that is compatible with CMOSICs.
本発明によれば、ｎチヤンネルMOSFETのド
レインにポリシリコン抵抗を接続した直列回路の
一対を交差結合して成るフリツプフロツプ回路
と、一対の前記MOSFETのドレインにそれぞれ
接続される他の一対のｎチヤンネルMOSFETと
を有するメモリセルを、相補型MOS半導体集積
回路装置を構成する半導体基板主面にpn接合で
区画されたｐ型ウエル領域内に形成して成り、前
記ポリシリコン抵抗の一端を前記メモリセル構成
に接続するための配線およびそのポリシリコン抵
抗の他端を電源に接続するための配線は前記ポリ
シリコン抵抗と一体形成されたポリシリコン層か
ら成り、該ポリシリコン層は、高濃度ｎ型不純物
がドープされた配線用領域と、前記高濃度ｎ型不
純物がドープされない抵抗領域とを有して成るこ
とを特徴とする。 According to the present invention, there is provided a flip-flop circuit formed by cross-coupling a pair of series circuits in which polysilicon resistors are connected to the drains of n-channel MOSFETs, and another pair of n-channel MOSFETs each connected to the drains of the pair of MOSFETs. A memory cell having a structure of the memory cell is formed in a p-type well region defined by a pn junction on the main surface of a semiconductor substrate constituting a complementary MOS semiconductor integrated circuit device, and one end of the polysilicon resistor is connected to the memory cell structure. The wiring for connecting to the polysilicon resistor and the wiring for connecting the other end of the polysilicon resistor to the power supply are made of a polysilicon layer formed integrally with the polysilicon resistor, and the polysilicon layer is doped with high concentration n-type impurities. It is characterized by comprising a doped wiring region and a resistance region not doped with the high concentration n-type impurity.
以下、本発明を実施例にそつて具体的に説明す
る。 Hereinafter, the present invention will be specifically explained with reference to Examples.
第１図ａ〜ｊはｎ型Si基板上にｐチヤネル
MOSFETとｎチヤネルMOSFETを形成し、一
部に高抵抗回路を有するCMOSIC、例えばメモ
リセルの製造に本発明を適用した場合の工程図を
示す。 Figure 1 a to j shows a p channel on an n-type Si substrate.
A process diagram is shown in which the present invention is applied to the manufacture of a CMOSIC, such as a memory cell, in which a MOSFET and an n-channel MOSFET are formed, and a part of which has a high resistance circuit.
ａ n--型Si基板１を用意し、全面にｐ（リン）イ
オンの打込みを行う。次いで表面酸化膜
（SiO2）２を形成し、ホトレジスト３によるウ
エル窓開し、Ｂ（ボロン）イオン打込みを行う。An --- type Si substrate 1 is prepared, and p (phosphorus) ions are implanted into the entire surface. Next, a surface oxide film (SiO 2 ) 2 is formed, a well window is opened using a photoresist 3, and B (boron) ions are implanted.
ｂ ウエル拡散のための熱処理を行い、基板表面
層にn-層４とp-ウエル５を形成する。b Perform a heat treatment for well diffusion to form an n - layer 4 and a p - well 5 on the substrate surface layer.
ｃ 酸化膜２を全面除去し、洗浄後、新たに薄い
酸化膜６を形成し、次いでSi3N4膜７をデポジ
シヨンし、ホトレジスト８によりSi3N4膜を部
分的に除去する。c. The oxide film 2 is completely removed, and after cleaning, a new thin oxide film 6 is formed. Next, a Si 3 N 4 film 7 is deposited, and the Si 3 N 4 film is partially removed using a photoresist 8.
ｄ 全面にCVD膜９を形成し、ホトレジスト処
理によりp-ウエル側のCVDを取除いた後、Ｂ
イオン打込みを行う。d After forming the CVD film 9 on the entire surface and removing the CVD on the p - well side by photoresist treatment,
Perform ion implantation.
ｅ CVD膜９を取除いてn-基板側を露出すると
同時にp-ウエル側を新たなCVD膜１０で覆い、
ｐイオン打込みを行う。e Remove the CVD film 9 to expose the n -substrate side, and at the same time cover the p - well side with a new CVD film 10.
Perform p ion implantation.
ｆ 前記Si3N4膜をマスクとしてフイルド部に選
択酸化膜１１を形成すると同時に、この酸化膜
１１の下にｐ領域１２及びｎ領域１３を拡散す
る。このあと両面エツチを行つてSi3N4膜７及
び薄い酸化膜６を除去する。f Using the Si 3 N 4 film as a mask, a selective oxide film 11 is formed in the field portion, and at the same time, a p region 12 and an n region 13 are diffused under this oxide film 11. Thereafter, double-sided etching is performed to remove the Si 3 N 4 film 7 and the thin oxide film 6.
ｇ ゲート酸化膜１５を生成し、次いで、ポリSi
層１６をデポジシヨンし、ホトレジスト処理に
よりソース・ドレイン部を窓開する。このあと
ポリSi層１６に対し低濃度不純物イオン打込み
をかるく行う。g Gate oxide film 15 is formed, and then poly-Si
Layer 16 is deposited and the source/drain regions are opened by photoresist processing. Thereafter, low concentration impurity ions are lightly implanted into the poly-Si layer 16.
ｈ CVD酸化膜を形成し、ホトレジスト処理に
よりn-基板側を露出するp+マスク１７となし、
高濃度Ｂ拡散によりp+ソース、ドレイン１８
を形成する。h A CVD oxide film is formed, and a p + mask 17 is formed to expose the n - substrate side by photoresist processing,
P + source and drain 18 due to high concentration B diffusion
form.
ｉ p+マスク１７を取除き、p-ウエル側を露出
するn+マスク１９を形成、高濃度ｐ拡散によ
りn+ソース、ドレイン２０を形成する。これ
らの工程において、第２図に示すようにポリSi
層の一部にn+マスク（CVD酸化膜）１９ａが
残るようなパターンのホトマスクm1，m2を使
用し、このn+マスク１９ａによつてポリSi層の
一部は高抵抗部２１となつて残り、マスク１９
ａで覆われない部分１６は高濃度不純物ドープ
により低抵抗部となる。The i p + mask 17 is removed, an n + mask 19 exposing the p - well side is formed, and an n + source and drain 20 are formed by high concentration p diffusion. In these steps, as shown in Figure 2, poly-Si
Photomasks m 1 and m 2 with a pattern that leaves an n + mask (CVD oxide film) 19a in a part of the layer are used, and a part of the poly-Si layer is formed into a high resistance part 21 by this n + mask 19a. Remaining with age, mask 19
The portion 16 not covered by a becomes a low resistance portion due to high concentration impurity doping.
ｊ 全面にPSG（リン・シリケート・ガラス）膜
２２を形成し、N2アニールの後、コンタクト
部ホトエツチングを行い、次いでAl蒸着、配
線パターンマスクによるホトエツチングを行つ
てAl配線２３を完成する。j A PSG (phosphorus silicate glass) film 22 is formed on the entire surface, and after N2 annealing, the contact portion is photoetched, followed by Al evaporation and photoetching using a wiring pattern mask to complete the Al wiring 23.
第３図はこの発明の第４図の回路に対応するメ
モリセルの平面形状を示す。同図において、斜線
ハツチングを施した部分がポリSi層１６からなる
配線でその一部をMOSFET（Q1，Q2，Q3，Q4）
の各ゲートを構成する。又、破線でハツチングを
施した部分は高抵抗部（R1，R2）である。この
R1，R2は第５図に示すようなp+拡散マスクm1と
n+拡散マスクm2とを使用し、これらのマスクの
重複する部分mR1，mR2によつて不純物のドー
プされない高抵抗部をつくるものである。 FIG. 3 shows a planar shape of a memory cell corresponding to the circuit of FIG. 4 of the present invention. In the figure, the hatched area is the wiring made of poly-Si layer 16, and some of it is connected to MOSFETs (Q 1 , Q 2 , Q 3 , Q 4 ).
Configure each gate. Further, the hatched portions with broken lines are high resistance portions (R 1 , R 2 ). this
R 1 and R 2 are p + diffusion mask m 1 as shown in Figure 5.
n + diffusion mask m 2 is used, and the overlapping portions mR 1 and mR 2 of these masks create a high-resistance portion that is not doped with impurities.
本発明の構造によれば、高抵抗素子はメモリセ
ル配線のポリシリコン層と一体構造となるのでメ
モリセルの占有面積を低減できる。また、メモリ
セルはｐ型ウエル内に形成されるので、メモリセ
ルの低消費電力化すなわち低電流化のためにフリ
ツプフロツプ回路のポリシリコン抵抗素子を出来
る限り高抵抗化しても、半導体基板の周辺回路で
発生する好ましくないキヤリアや、α線照射によ
る好ましくないキヤリアのｐ型ウエル内へのリー
ケージを阻止でき、これによつてメモリセルの誤
動作を防止できる。 According to the structure of the present invention, the high resistance element has an integral structure with the polysilicon layer of the memory cell wiring, so that the area occupied by the memory cell can be reduced. Furthermore, since the memory cell is formed in a p-type well, even if the polysilicon resistance element of the flip-flop circuit is made as high as possible in order to reduce the power consumption or current of the memory cell, the peripheral circuit of the semiconductor substrate It is possible to prevent the leakage of undesirable carriers generated by irradiation and undesirable carriers caused by α-ray irradiation into the p-type well, thereby preventing malfunction of the memory cell.
上記実施例で明らかなように上記例によればマ
スクパターンの一部を変更するのみで、新たな工
程を付加することなくCMOSに高抵抗素子を形
成することができる。 As is clear from the above embodiment, according to the above example, a high resistance element can be formed in CMOS by only changing a part of the mask pattern and without adding any new process.
第１図ａ〜ｊはこの発明の一実施例の工程図、
第２図はこの発明の原理説明のための断面図、第
３図はこの発明を応用したメモリセルの平面図、
第４図は第３図に等価の回路図、第５図は第３図
のメモリセル装置の際にp+拡散及びn+拡散に使
用するマスクの形状を示す平面図である。
１……n--型Si基板、２……表面酸化膜、３…
…ホトレジスト、４……n-層、５……p-ウエル、
６……酸化膜、７……Si3N4膜、８……ホトレジ
スト、９……CVD膜、１０……CVD膜、１１…
…選択酸化膜、１２……ｐ領域、１３……ｎ領
域、１５……ゲート酸化膜、１６……ポリSi層、
１７……p+マスク、１８……p+ソース、ドレイ
ン、１９……n+マスク、２０……n+ソース、ド
レイン、２１……高抵抗部、２２……PSG膜、
２３……Al配線。
Figures 1a to 1j are process diagrams of an embodiment of this invention.
FIG. 2 is a cross-sectional view for explaining the principle of this invention, and FIG. 3 is a plan view of a memory cell to which this invention is applied.
4 is a circuit diagram equivalent to FIG. 3, and FIG. 5 is a plan view showing the shape of a mask used for p + diffusion and n + diffusion in the memory cell device of FIG. 3. 1... n - type Si substrate, 2... surface oxide film, 3...
...photoresist, 4...n - layer, 5...p - well,
6...Oxide film, 7... Si3N4 film , 8...Photoresist, 9...CVD film, 10...CVD film, 11...
... selective oxide film, 12 ... p region, 13 ... n region, 15 ... gate oxide film, 16 ... poly-Si layer,
17...p + mask, 18...p + source, drain, 19...n + mask, 20...n + source, drain, 21...high resistance part, 22...PSG film,
23...Al wiring.
Claims (1)
リコン抵抗を接続した直列回路の一対を交差結合
して成るフリツプフロツプ回路と、一対の前記
MOSFETのドレインにそれぞれ接続される他の
一対のｎチヤンネルMOSFETとを有するメモリ
セルを、相補型MOS半導体集積回路装置を構成
する半導体基板主面にpn接合で区画されたｐ型
ウエル領域内に形成して成り、前記ポリシリコン
抵抗の一端を前記メモリセル構成に接続するため
の配線およびそのポリシリコン抵抗の他端を電源
に接続するための配線は前記ポリシリコン抵抗と
一体形成されたポリシリコン層から成り、該ポリ
シリコン層は、高濃度ｎ型不純物がドープされた
配線用領域と、前記高濃度ｎ型不純物がドープさ
れない抵抗領域とを有して成ることを特徴とする
相補型MOS半導体集積回路装置。 ２ 前記ポリシリコン抵抗の一端は、前記ポリシ
リコン層の配線領域の高濃度ｎ型不純物ドープ領
域によつて、前記メモリセルを構成する前記ｎチ
ヤンネルMOSFETのドレイン領域に接続されて
いることを特徴とする特許請求の範囲第１項記載
の相補型MOS半導体集積回路装置。[Claims] 1. A flip-flop circuit formed by cross-coupling a pair of series circuits in which a polysilicon resistor is connected to the drain of an n-channel MOSFET;
A memory cell having another pair of n-channel MOSFETs each connected to the drain of the MOSFET is formed in a p-type well region defined by a p-n junction on the main surface of a semiconductor substrate constituting a complementary MOS semiconductor integrated circuit device. The wiring for connecting one end of the polysilicon resistor to the memory cell structure and the wiring for connecting the other end of the polysilicon resistor to the power supply are formed of a polysilicon layer integrally formed with the polysilicon resistor. , wherein the polysilicon layer has a wiring region doped with a high concentration n-type impurity and a resistance region not doped with the high concentration n-type impurity. circuit device. 2. One end of the polysilicon resistor is connected to the drain region of the n-channel MOSFET constituting the memory cell through a heavily doped n-type impurity region in the wiring region of the polysilicon layer. A complementary MOS semiconductor integrated circuit device according to claim 1.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58184986A JPS59112643A (en) | 1983-10-05 | 1983-10-05 | Complementary mis semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58184986A JPS59112643A (en) | 1983-10-05 | 1983-10-05 | Complementary mis semiconductor integrated circuit device |
Related Parent Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2022177A Division JPS53105990A (en) | 1977-02-28 | 1977-02-28 | Manufacture of mos semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59112643A JPS59112643A (en) | 1984-06-29 |
| JPH0248142B2 true JPH0248142B2 (en) | 1990-10-24 |
Family
ID=16162794
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58184986A Granted JPS59112643A (en) | 1983-10-05 | 1983-10-05 | Complementary mis semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59112643A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0821629B2 (en) * | 1988-11-08 | 1996-03-04 | ヤマハ株式会社 | Manufacturing method of integrated circuit device |
-
1983
- 1983-10-05 JP JP58184986A patent/JPS59112643A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59112643A (en) | 1984-06-29 |
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