JPH0821629B2 - Manufacturing method of integrated circuit device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a method for manufacturing an integrated circuit device (hereinafter referred to as a MOS type IC) including a MOS type transistor, and in particular, an MOS type transistor having an LDD (Lighty Doped Drain) structure. The present invention also relates to a technique for forming a resistance element having a high resistance value when the wiring has a salicide (Self-Aligned Silicide) structure.

SUMMARY OF THE INVENTION According to the present invention, an upper surface of a polysilicon layer for resistance is oxidized to form an oxide film, and an impurity mask layer is formed on the oxide film so as to overlap a portion of the polysilicon layer to be a resistor. The impurity introduction process for forming the source / drain is performed in the state where the gates are arranged, and the oxide film is selectively etched and removed by using the impurity mask layer as an etching mask to expose a portion of the polysilicon layer that is to be a terminal. By siliciding the formed portion, a high resistance element can be realized by a simple process.

[Prior Art] Conventionally, as a MOS type IC (especially LSI) in which a MOS transistor has an LDD structure and a wiring has a salicide structure,
The one shown in the figure is known.

In FIG. 9, a field insulating film 2 having an active region placement hole 2A is formed on the surface of a semiconductor substrate 1 made of, for example, P-type silicon by a selective oxidation process. Then, after forming the gate insulating film 3 on the silicon surface in the active region arranging hole 2A by the oxidation treatment, polysilicon is deposited on the upper surface of the substrate and the deposited layer is patterned by the photolithography treatment to form the gate polysilicon layer. 4G and a resistor polysilicon layer 4R are formed on the gate insulating film 3 and the field insulating film 2, respectively.

Next, the N ⁻ type source region 5S and the N ⁻ type drain region 5D are formed by selective ion implantation using the gate polysilicon layer 4G and the field insulating film 2 as a mask. Then, for example, silicon oxide is deposited on the upper surface of the substrate and then anisotropic etching is performed to form side spacers 6A to 6D on both sides of each of the polysilicon layers 4G and 4R. The etching process at this time also selectively removes the gate insulating film 3 to expose the silicon surface on which the N ⁺ type regions 7S and 7D are to be formed.

After that, a selective ion implantation process using the gate portion including the gate polysilicon layer 4G and the side spacers 6A and 6B and the field insulating film 2 as a mask is performed to form the N ⁺ type source region 7S.
And an N ⁺ type drain region 7D is formed. Then, after depositing a silicide forming metal such as Ti on the upper surface of the substrate, a heat treatment for silicidation is performed, and then the unreacted silicide forming metal is removed by etching to form the N ⁺ type source region 7S,
Silicide layers 8S and 8S are formed on the N ⁺ type drain region 7D, the gate polysilicon layer 4G and the resistor polysilicon layer 4R, respectively.
Form D, 8G and 8R.

[Problems to be Solved by the Invention] According to the above-described conventional technique, the resistance polysilicon layer 4R is similar to the gate polysilicon layer 4G in the ion implantation process for forming the N ⁺ type regions 7S and 7D. Since the N-type determining impurity is highly doped, the resistivity is reduced.
Further, since the silicide layer 8R is formed on the resistor polysilicon layer 4R, the resistance value of the resistor formed of these layers 4R and 8R becomes considerably small. Therefore, for example, as a high resistance element required for an input / output protection circuit, a linear circuit, etc.
The use of the resistor composed of 4R and 8R has the disadvantage that the occupied area increases (decrease in the degree of integration) in addition to increasing the length.

As a method to eliminate such inconvenience, N ⁺ type region
In the impurity introduction process for forming 7S and 7D, the portion of the polysilicon layer 4R that is to be the resistor is covered with an impurity mask layer, the silicide layer 8R is formed, and then the silicide layer 8R is added to the resistance of the polysilicon layer 4R. A method of selectively removing the etch corresponding to the body part can be considered. However, according to such a method, the selective etching step for removing the silicide is increased by one step, and the displacement of the etching mask is added in addition to the displacement of the impurity mask layer, which increases the variation in the resistance value. There is a problem that the degree of integration is lowered because it is necessary to secure a mask alignment margin.

An object of the present invention is to make it possible to manufacture a high resistance element with less variation in a simple process and to improve the degree of integration.

[Means for Solving the Problems] A method of manufacturing an integrated circuit device according to the present invention is a field insulating film, a gate oxide film, a polysilicon layer for a gate and a resistor, a source with a low impurity concentration on a semiconductor substrate by a usual method. And a drain region, side spacers on both sides of each polysilicon layer, etc. are formed, and then a first oxide film and a second oxide film are formed on the gate polysilicon layer and the resistor polysilicon layer by an oxidation process, Source and drain regions of high impurity concentration are formed by performing a selective impurity introduction process in a state where an impurity mask layer is arranged on the second oxide film so as to overlap a portion of the resistor polysilicon layer to be a resistor. Then, the first oxide film and the second oxide film are selectively removed by a selective etching process using the impurity mask layer as an etching mask. After removing the mask layer, the side spacer and the remaining portion of the second oxide film are used as a mask to form a silicide layer on the gate polysilicon layer and on the portion of the resistor polysilicon layer to be the terminal, respectively. It was done.

[Operation] According to the manufacturing method of the present invention, the impurity mask layer is arranged in the portion of the resistor polysilicon layer to be the resistor when the impurity is introduced for forming the source and drain regions of high impurity concentration. Since no impurities are introduced, the portion to be the resistor is maintained in the high resistance state. Further, since the remaining portion of the second oxide film acts as a mask on the portion of the resistor polysilicon layer that is to be the resistor, the silicide layer is not formed, and the portion that is to be the resistor is in the high resistance state. Maintained at. Therefore, it is not necessary to form the resistance polysilicon layer particularly long to realize the high resistance element, and the occupied area can be reduced.

Further, since only the oxidation step is added to the conventional process and the selective etching process after the formation of the silicide layer is unnecessary, the process becomes simple.

In addition, since the impurity mask layer is also used as an etching mask, in the resistance polysilicon layer, the terminal portion is arranged in a self-aligned manner with respect to the resistor portion, which reduces variations in resistance value. In addition, the degree of integration can be improved.

[Embodiment] FIGS. 1 to 7 show a MOS according to an embodiment of the present invention.
A method of manufacturing a type IC will be described, and steps (1) to (7) corresponding to each drawing will be sequentially described.

(1) After the P-type well region 11 is formed on the surface of the semiconductor substrate 10 made of N-type silicon, the active region arranging hole 12A corresponding to a part of the well region 11 and a part of the N-type semiconductor surface are formed. The field insulating film 12 made of silicon oxide and having the active region arranging holes 12B is formed by selective oxidation. Then, the semiconductor surfaces in the active area placement holes 12A and 12B are thermally oxidized to form gate insulating films 14 and 16 made of silicon oxide, and then polysilicon is deposited on the upper surface of the substrate by a CVD (Chemical Vapor Devolution) method. In addition, the deposited layers are patterned by photolithography to form gate polysilicon layers 18 and 20 on the gate insulating films 14 and 16, respectively, and resistor polysilicon on the field insulating film 12. Form layer 22. Polysilicon layer 18,20,
22 may optionally be doped with N-type determining impurities during or after deposition, for example. The impurity concentration at this time is
It is determined according to the resistance value required when using polysilicon as the resistance.

After forming the polysilicon layer, a resist layer is formed on the upper surface of the substrate so as to cover the active region disposing holes 12B and the polysilicon layer 22 and expose the active region disposing holes 12A, and the resist layer and the field insulating film 12 are formed. And an N-type determining impurity (for example, phosphorus or arsenic) is selectively ion-implanted using the gate polysilicon layer 18 as a mask.
N ⁻ type source region 24 and N ⁻ type drain region 26 are well regions
Form within 11. Then, after removing the resist layer, a new resist layer is formed on the upper surface of the substrate so as to cover the active region disposing holes 12A and the polysilicon layer 22 and expose the active region disposing holes 12B, and this resist layer, Field insulating film 12 and gate polysilicon layer 20
A P ⁻ type source region 28 and a P ⁻ type drain region 30 are formed by a selective ion implantation process of a P type determining impurity (for example, boron) with and as a mask. After that, the resist layer is removed, and then CV of silicon oxide is used as an example on the upper surface of the substrate.
The side spacers 32A to 32F are formed on both sides of each of the polysilicon layers 18, 20 and 22 by depositing by the D method and etching back the deposited layer, and with each surface of the N ⁻ type regions 24 and 26. , P ^- type regions 28 and 30 and polysilicon layer 1
Expose the upper surface of 8,20,22.

(2) Next, by oxidation treatment, oxide films 34A and 34B are formed on the surfaces of the N ⁻ type regions 24 and 26, and oxide films 34C and 34C are formed on the surfaces of the P ⁻ type regions 28 and 30, respectively.
34D, and an oxide film 34E, 3 on the upper surface of the polysilicon layers 18,20,22.
Form 4F and 34G respectively. All of these oxide films 34A to 34G are made of silicon oxide.

(3) Next, the active area placement hole 12B is formed on the upper surface of the substrate.
And a resist layer 36 as an impurity mask layer so as to cover the portion of the polysilicon layer 22 to be the resistor and expose the oxide film portion and the active region arrangement hole 12A on the portion 22a of the polysilicon layer 22 to be the terminal. The resist layer 36, the field insulating film 12, the oxide film 34E, the polysilicon layer 18, and the side spacers 32A and 32B on both sides thereof are formed.
The N ⁺ -type source region 38 and the N ⁺ -type drain region 40 are connected to each other by the N-type determining impurity selective ion implantation process using the gate portion including the N ^- type source region 24 and the N ⁻ -type drain region 26 as a mask. Is formed adjacent to. By the ion implantation process at this time, the portions 22a of the gate polysilicon layer 18 and the resistor polysilicon layer 22 to be the terminals are also doped with the N-type determining impurity, and the polysilicon layer 18 and the portions 22a to be the terminals are formed.
Both have low resistance.

(4) Next, selective etching of silicon oxide is performed using the resist layer 36 as a mask to form N ⁺ type regions 38, 4
0 surface and polysilicon layer 18 and part 2 to be a terminal 2
Expose each upper surface of 2a. After that, the resist layer 36 is removed.

(5) Next, on the top surface of the substrate, the active area placement hole 12A is formed.
A resist layer 42 is formed so as to cover the polysilicon layer 22 and expose the active region disposition holes 12B, and the resist layer 42, the field insulating film 12, the oxide film 34G,
Polysilicon layer 20 and side spacers 32C on both sides thereof,
The P ⁺ type source region 44 and the P ⁺ type drain region 46 are formed into the P ⁻ type source region 28 and the P ⁻ type drain region 30, respectively, by the selective ion implantation process of the P type determining impurity using the gate portion including 32D as a mask. Form adjacently.

(6) Next, using the resist layer 42 as a mask, selective etching of silicon oxide is performed to form P ⁺ -type regions 44, 4
Each surface of 6 and the upper surface of the polysilicon layer 20 are exposed. After that, the resist layer 42 is removed. The etching process shown in FIGS. 4 and 6 may be either wet etching or dry etching.

(7) Next, for example, Ti is deposited as a silicide forming metal on the upper surface of the substrate by a sputtering method. Then, heat treatment for silicidation is performed. At this time, the field insulating film 12, the gate insulating films 14 and 16, the side spacers 32A to 32F.
Also, the oxide film 34F acts as a mask for preventing the silicidation reaction. After this, unreacted Ti is removed by etching.
As a result, the silicide layers 48A and 48B are formed on the N ⁺ type regions 38 and 40.
However, the silicide layers 48C and 48D are formed on the P ⁺ type regions 44 and 46, the silicide layers 48E and 48G are formed on the polysilicon layers 18 and 20, and the silicide layers 48E and 48G are formed on the portion 22a of the polysilicon layer 22 which is to be a terminal. Layer 4
8F is formed respectively.

FIG. 8 shows an example of the resistance portion obtained by the above method. The resistance portion of the polysilicon layer 22 (corresponding to the polysilicon portion under the oxide film 34F in FIG. 7) is
It has a U-shaped plane pattern. This resistor part is
The resist layer 36 prevents the N-type determining impurities from being doped in the ion implantation step of FIG. 3 and the remaining portion of the oxide film 34F prevents the silicidation in the silicidation step of FIG. It is like this. In addition, terminal portions 48F and 48F 'which are continuous at both ends of the resistor portion (corresponding to the polysilicon portion 22a in FIG. 7)
Is a gate electrode layer (polysilicon layer 18 and silicide layer
Similar to the (48E stack), it is composed of a stack of polysilicon and silicide, and has a low resistance due to the doping of N-type determining impurities into polysilicon in the ion implantation step of FIG. Side spacers 32E and 32F are formed on both sides of the polysilicon layer from below the terminal portion 48F to below the terminal portion 48F 'through the resistor portion.

According to the manufacturing method described above, it is possible to coexist a high resistance element as shown in FIG. 8 and a low resistance element having the same structure as the gate electrode layer on the same substrate.

[Effects of the Invention] As described above, according to the present invention, it is possible to realize a high resistance element in a simple process, and it is possible to reduce the variation in resistance value and improve the integration degree by using a self-alignment process. It is possible to obtain the effect that the high performance of the MOS type LSI and the cost reduction can be achieved.

[Brief description of drawings]

1 to 7 show a MOS type I according to an embodiment of the present invention.
FIG. 8 is a plan view showing an example of a resistor portion, and FIG. 9 is a cross-sectional view showing a conventional MOS IC. 10 ... Semiconductor substrate, 11 ... Well region, 12 ... Field insulating film, 14,16 ... Gate insulating film, 18, 20 ... Gate polysilicon layer, 22 ... Resistor polysilicon layer, 24, 26,
28,30 …… Low-concentration source / drain regions, 32A to 32F ……
Side spacers, 34A-34G ... Oxide film, 36, 42 ... Resist layer, 38, 40, 44, 46 ... High-concentration source / drain regions, 48A-48G, 48F '... Silicide layer.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H01L 21/822 27/04 27/088 29/78 H01L 29/78 301 P

Claims (1)

[Claims] 1. A step of: (a) forming a field insulating film having a desired active region arranging hole on a surface of a semiconductor substrate; and (b) forming a gate insulating film on a semiconductor surface in the active region arranging hole. (C) forming a gate polysilicon layer on the gate insulating film and forming a resistance polysilicon layer on the field insulating film; and (d) the field insulating film and the gate. Forming source and drain regions of low impurity concentration on the semiconductor surfaces on one side and the other side of the gate polysilicon layer by selective impurity introduction treatment using the polysilicon layer as a mask, and (e) for the gate Insulating side spacers are formed on both sides of the polysilicon layer and on both sides of the resistor polysilicon layer, and each of the polysilicon side spacers is formed. Exposing the upper surface of the recon layer, and (f) oxidizing the exposed upper surface of the gate polysilicon layer and the exposed upper surface of the resistor polysilicon layer to form first and second oxide films, respectively. And (g) the first oxide film and the gate in a state where an impurity mask layer is arranged on the second oxide film so as to overlap a portion of the resistor polysilicon layer to be a resistor. Of the low impurity concentration by selectively introducing the conductivity determining impurity into the semiconductor surface in the active region arrangement hole using the gate portion including the polysilicon layer for use and side spacers on both sides thereof and the field insulating film as a mask. Forming a high impurity concentration source and drain region adjacent to the source and drain regions, respectively, and (h) using the impurity mask layer as an etching mask By selective etching, the first oxide film is removed to expose the upper surface of the gate polysilicon layer, and the second oxide film is selectively removed to serve as terminals of the resistor polysilicon layer. Exposing the upper surface of the desired portion, and (i) after removing the impurity mask layer, the upper surface of the polysilicon layer for gate and the resistance using the side spacer and the remaining portion of the second oxide film as a mask. Integrated circuit device including a step of forming first and second silicide layers by reacting a silicide-forming metal and removing an unreacted silicide-forming metal on an upper surface of a portion of the polysilicon layer for use as a terminal, respectively. Manufacturing method.