JPH0513717A - Semiconductor integrated circuit device and its manufacture - Google Patents

Abstract

PURPOSE:To provide a manufacture of a semiconductor integrated circuit device which has memory cell structure within, being excellent in the resistance to the soft error due to an alpha ray and is stable in operation, while maintaining the pattern layout of a conventional logic circuit part and the performance. CONSTITUTION:P-type impurities are introduced from the openings, which are provided in one part each inside the region of the region of the first n-well 5 formed on a p-type semiconductor substrate 1 and outside the region of the first n-well 5, so as to form a p-type conductive layer 10, and the p-type semiconductor substrate 1 is oxidized to form a thick oxide film 12 in the opening, and then n-type impurities are introduced from the part other than the thick oxide film 12 to form an n-type conductive layer 13, and the entire p-type semiconductor substrate 1 is heat-treated to diffuse them inward, whereby those are made a p-well 16 and the second n-well 15, respectively.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device and a method of manufacturing the same, and in particular, it has a built-in memory cell formed by a flip-flop circuit having a resistance element having a memory cell structure excellent in soft error resistance due to α rays as a load. It concerns a microprocessor.

[0002]

2. Description of the Related Art FIG. 6 is a sectional view showing a conventional semiconductor integrated circuit device, in which 101 is a P-type semiconductor substrate and 11 is a semiconductor device.
4 is a P well, 115 is an N well, 116 is a thick oxide film for element isolation, 117 is a p-type conductive layer, 119 is a gate electrode, 120 is polycrystalline silicon, 121 is an NMOS source / drain region, and 122 is PMOS. Source / drain regions.

In a conventional microprocessor having a built-in memory cell formed of a flip-flop circuit using a resistance element as a load, an N well 115 and a P well 115 are formed on a P type semiconductor substrate 101.
After forming the well 114, a thick oxide film 116 for element isolation is selectively formed, and the gate electrode 119 of the MOS transistor and the source / drain region 121 of the NMOS 121 are formed.
And the source / drain regions 122 of the PMOS are formed, and then, for example, the polycrystalline silicon layer 1 which becomes a resistance element is formed.
Had formed 20. That is, the flip-flop type memory cell exists in the P well 114, and the P well 11
Since 4 exists on the P-type semiconductor substrate 101, as a result, the flip-flop type memory cell becomes the P-type semiconductor substrate 10.
1 had a structure electrically equivalent to that existing on the upper part.

[0004]

Since the conventional semiconductor integrated circuit device is configured as described above, the semiconductor substrate 1
There is a problem that the built-in memory cell is likely to malfunction due to α rays (alpha rays) generated inside. Malfunction due to this α-ray is a soft error (Soft-Erro
It is known to occur by the following mechanism. FIG. 7 shows a conventional semiconductor integrated circuit device, that is, one in which a memory cell portion is arranged in a P well 126 formed on a P-type semiconductor substrate 127, when .alpha. When the α-rays 124 are irradiated to this memory cell portion, electron-hole pairs 125 are generated along the range inside the substrate, and at that time, the n ⁺ layer 123 which is a diffusion layer becomes the high potential side. If so, the generated electrons gather on the n ⁺ layer 123 side, and the n ⁺ layer, which should have been at a high potential, becomes a low potential, resulting in malfunction of the memory cell. That is, the α ray 124 induces electrical noise.

The present invention has been made in order to solve the above problems, and provides a memory cell structure excellent in soft error resistance due to α rays while maintaining the pattern layout and performance of a conventional logic circuit section. An object of the present invention is to provide a built-in semiconductor integrated circuit device and its manufacturing method.

[0006]

SUMMARY OF THE INVENTION A semiconductor integrated circuit device according to the present invention is a flip-flop circuit having a pair of input / output terminals, which is composed of two resistance elements and two MISFETs, and a flip-flop circuit on a P-type semiconductor substrate. Switch MI connected to each of the input / output terminals of the switch circuit
A memory cell portion including an SFET and a logic circuit portion are formed, and the memory cell portion is formed in an N-type region formed in the semiconductor substrate, leaving an N-type region between the substrate and the substrate. Formed in the P-type region.

In the semiconductor integrated circuit device according to the present invention, the N-type region operates at the same potential as the power supply voltage and the P-type region operates at the ground potential.

In the method of manufacturing a semiconductor integrated circuit device according to the present invention, a part of the oxide film grown on the p-type semiconductor substrate is removed and an n-type impurity is introduced from the exposed part. Forming an n-type conductive layer, forming a first n-well by heat treating the semiconductor substrate to diffuse the first n-type conductive layer into the semiconductor substrate, and the semiconductor substrate. After forming an oxide film and a nitride film on the entire surface, using the photoresist patterned and coated on the nitride film as a mask, the inside of the region of the first N well and the region of the first N well of the nitride film are used. A part of the outside of the hole is opened, and a p-type impurity is introduced from the hole to form a p-type conductive layer; and after the photoresist is removed, the semiconductor substrate is oxidized to form the hole. The step of forming a thick oxide film on the After removing the film, a step of introducing an n-type impurity from a portion other than the thick oxide film to form a second n-type conductive layer, and a step of heat-treating the semiconductor substrate to remove the p-type conductive layer and the Diffusing the second n-type conductive layer into the semiconductor substrate to form a P well and a second N well.

[0009]

According to the present invention, the P well of the memory cell portion is formed in the region surrounded by the N well formed in the semiconductor substrate. As a result, as shown in FIG.
Among the electrons induced by the α-ray irradiation and transmitted by the α-ray 24, the electrons generated in the N well 28 and the P-type substrate 27 are between the P well 26 and the N well 28 in which the memory cell exists. Since the P well cannot enter the P well due to the potential barrier, the amount of electric charge that causes electrical noise is significantly reduced as compared with the conventional structure, and a semiconductor integrated circuit device having a memory cell structure excellent in soft error resistance due to α rays is provided. Obtainable.

According to the present invention, since the N-type region operates at the same potential as the power supply voltage and the P-type region operates at the ground potential, a semiconductor integrated circuit device having a memory cell structure excellent in soft error resistance due to α rays is provided. Obtainable.

Since the method of manufacturing a semiconductor integrated circuit device according to the present invention has the above-mentioned structure, it has a memory cell structure excellent in soft error resistance due to α rays while maintaining the pattern layout and performance of the conventional logic circuit section. A semiconductor integrated circuit device can be obtained.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. 1 to 3 are sectional views showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.
1 is a P-type silicon single crystal substrate (hereinafter referred to as P-type substrate), 2 is a silicon oxide film, 3 is an n-type conductive layer, 4 is an n-type impurity, 5 is a first N well, and 6 is a silicon oxide film. , 7
Is a silicon oxide film, 8 is a silicon nitride film, 9 is a photoresist, 10 is a p-type conductive layer, 11 is a p-type impurity, 12 is a thick oxide film for element isolation, 13 is an n-type conductive layer, and 14 is n.
Type impurity, 15 is a second N well, 16 is a P well, 1
Reference numeral 7 is a thick oxide film, 18 is a p ⁺ -type conductive layer, 19 is a gate electrode, and 20 is polycrystalline silicon which serves as a resistance element.

First, as shown in FIG. 1 (b), a silicon oxide film 2 is grown to a thickness of about 3000 to 5000 angstroms on a P-type substrate 1 shown in FIG. 1 (a). By performing the process, the silicon oxide film 2 is removed over the region including the region where the memory cell portion is to be formed, and the surface of the P-type substrate 1 is exposed.

After that, phosphorus or arsenic 4 which is an impurity exhibiting n-type conductivity is doped from the exposed portion of the P-type substrate 1 by a normal ion implantation method or a thermal diffusion method to form an n-type conductive layer 3. .

Then, as shown in FIG. 1C, the n-type conductive layer 3 is formed by heating the entire substrate 1 at a high temperature of 1000 ° C. or higher.
Are diffused into the P-type substrate 1 to form a first N well 5. At this time, it is usual that a silicon oxide film 6 is newly grown on the exposed portion of the P-type substrate 1 so that the n-type impurities 4 do not evaporate into the vapor phase during the above-mentioned high temperature heat treatment.

Next, the second N well and P well are formed by the method shown in FIGS. 2 (a) to 3 (c).
As shown in FIG. 3, a silicon oxide film 7 and a silicon nitride film 8 are formed on the surface of the substrate 1, and the inside of the region of the first N well 5 and the outside of the region of the first N well 5 are formed according to ordinary photolithography. The photoresist 9 is patterned so that a part of it is opened.

Subsequently, as shown in FIG. 2B, the silicon nitride film 8 is removed by etching using the photoresist 9 as a mask, and then a p-type impurity 11 such as boron is ion-implanted. A p-type conductive layer 10 is formed on the surface of the substrate 1 which is not covered.

Then, as shown in FIG. 2C, after the photoresist 9 is removed, the entire substrate 1 is oxidized in an oxidizing atmosphere. The thick oxide film 12 grows only on the surface of the portion where the type conductive layer 10 is formed.

After that, as shown in FIG. 3 (a), the silicon nitride film 8 is removed, and then an impurity 14 having n-type conductivity is ion-implanted, and this time the surface of the substrate 1 other than the thick oxide film 12 is ion-implanted. Then, the n-type conductive layer 13 is formed.

After that, as shown in FIG. 3B, the entire substrate 1 is heat-treated, so that the p-type conductive layer 10 and the n-type conductive layer 13 are formed.
Are diffused into the substrate 1 to form a P well 16 and a second N well 15, respectively. Then, as shown in FIG. 3 (c),
If the silicon oxide film 7 and the thick oxide film 12 on the entire substrate 1 are removed, the second N well 15 and the P well 16 are respectively formed.
And the P well 16 formed inside the first N well 5
Substrate 1 having is completed. Then, as shown in FIG. 4, a flip-flop type memory cell and an N channel M are formed by a normal method.
The OS transistor and the P-channel MOS transistor may be formed.

In this embodiment, as described above, the P well 16 in which the flip-flop type memory cell is formed is formed into the N well.
Since it is formed in the well 5 and the N well 5 operates at the same potential as the power supply voltage and the P well 16 operates at the ground potential during operation as a memory, n ^{+ of the} memory cell portion is operated.
The substrate structure around the diffusion layer 23 is as shown in FIG. That is, among the electrons induced by the α rays 24, the electrons generated in the N well 28 and the P type substrate 27 are in the P well 26 due to the potential barrier between the P well 26 in which the memory cell exists and the N well 28. Therefore, the amount of electric charge collected in the n ⁺ diffusion layer 23 is much smaller than that in the structure of the conventional semiconductor integrated circuit device, and the margin against the noise induced by the α ray 24 can be improved.

Further, in the present embodiment, the p-type is formed from the holes formed in the region of the first N well 5 formed in the P-type substrate 1 and in the portion outside the region of the first N well 5. To form the p-type conductive layer 10 and oxidize the P-type substrate 1 to form a thick oxide film 12 in the opening, and then to remove the n-type impurities from the portion other than the thick oxide film 12. Then, the n-type conductive layer 13 is formed and then the whole of the p-type substrate 1 is heat-treated to diffuse the p-type conductive layer 10 and the n-type conductive layer 13 into the p-well 16 and the second n-type conductive layer 13, respectively. Since the well 15 is used, the N-channel MOS transistor and the P-channel MOS transistor forming the logic circuit section can be formed in parallel with the formation of the memory cell section without changing the pattern layout or performance thereof from the conventional one.

In the above embodiment, the P well in which the memory cell is formed and the P well 16 in the other portion are formed at the same time.
6 may be formed separately. In any case, it is necessary to provide the P well of the memory cell portion so as to be in the region surrounded by the N well.

[0024]

As described above, according to the present invention, since the P well of the memory cell portion is surrounded by the N well, of the electrons which are irradiated with α rays and are transmitted through the α rays and are induced. Electrons generated in the N well and in the P type substrate cannot enter the P well due to the potential barrier between the P well in which the memory cell exists and the N well.
Compared to the conventional structure, the amount of electric charge that causes electrical noise is significantly reduced, and the α-ray causes erroneous operation (soft error).
A semiconductor integrated circuit device having a memory cell structure with excellent durability can be obtained. Further, in the manufacturing process, since the logic circuit portion is formed on the P-type substrate as in the conventional case, it is possible to manufacture a semiconductor integrated circuit having stable memory cells without changing the pattern layout.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 3 is a cross-sectional view showing a manufacturing process of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 4 is a sectional view of a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 5 is a factor diagram showing that the present invention has an operating margin with respect to induced noise due to α rays.

FIG. 6 is a cross-sectional view of a conventional semiconductor integrated circuit device.

FIG. 7 is a factor diagram for explaining that in the conventional structure, there is no operating margin for induced noise due to α rays.

[Explanation of symbols]

1 P-type semiconductor substrate 2 Silicon oxide film 3 n-type conductive layer 4 n-type impurity 5 First N-well 6 Silicon oxide film 7 Silicon oxide film 8 Silicon nitride film 9 Photoresist 10 p-type conductive layer 11 p-type impurity 12 Thick Oxide film 13 n-type conductive layer 14 n-type impurity 15 second N well 16 P well 17 thick oxide film 18 p ^{+ type} conductive layer 19 gate electrode 20 polycrystalline silicon 21 NMOS source / drain region 22 PMOS source / drain Region 23 n ⁺ layer 24 α ray 25 electron / hole pair 26 P well 27 P type semiconductor substrate 28 N well

Claims (3)

[Claims] 1. A flip-flop circuit having a pair of input / output terminals, which is composed of two resistance elements and two MISFETs, and a switch connected to each of the input / output terminals of the flip-flop circuit on a P-type semiconductor substrate. For MI
In a semiconductor integrated circuit device having a memory cell section composed of an SFET and a logic circuit section at the same time, the memory cell section has an N type region between the substrate and an N type region formed in the semiconductor substrate. A semiconductor integrated circuit device, wherein the semiconductor integrated circuit device is formed in a P-type region formed by leaving the region. 2. The semiconductor integrated circuit device according to claim 1, wherein the N-type region operates at the same potential as a power supply voltage and the P-type region operates at a ground potential. 3. A step of removing a part of an oxide film grown on a P-type semiconductor substrate and introducing an n-type impurity from the exposed part to form a first n-type conductive layer, A step of heat-treating the semiconductor substrate to diffuse the first n-type conductive layer into the inside of the semiconductor substrate to form a first N well; and a step of forming an oxide film and a nitride film on the entire surface of the semiconductor substrate. Using the photoresist coated and patterned on the film as a mask, a portion of the nitride film inside the region of the first N well and a portion outside the region of the first N well are opened. By introducing a p-type impurity from the opening,
A step of forming a mold conductive layer, a step of oxidizing the semiconductor substrate after removing the photoresist to form a thick oxide film in the opening, and a step of removing the nitride film and removing a layer other than the thick oxide film. Part to n
A p-type conductive layer and the second n-type conductive layer are formed in the semiconductor substrate by heat-treating the semiconductor substrate by introducing a p-type impurity into the semiconductor substrate. A step of diffusing to form a P well and a second N well.