JPH0245377B2 - - Google Patents
Info
- Publication number
- JPH0245377B2 JPH0245377B2 JP55170063A JP17006380A JPH0245377B2 JP H0245377 B2 JPH0245377 B2 JP H0245377B2 JP 55170063 A JP55170063 A JP 55170063A JP 17006380 A JP17006380 A JP 17006380A JP H0245377 B2 JPH0245377 B2 JP H0245377B2
- Authority
- JP
- Japan
- Prior art keywords
- mos transistor
- gate
- inverter
- source
- drain
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 claims description 9
- 238000010586 diagram Methods 0.000 description 7
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/0175—Coupling arrangements; Interface arrangements
- H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
- H03K19/018507—Interface arrangements
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Manipulation Of Pulses (AREA)
- Logic Circuits (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170063A JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP55170063A JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5793731A JPS5793731A (en) | 1982-06-10 |
| JPH0245377B2 true JPH0245377B2 (enExample) | 1990-10-09 |
Family
ID=15897936
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP55170063A Granted JPS5793731A (en) | 1980-12-02 | 1980-12-02 | Logical level conversion circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5793731A (enExample) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4553051A (en) * | 1983-07-18 | 1985-11-12 | Texas Instruments Incorporated | PMOS Input buffer compatible with logic inputs from an NMOS microprocessor |
-
1980
- 1980-12-02 JP JP55170063A patent/JPS5793731A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5793731A (en) | 1982-06-10 |
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