JPH0245377B2 - - Google Patents

Info

Publication number
JPH0245377B2
JPH0245377B2 JP55170063A JP17006380A JPH0245377B2 JP H0245377 B2 JPH0245377 B2 JP H0245377B2 JP 55170063 A JP55170063 A JP 55170063A JP 17006380 A JP17006380 A JP 17006380A JP H0245377 B2 JPH0245377 B2 JP H0245377B2
Authority
JP
Japan
Prior art keywords
mos transistor
gate
inverter
source
drain
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP55170063A
Other languages
English (en)
Japanese (ja)
Other versions
JPS5793731A (en
Inventor
Takayoshi Makabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP55170063A priority Critical patent/JPS5793731A/ja
Publication of JPS5793731A publication Critical patent/JPS5793731A/ja
Publication of JPH0245377B2 publication Critical patent/JPH0245377B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0175—Coupling arrangements; Interface arrangements
    • H03K19/0185—Coupling arrangements; Interface arrangements using field effect transistors only
    • H03K19/018507—Interface arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)
  • Manipulation Of Pulses (AREA)
JP55170063A 1980-12-02 1980-12-02 Logical level conversion circuit Granted JPS5793731A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55170063A JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55170063A JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Publications (2)

Publication Number Publication Date
JPS5793731A JPS5793731A (en) 1982-06-10
JPH0245377B2 true JPH0245377B2 (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html) 1990-10-09

Family

ID=15897936

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55170063A Granted JPS5793731A (en) 1980-12-02 1980-12-02 Logical level conversion circuit

Country Status (1)

Country Link
JP (1) JPS5793731A (GUID-C5D7CC26-194C-43D0-91A1-9AE8C70A9BFF.html)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4553051A (en) * 1983-07-18 1985-11-12 Texas Instruments Incorporated PMOS Input buffer compatible with logic inputs from an NMOS microprocessor

Also Published As

Publication number Publication date
JPS5793731A (en) 1982-06-10

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