JPH0244817A - Sequential comparison analog/digital converter - Google Patents

Sequential comparison analog/digital converter

Info

Publication number
JPH0244817A
JPH0244817A JP19556288A JP19556288A JPH0244817A JP H0244817 A JPH0244817 A JP H0244817A JP 19556288 A JP19556288 A JP 19556288A JP 19556288 A JP19556288 A JP 19556288A JP H0244817 A JPH0244817 A JP H0244817A
Authority
JP
Japan
Prior art keywords
converter
terminal
external
test signal
data output
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP19556288A
Other languages
Japanese (ja)
Inventor
Matsuo Senzaki
松士 浅崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP19556288A priority Critical patent/JPH0244817A/en
Publication of JPH0244817A publication Critical patent/JPH0244817A/en
Pending legal-status Critical Current

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  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To facilitate the estimation of a fault part by switching a data output terminal in such e way that it functions as an input terminal by means of a signal inputted from an external control terminal, converting an external test signal inputted from the data output terminal into the output of a sequential comparison register and supplying it to a D/A converter. CONSTITUTION:When a check mode is switched by the external control terminal 5, a check mode switching control circuit 7 causes a data output pin 8 which has been an output pin till that time to function as an input pin, and the external test signal can be inputted. Consequently, the check mode switching control circuit 7 converts the external test signal into the output of the sequential comparison register 3, and supplies the external test signal inputted from the data output pin 8 to the D/A converter. With optionally inputting the external test signal, a D/A monitor output terminal 6 removes and checks an objective voltage. Thus, the fault can easily be analyzed.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は逐次比較アナログ・ディジタル変換器に関する
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a successive approximation analog-to-digital converter.

〔従来の技術〕[Conventional technology]

従来の逐次比較アナログ・ディジタル変換器(以下アナ
ログ・ディジタルはD/Aと記す)の構成図を第2図に
示す。
FIG. 2 shows a configuration diagram of a conventional successive approximation analog-to-digital converter (hereinafter analog-to-digital is referred to as D/A).

第2図において、9はD/Aコンバータ12の出力とア
ナログ入力電圧を比較するコンパレータ、10はコンパ
レータ9の判定を受けて逐次比較レジスタ11を制御す
る制御回路、11はD/Aコンバータを制御する逐次比
較レジスタ、12は逐次比較レジスタの命令を受は基準
比較電圧を発生するD/Aコンバータである。
In FIG. 2, 9 is a comparator that compares the output of the D/A converter 12 and the analog input voltage, 10 is a control circuit that controls the successive approximation register 11 based on the judgment of the comparator 9, and 11 is a control circuit that controls the D/A converter. 12 is a D/A converter that receives the instruction of the successive approximation register and generates a reference comparison voltage.

アナログ入力電圧が入力されると、これに対する基準電
圧がD/Aコンバータ12から出力されコンパレータ9
で比較される。その判定を受けて、制御回路10はD/
Aコンバータ12の次の比較電圧を発生させることがで
きるように逐次比較レジスタ11を制御する。逐次比較
レジスタ11は制御回路10の命令を受けてD/Aコン
バータ12を制御する。これら一連の動作をくりかえし
上位ビットより順にA/D値が決まる。
When an analog input voltage is input, a reference voltage for this is output from the D/A converter 12 and the comparator 9
are compared. In response to the determination, the control circuit 10
The successive approximation register 11 is controlled so that the next comparison voltage of the A converter 12 can be generated. Successive approximation register 11 receives instructions from control circuit 10 and controls D/A converter 12 . These series of operations are repeated to determine the A/D value in order from the most significant bits.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のA/D変換器は、D/Aコンバータ12
のチエツクができないため、故障解析時において、多く
の時間をついやす、故障箇所の推定が困難、外部からの
調査する手段が少ないという欠点がある。
The conventional A/D converter described above includes the D/A converter 12.
Since it is not possible to check the fault, it takes a lot of time during failure analysis, it is difficult to estimate the failure location, and there are few means for investigating from the outside.

本発明の目的は、以上の欠点を解決し、解析時間の短縮
ができ、また故障箇所の推定を容易にすべく外部からの
調査の手段を増やすことができるA/D変換器を提供す
ることにある。
An object of the present invention is to provide an A/D converter that can solve the above-mentioned drawbacks, shorten analysis time, and increase the means for external investigation to facilitate estimation of failure locations. It is in.

〔課題を解決するための手段〕[Means to solve the problem]

本発明の逐次比較アナログ ティジタル変換器は、内部
基準電圧を発生するD/Aコンバータと、外部からのア
ナログ入力信号と前記D/Aコンバータ出力とを比較す
るコンパレーターと、該コンパレーターの判定結果に基
づき前記D/Aコンバータを制御する逐次比較レジスタ
と、外部制御端子と、該外部制御端子から入力する信号
により、データ出力端子を入力端子として機能するよう
に切換え、前記データ出力端子から入力する外部テスト
信号を前記逐次比較レジスタの出力に換えて前記D/A
コンバータに供給するチェックモード切換制御回路を有
することを特徴とする。
The successive approximation analog-to-digital converter of the present invention includes a D/A converter that generates an internal reference voltage, a comparator that compares an external analog input signal and the output of the D/A converter, and a determination result of the comparator. A successive approximation register that controls the D/A converter based on the data output terminal, an external control terminal, and a signal input from the external control terminal, switches the data output terminal to function as an input terminal, and inputs from the data output terminal. The D/A converts the external test signal into the output of the successive approximation register.
The present invention is characterized by having a check mode switching control circuit that supplies power to the converter.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第1図は本発明の一実施例の回路構成図である。FIG. 1 is a circuit diagram of an embodiment of the present invention.

第1図において、1はアナログ入力電圧とD/Aコンバ
ータ4の出力とを比較するコンパレータ、2はコンパレ
ータ1の判定を受けて逐次比較レジスタ3を制御する制
御回路、3はD/Aコンバータ4を制御する逐次比較レ
ジスタ、4は逐次比較レジスタ3の命令を受は基準比較
電圧を発生するD/Aコンバータ、5はチェックモード
切換えを可能にする外部制御端子、6はD/Aコンバー
タの出力をモニターするD/Aモニター出力端子、7は
外部制御端子5がら入力する命令を受はチェックモード
切換えを行うチェックモード切換制御回路、8はA/D
変換値を出力するデータ出力ピンである。
In FIG. 1, 1 is a comparator that compares the analog input voltage and the output of the D/A converter 4, 2 is a control circuit that controls the successive approximation register 3 based on the judgment of the comparator 1, and 3 is the D/A converter 4. 4 is a D/A converter that receives the command of successive approximation register 3 and generates a reference comparison voltage, 5 is an external control terminal that enables check mode switching, and 6 is the output of the D/A converter. 7 is a check mode switching control circuit that receives commands input from the external control terminal 5 to switch the check mode, and 8 is an A/D monitor output terminal for monitoring the A/D.
This is a data output pin that outputs the converted value.

A/D変換動作自体は前述した従来のA/D変換器にお
けるものと変わらないが、外部制御端子5によりチェッ
クモードの切換えが行われると、チェックモード切換制
御回路17により今まで出力ピンであったデータ出力ピ
ン8が入力ピンとして機能するようになり、外部テスト
信号の入力を可能にする。これにより、チェックモード
切換制御回路7は、通常動作時における逐次比較レジス
タ3の出力に換えて、デ−タ出力ピン8から入力する外
部テスト信号をD/Aコンバータ4に供給するようにな
る。
The A/D conversion operation itself is the same as that in the conventional A/D converter described above, but when the check mode is switched by the external control terminal 5, the check mode switching control circuit 17 changes the output pin that was previously used. The data output pin 8 now functions as an input pin, allowing input of an external test signal. As a result, the check mode switching control circuit 7 supplies the external test signal input from the data output pin 8 to the D/A converter 4 instead of the output of the successive approximation register 3 during normal operation.

次に外部テスト信号を任意に入力することにより、D/
Aモニター出力端子により、所望の電圧を取り出しチエ
ツクすることができる。このようにすることにより、故
障解析時において、時間をかけずに故障解析を容易にし
、かつ外部からの調査手段を増やすことができるように
なる。
Next, by inputting an external test signal arbitrarily, the D/
A desired voltage can be taken out and checked using the A monitor output terminal. By doing so, it becomes possible to facilitate failure analysis without spending much time during failure analysis, and to increase the number of external investigation means.

〔発明の効果〕〔Effect of the invention〕

以上の説明で明らかな如く、本発明のA/D変換器によ
れば、内部D/A変換器の出力を外部から制御し、モニ
タ一端子により外部に取り出すことができ、内部のD/
A変換器のチエツクが容易となるばかりでなく、故障解
析時において、解析時間を短縮し、故障箇所を推定を容
易にし、外部調査手段を増やすことなどの効果を得るこ
とができる。
As is clear from the above description, according to the A/D converter of the present invention, the output of the internal D/A converter can be controlled from the outside and taken out to the outside through the monitor terminal, and the output of the internal D/A
This not only makes it easier to check the A converter, but also reduces the analysis time during failure analysis, makes it easier to estimate the failure location, and increases the number of external investigation means.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例の回路構成図、第2図は従来
の回路構成図である。 1.9・・・コンパレータ、2,10・・・制御回路、
2.11・・・逐次比較レジスタ、4,12・・・D/
Aコンバータ、5・・・外部制御端子、6・・・D/A
モニター出力端子、7・・・チェックモード切換制御回
路、8・・・データ出力ピン。
FIG. 1 is a circuit configuration diagram of an embodiment of the present invention, and FIG. 2 is a conventional circuit configuration diagram. 1.9... Comparator, 2,10... Control circuit,
2.11...Successive approximation register, 4,12...D/
A converter, 5...external control terminal, 6...D/A
Monitor output terminal, 7... Check mode switching control circuit, 8... Data output pin.

Claims (1)

【特許請求の範囲】[Claims] 内部基準電圧を発生するD/Aコンバータと、外部から
のアナログ入力信号と前記D/Aコンバータ出力とを比
較するコンパレーターと、該コンパレーターの判定結果
に基づき前記D/Aコンバータを制御する逐次比較レジ
スタと、外部制御端子と、該外部制御端子から入力する
信号により、データ出力端子を入力端子として機能する
ように切換え、前記データ出力端子から入力する外部テ
スト信号を前記逐次比較レジスタの出力に換えて前記D
/Aコンバータに供給するチェックモード切換制御回路
を有することを特徴とした逐次比較アナログ・ディジタ
ル変換器。
A D/A converter that generates an internal reference voltage, a comparator that compares an external analog input signal with the output of the D/A converter, and a sequential controller that controls the D/A converter based on the determination result of the comparator. A data output terminal is switched to function as an input terminal by a comparison register, an external control terminal, and a signal input from the external control terminal, and an external test signal input from the data output terminal is outputted from the successive approximation register. Instead, the above D
1. A successive approximation analog-to-digital converter comprising a check mode switching control circuit for supplying a signal to an A/A converter.
JP19556288A 1988-08-04 1988-08-04 Sequential comparison analog/digital converter Pending JPH0244817A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP19556288A JPH0244817A (en) 1988-08-04 1988-08-04 Sequential comparison analog/digital converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP19556288A JPH0244817A (en) 1988-08-04 1988-08-04 Sequential comparison analog/digital converter

Publications (1)

Publication Number Publication Date
JPH0244817A true JPH0244817A (en) 1990-02-14

Family

ID=16343183

Family Applications (1)

Application Number Title Priority Date Filing Date
JP19556288A Pending JPH0244817A (en) 1988-08-04 1988-08-04 Sequential comparison analog/digital converter

Country Status (1)

Country Link
JP (1) JPH0244817A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181584A (en) * 1994-12-22 1996-07-12 Nec Corp Variable delay circuit and delay time check method

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57119259A (en) * 1981-01-19 1982-07-24 Hitachi Ltd Testing method for a/d converter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57119259A (en) * 1981-01-19 1982-07-24 Hitachi Ltd Testing method for a/d converter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08181584A (en) * 1994-12-22 1996-07-12 Nec Corp Variable delay circuit and delay time check method

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