JPH1183559A - Signal processor and reconstitution method for circuit pattern in signal processor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce the size of a processor by a method wherein a control part selects a the size of circuit pattern corresponding to a sensor and a circuit pattern in an FPGA part for preprocessing is rewritten. SOLUTION: By a manual instruction, a sensor selection signal is output to a selector 7 and to a control part 11. The control part 11 selects a circuit pattern 12 in a preprocessing part for a sensor to be selected, and it rewrites the content of an FPGA part 8 for preprocessing. In addition, the selector 7 connects the sensor, to be selected, to the FPGA part 8 for preprocessing. When, e.g. a sensor 1 is instructed as a result of their control, data on the sensor 1 ic converted by an A/D conversion part 4 so as to be output to the FPGA part 8 for preprocessing via the selector 7. A processing operation according to the sensor 1 is executed by the FPGA part 8 for preprocessing, the data is output to a signal processing part 9, an object or the like is detected, and the data is output to an information processing part 10. Then, the recognition processing operation, the tracking processing operation or the like of the object detected by the signal processing part 9 is performed by the information processing part 10. Consequently, a preprocessing part is not required in every sensor, and the size of the processor can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a preprocessing device for a sensor which is not used simultaneously.
The present invention relates to a signal processing device capable of simplifying the entire device by sharing it using a ramble gate array or the like and a method of reconfiguring a circuit pattern in the signal processing device.

[0002]

2. Description of the Related Art FIG. 9 shows, for example, "Theory and
Applications of Digital S
FIG. 1 is a configuration diagram showing a conventional signal processing device shown in “signal processing”, wherein 1 is a sensor, 4 is an A / D conversion unit that performs A / D conversion of an output of the sensor 1, and 15 is an A / D conversion. A pre-processing unit that performs processes such as a matched filter process and a threshold value detection process on the signal that has been A / D-converted by the unit 4; And a signal processing unit 10 for recognizing and tracking the object detected by the signal processing unit 9.

Next, the operation will be described. First, the signal output from the sensor 1 is converted into an A / D signal by the A / D converter 4.
After the D conversion, the pre-processing unit 15 performs matched filter processing, threshold value detection processing, and the like. Next, the signal processing unit 9 receives the signal processed by the preprocessing unit 15 and detects a target object or the like.
Performs recognition and tracking of an object detected based on a detection signal from the signal processing unit 9. Note that these preprocessing units 1
In many cases, the distinction between the signal processing unit 5 and the signal processing unit 9 and the information processing unit 10 is not clear, but here, high-speed processing and real-time processing are required, and the part realized by dedicated hardware is defined as the preprocessing unit 15. I do.

Next, a conventional signal processing device including a plurality of sensors will be described. FIG. 10 is a configuration diagram showing a conventional signal processing device including a plurality of sensors. In the figure, 1, 2, and 3 are sensors, 4, 5, and 6 are A / D converters, and 15, 16, and 17 are shown. Denotes a preprocessing unit, 20, 21 and 22 denote signal processing units, and 10 denotes an information processing unit. In the case of a signal processing device including a plurality of sensors as shown in FIG.
5, 6, each of the pre-processing units 15, 16, 17 and each of the signal processing units 20, 21, 22; the information processing unit 10 receives the signals output from each of the signal processing units 20, 21, 22;
Integrate and process.

[0005]

Since the conventional signal processing apparatus is configured as described above, a preprocessing apparatus composed of dedicated hardware is required for each sensor, and the number of sensors increases. However, there has been a problem that the circuit scale of the entire apparatus becomes large in proportion to the above.

Further, any of the pre-processing units 15, 16, 17
When a failure occurs, the preprocessing unit 1 in which the failure occurred
Since there is no configuration for performing the processing of 5, 16, and 17, there is a problem that the processing of the sensors 1, 2, and 3 corresponding to the preprocessors 15, 16, and 17 in which the failure has occurred cannot be performed continuously. .

Further, when a processing error occurs in each of the pre-processing units 15, 16, 17, there is a problem that the processing of the sensors 1, 2, 3 cannot be continued due to the influence of the processing error.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems, and a signal processing device and a signal which can simplify the entire device by sharing a pre-processing device for sensors which are not used at the same time. An object of the present invention is to obtain a method for reconfiguring a circuit pattern in a processing device.

Further, according to the present invention, by automatically detecting a pre-processing unit in which a failure has occurred, and by substituting the pre-processing unit in which the failure has occurred, the processing of the sensor can be continued. It is an object to obtain a signal processing device and a method for reconfiguring a circuit pattern in the signal processing device.

Further, according to the present invention, even when a processing error occurs in each preprocessing unit, the processing error is not affected by the processing error.
An object of the present invention is to provide a signal processing device capable of continuing sensor processing and a method for reconfiguring a circuit pattern in the signal processing device.

[0011]

A signal processing device according to the present invention receives output signals of all sensors, selects one output signal according to an instruction of an operator by a selector, and outputs a signal corresponding to the sensor. The pattern is rewritten in software by the preprocessing FPGA unit, and when any one of the sensors is selected by an instruction from the operator, the control unit selects a circuit pattern corresponding to the selected sensor, and executes the preprocessing. F
The circuit pattern of the PGA section is rewritten.

In the signal processing apparatus according to the present invention, a sensor to be used next is automatically selected based on a result of information processing in a selector and a circuit pattern to be rewritten into a preprocessing FPGA unit.

The signal processing device according to the present invention receives the output signals of all the sensors, selects a plurality of output signals according to an instruction of an operator by a selector, and pre-processes a circuit pattern corresponding to the sensors into a plurality of pre-processes. The software can be rewritten in software by the FPGA unit, and when one of the sensors is selected by the control unit according to an instruction from the operator, and the priority of the sensor is instructed by the operator, the selected sensor is selected. And a circuit pattern corresponding to the specified priority is selected, and the circuit pattern of the preprocessing FPGA unit is rewritten.

The signal processing apparatus according to the present invention automatically selects a plurality of sensors to be used next and the priority of the sensors based on the result of the information processing in the circuit pattern to be rewritten to the selector and the preprocessing FPGA unit. It was made.

In the signal processing device according to the present invention, a circuit pattern corresponding to each sensor is set by a plurality of preprocessing units,
The circuit pattern corresponding to the sensor is rewritten in software by the preprocessing FPGA unit, the output signals of all the sensors are input, one output signal is selected by the first selector according to the instruction, and a plurality of signals are output by the failure detection circuit. Monitor the pre-processing unit, and when a failure occurrence signal is received from any of the pre-processing units, notify the pre-processing unit where the failure has occurred, and when a failure occurrence notification is received from this failure detection circuit. Then, the control unit selects the circuit pattern of the preprocessing unit in which the failure has occurred,
In addition to writing to the preprocessing FPGA unit, the sensor corresponding to the failed preprocessing unit and the preprocessing FPGA unit are connected, and set according to each sensor. When a failure occurs in the processing unit, a signal from the preprocessing FPGA unit is selected.

In the signal processing device according to the present invention, a circuit pattern corresponding to the sensor is rewritten in software by a plurality of preprocessing FPGA units, and one circuit pattern corresponding to an instruction of an operator is subjected to a plurality of preprocessing by the control unit. Set to the processing FPGA unit, input the output signals of all the sensors, select one signal according to the operator's instruction by the selector, output to the plurality of preprocessing FPGA units, and select the multiple signals by the majority function unit. The output from the preprocessing FPGA unit is fetched, and the result of the most matching number of outputs from the preprocessing FPGA unit is output.

According to a method of reconstructing a circuit pattern in a signal processing apparatus according to the present invention, output signals of all sensors are inputted, one output signal corresponding to an instruction of an operator is selected by a selector, and the output signal is selected according to the sensor. The circuit pattern is rewritten in software by the preprocessing FPGA unit, and when any of the sensors is selected by an instruction from the operator, a circuit pattern corresponding to the sensor selected by the control unit is selected, and the circuit pattern is rewritten. The circuit pattern of the FPGA section is rewritten.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below. Embodiment 1 FIG. FIG. 1 is a block diagram showing a signal processing apparatus according to Embodiment 1 of the present invention.
3 is a sensor, 4 is an A / D converter for A / D converting a signal from the sensor 1, 5 is an A / D converter for A / D converting a signal from the sensor 2, and 6 is a signal from the sensor 3. A / D converter for A / D conversion, 7 is a selector for selecting one of the signals output from A / D converters 4, 5, and 6 according to a manual instruction, and 8 is dedicated hardware which is software-like. Is one of the rewritable integrated circuits.
Preprocessing FPGA (Field Programmable) in which a circuit pattern 12 corresponding to the processing corresponding to 2 and 3 is set.
(able Gate Array) section.

Reference numeral 9 denotes a signal processing unit for detecting a target object or the like based on the result of the signal output from the preprocessing FPGA unit 8, and 10 performs recognition and tracking of the object detected by the signal processing unit 9. The information processing unit 11 selects the circuit pattern 12 of the pre-processing unit corresponding to each of the sensors 1, 2, 3 when one of the sensors 1, 2, 3 is selected according to a manual instruction from the operator. This is a control unit for rewriting the contents of the preprocessing FPGA unit 8.

Next, the operation will be described. FIG. 2 is a flowchart showing the operation of the signal processing device according to the first embodiment of the present invention. First, the operator checks the output result from the information processing unit 10 obtained in advance (step ST
1) It is determined which of the sensors 1, 2 and 3 can be used most effectively for processing, and a sensor selection signal is output to the selector 7 and the controller 11 according to a manual instruction (step ST2). Next, the control section 11 selects the corresponding circuit pattern 12 of the pre-processing section of the sensors 1, 2, 3 based on the input sensor selection signal (Step ST).
3) Rewrite the contents of the preprocessing FPGA unit 8 (step ST4). Further, the selector 7 connects the sensors 1, 2, 3 designated on the basis of the sensor selection signal to the preprocessing FPGA.
Connect to the unit 8 (step ST5). As a result, the preprocessing FPGA unit 8 becomes a preprocessing unit for the corresponding sensor.

As a result of these controls, when the sensor 1 is instructed by the operator, the data of the sensor 1 is A / D-converted by the A / D converter 4, and the pre-processing Output to the FPGA unit 8. Then, after the processing corresponding to the sensor 1 is performed in the preprocessing FPGA unit 8, the signal is output to the signal processing unit 9, the target object is detected (step ST6), and output to the information processing unit 10. You. Next, the information processing section 10 performs processing such as recognition and tracking of the object detected by the signal processing section 9 (step ST).
7). When the sensors 1, 2, and 3 are switched according to the processing result of the information processing unit 10, the above processing is repeated again.

As described above, according to the first embodiment, it is not necessary to have a pre-processing unit for each sensor.
Effects such as reduction in size of the device can be obtained.

Embodiment 2 FIG. FIG. 3 is a block diagram showing a signal processing apparatus according to a second embodiment of the present invention. In the figure, the same reference numerals as those in the first embodiment denote the same or corresponding parts, and a description thereof will be omitted. In the first embodiment, the operator checks the output result from the information processing unit 10 obtained in advance and determines which of the plurality of types of sensors 1, 2, and 3 is most effective. Was. However, in the second embodiment, the information processing unit 10 determines which one of the plurality of types of sensors 1, 2, and 3 is most effective according to its own result, and switches the selector 7. .

As described above, according to the second embodiment, it is not necessary to own a pre-processing unit for each of the sensors 1, 2, and 3, so that the apparatus can be reduced in size and the operator can obtain in advance. The output result from the information processing unit 10 is confirmed,
Since it is not necessary to determine which of the plurality of types of sensors 1, 2, and 3 is most effective, it is possible to reduce the burden on the operator.

Embodiment 3 FIG. 4 is a block diagram showing a signal processing apparatus according to Embodiment 3 of the present invention. In the figure, the same reference numerals as those in Embodiment 1 denote the same or corresponding parts, and a description thereof will be omitted. 13 is a sensor 1, 2,
A selector 14 for selecting two signals from among the three signals input from 3 corresponds to each of the sensors 1, 2, 3, and a pre-processing corresponding to the priority of the processing of each sensor 1, 2, 3. 6 is a circuit pattern of a unit.

Next, the operation will be described. First, the operator checks the output result from the information processing unit 10 obtained in advance and determines which of the two sensors 1, 2, 3 can be used to perform the processing most effectively. Here, for example, the operator selects the sensor 1 and the sensor 2 and determines that the sensor 1 is to be processed with higher accuracy (high priority). Next, the operator outputs a sensor selection signal to the selector 13 and the control unit 11 according to a manual instruction.

Next, based on the input sensor selection signal, the control unit 11 selects a circuit pattern 14 corresponding to the priority of the pre-processing unit of the corresponding sensor 1, 2, 3, and 3
The contents of the two preprocessing FPGA units 8 are rewritten. Also,
The selector 13 connects the sensor 1 specified based on the sensor selection signal to one preprocessing FPGA unit 8 and connects the sensor 2 to the other preprocessing FPGA unit 8. As a result, each preprocessing FPGA unit 8 becomes a preprocessing unit for the corresponding sensor.

As a result of these controls, when the sensor 1 and the sensor 2 are instructed by the operator, the data of the sensor 1 is A / D-converted by the A / D converter 4 and then transmitted through the selector 13. It is output to one preprocessing FPGA unit 8. After the data of the sensor 2 is A / D converted by the A / D converter 5, the data is output to the other preprocessing FPGA unit 8 via the selector 13. Then, after being processed by the preprocessing FPGA unit 8 with an accuracy corresponding to the priority, it is output to the signal processing unit 9, where a target object or the like is detected and output to the information processing unit 10. Next, the information processing unit 10 performs processing such as recognition and tracking of the object detected by the signal processing unit 9. When the sensors 1, 2, and 3 are switched according to the processing result of the information processing unit 10, the above processing is repeated again.

As described above, according to the third embodiment, it is not necessary to have a preprocessing unit for each sensor.
It is possible to reduce the size of the apparatus, and to obtain effects such as changing the accuracy of processing for each sensor in the preprocessing unit according to the plurality of sensors selected by the operator and their priorities.

Embodiment 4 FIG. 5 is a block diagram showing a signal processing apparatus according to a fourth embodiment of the present invention. In the figure, the same reference numerals as those in the first and third embodiments denote the same or corresponding parts, and a description thereof will be omitted. In the third embodiment, the operator uses the information processing unit 1 obtained in advance.
Check the output result from 0, and check the sensor 1
They determined which of two or three would be most effective. However, in the fourth embodiment, the information processing unit 10
Is to determine which of two or more types of sensors 1, 2 and 3 can be processed most effectively according to its own result.

As described above, according to the fourth embodiment, it is not necessary to own a preprocessing unit for each sensor.
The size of the apparatus can be reduced, and the effect of changing the accuracy of the processing of each sensor in the preprocessing unit according to the plurality of sensors selected by the information processing apparatus and their priorities can be obtained.

Embodiment 5 FIG. 6 is a block diagram showing a signal processing apparatus according to Embodiment 5 of the present invention. In the figure, the same reference numerals as those in Embodiment 1 denote the same or corresponding parts, and a description thereof will be omitted. 8a is a pre-processing unit 15,
When all 16 and 17 are operating normally, they are not connected to the sensors 1, 2 and 3 and the pre-processing units 15 and 1 are not connected.
When a failure occurs in any one of the sensors 6 and 17, a preprocessing FPGA unit that inputs and processes signals from the sensors 1, 2, and 3 in place of the preprocessing unit in which the failure has occurred, and 15 is a sensor 1
16 is a pre-processing unit for the sensor 2, 17 is a pre-processing unit for the sensor 3, and 18 is a pre-processing unit 15, 16, 17
Is detected, and when a failure occurrence signal is received from any of the preprocessing units 15, 16, and 17, the failure detection unit notifies the control unit 11 and the selector 7 of the failed preprocessing units 15, 16, and 17. A circuit, 19 is a selector for selecting one output from two inputs, 20 is a signal processing unit for the sensor 1, and 21 is a sensor 2
And a signal processing unit 22 for the sensor 3.

Next, the operation will be described. First, when all of the pre-processing units 15, 16, and 17 are operating normally, the sensor 1 that has been A / D converted via the A / D conversion unit 4.
Are output to the signal processing unit 20 for the sensor 1 and then output to the information processing unit 10. Since the selector 19 at this time is open, the sensor 1 and the pre-processing unit 15,
Sensor 2 and pre-processing unit 16, Sensor 3 and pre-processing unit 1
7 are connected. Further, the selector 19 is a pre-processing unit 1
5, the signal processing unit 20 for the sensor 1, the preprocessing unit 16 and the signal processing unit 21 for the sensor 2, the preprocessing unit 17 and the signal processing unit 22 for the sensor 3 are connected. Therefore, the processing flow is the same as that of the conventional signal processing device.

However, when the failure detection circuit 18 receives a failure occurrence signal from any of the pre-processing units 15, 16, 17, the pre-processing unit 15, 16, 17 in which the failure has occurred is communicated with the control unit 11. Notify the selector 19. In the control unit 11,
The circuit pattern 12 of the pre-processing unit 15, 16, or 17 in which the failure has occurred is selected, and the pre-processing F which is on standby as a spare is selected.
By writing to the PGA unit 8a and operating the selector 7, the pre-processing units 15, 16,
17 and the corresponding sensors 1, 2, 3 are connected.
In the control unit 11, the selector 19 is connected to the pre-processing units 15, 16, 17 and the signal processing units 20, 21, 22, 22 in which the failure has occurred.
Is disconnected, and the preprocessing FPGA unit 8a and the signal processing units 20, 21, and 22 are connected. As a result, the failed pre-processing units 15, 16, 17 are disconnected and the pre-processing FP
The GA unit 8a acts on behalf of the GA unit 8a to continue the processing.

As described above, according to the fifth embodiment, when a failure occurs in the preprocessors 15, 16, and 17 for the sensors 1, 2, and 3, the failure is automatically detected. ,
By using the preprocessing FPGA unit 8a as a preprocessing unit for the sensors 1, 2, and 3, it is possible to obtain effects such as continuous processing.

Embodiment 6 FIG. FIG. 7 is a block diagram showing a signal processing apparatus according to Embodiment 6 of the present invention. In the figure, the same reference numerals as those in Embodiment 1 denote the same or corresponding parts, and a description thereof will be omitted. A majority function unit 23 examines the outputs from the three preprocessing FPGA units 8 and outputs two or more matched contents.

Next, the operation will be described. First, the operator checks the output result obtained from the information processing unit 10 obtained in advance, determines which of the sensors 1, 2, and 3 can be used most effectively to perform processing. Is output to the selector 7 and the control unit 11. next,
The control unit 11 selects the corresponding circuit pattern 12 of the preprocessing unit of the sensors 1, 2, 3 based on the input sensor selection signal, and rewrites the contents of the three preprocessing FPGA units 8. Further, the selector 7 converts the sensors 1, 2, 3 designated on the basis of the sensor selection signal into three pre-processing FPs.
Connect to GA unit 8. As a result, three pre-processing FPGs
A section 8 is a pre-processing section for the corresponding sensor.

As a result of these controls, when the sensor 1 is instructed by the operator, the data of the sensor 1 is A / D-converted by the A / D converter 4, and three It is output to the processing FPGA unit 8. Then, the three preprocessing FPGA sections 8 perform processing corresponding to the sensor 1 and output the processed data to the majority decision function section 23. Then, the majority function unit 23 includes three preprocessing FPGA units 8.
, And outputs two or more matched contents to the signal processing unit 9. Then, the signal processing unit 9 detects a target object or the like, and outputs the detection result to the information processing unit 10. Next, the information processing unit 10 performs processing such as recognition and tracking of the object detected by the signal processing unit 9. The information processing unit 10
When the sensors 1, 2, 3 are switched according to the processing result of the above, the above processing is repeated again.

As described above, according to the sixth embodiment, even when a processing error occurs in the pre-processing section, the effects can be obtained such that the processing can be continued without being affected by the processing error. .

Embodiment 7 FIG. 8 is a block diagram showing a signal processing apparatus according to Embodiment 7 of the present invention. In the figure, the same reference numerals as those in Embodiment 1 denote the same or corresponding parts, and a description thereof will be omitted. In the sixth embodiment, the operator checks the output result obtained from the information processing unit 10 in advance and determines which of the plurality of types of sensors 1, 2, and 3 is most effective. Was. However, in the seventh embodiment, the information processing unit 10 determines which one of the plurality of types of sensors 1, 2, and 3 is most effective according to its own result, and switches the selector 7. .

As described above, according to the seventh embodiment, even when one processing error occurs in the pre-processing unit,
The processing can be continued without being affected by this, and the operator can confirm the output result from the information processing unit 10 obtained in advance and check the plurality of types of sensors 1, 2, 3
Since it is not necessary to determine which one is most effective when used, it is possible to obtain an effect that the burden on the operator can be reduced.

[0042]

As described above, according to the present invention, the output signals of all the sensors are inputted, and one of the signals corresponding to the instruction of the operator is input.
One of the output signals is selected by the selector, and the circuit pattern corresponding to the sensor is rewritten in software by the preprocessing FPGA unit. When one of the sensors is selected by an instruction from the operator, the selection is made by the control unit. The configuration is such that the circuit pattern corresponding to the sensor is selected and the circuit pattern of the preprocessing FPGA unit is rewritten, so that it is not necessary to own the preprocessing unit for each sensor, and the size of the device can be reduced. effective.

According to the present invention, the output signals of all the sensors are input, two output signals are selected by the selector according to the operator's instruction, and the circuit pattern corresponding to the sensors is converted into a plurality of preprocessing FPGA units. The software can be rewritten by software, and any one of the sensors is selected by the control unit in accordance with an instruction from the operator, and when the priority of the sensor is instructed by the operator, the sensor is designated as the selected sensor. The circuit pattern corresponding to the priority is selected and the circuit pattern of the preprocessing FPGA unit is rewritten, so that it is not necessary to own the preprocessing unit for each sensor, and the device can be downsized. There is an effect that the accuracy of the processing for each sensor in the preprocessing unit can be changed according to the plurality of sensors selected by the operator and their priorities.

According to the present invention, a circuit pattern corresponding to each sensor is set by a plurality of pre-processing units, a circuit pattern corresponding to the sensor is rewritten in software by a pre-processing FPGA unit, and a plurality of pre-processing FPGA units are used by a failure detection circuit. The preprocessing unit is monitored, and when a failure occurrence signal is received from any of the preprocessing units, the preprocessing unit in which the failure has occurred is notified, and the output signals of all the sensors are input. One output signal corresponding to the instruction of the failure detection circuit is selected, and when a notification of the occurrence of the failure is received from the failure detection circuit, the control unit selects the circuit pattern of the pre-processing unit in which the failure has occurred. In addition to writing to the processing FPGA unit, the sensor corresponding to the failed preprocessing unit and the preprocessing FPGA unit are connected, and set according to each sensor. Since a signal from the preprocessing FPGA unit is selected when a failure occurs in the corresponding preprocessing unit, when a failure occurs in the preprocessing unit for each sensor, the failure is automatically detected. Detect and FP for pre-processing
By using the GA unit as the pre-processing unit for the sensor, there is an effect that the processing can be continued.

According to the present invention, the circuit pattern corresponding to the sensor is rewritten in software by the plurality of preprocessing FPGA units, and one circuit pattern corresponding to the instruction of the operator is converted by the control unit into the plurality of preprocessing FPGAs. Section, input the output signals of all sensors, select one signal according to the operator's instruction with a selector, and select a plurality of preprocessing FPGAs.
And a plurality of preprocessing FPGs by the majority function unit.
Since the output from the A section is taken in and the result of the most matching number of outputs from the preprocessing FPGA section is output, even if a processing error occurs in the preprocessing section, this is also affected. Without this, there is an effect that the processing can be continued.

According to the present invention, the output signals of all the sensors are input, one output signal is selected by the selector according to the instruction of the operator, and the circuit pattern corresponding to the sensor is software-processed by the preprocessing FPGA unit. When one of the sensors is selected by an instruction from the operator, a circuit pattern corresponding to the sensor selected by the control unit is selected, and the circuit pattern of the preprocessing FPGA unit is rewritten. Therefore, it is not necessary to have a pre-processing unit for each sensor, and the size of the apparatus can be reduced.

[Brief description of the drawings]

FIG. 1 is a configuration diagram illustrating a signal processing device according to a first embodiment of the present invention.

FIG. 2 is a flowchart showing an operation of the signal processing device according to the first embodiment of the present invention.

FIG. 3 is a configuration diagram illustrating a signal processing device according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram illustrating a signal processing device according to a third embodiment of the present invention.

FIG. 5 is a configuration diagram illustrating a signal processing device according to a fourth embodiment of the present invention.

FIG. 6 is a configuration diagram showing a signal processing device according to a fifth embodiment of the present invention.

FIG. 7 is a configuration diagram illustrating a signal processing device according to a sixth embodiment of the present invention.

FIG. 8 is a configuration diagram illustrating a signal processing device according to a seventh embodiment of the present invention.

FIG. 9 is a configuration diagram illustrating a conventional signal processing device.

FIG. 10 is a configuration diagram illustrating a conventional signal processing device including a plurality of sensors.

[Explanation of symbols]

7, 13, 19 selector, 8 preprocessing FPGA unit,
11 control unit, 12, 14 circuit pattern, 18 failure detection circuit, 23 majority function unit.

Claims (8)

[Claims] In a signal processing device for performing signal processing and information processing on input data from a plurality of sensors, output signals of all the sensors are input, and one output signal according to an instruction of an operator is generated. A selector to be selected, a preprocessing FPGA unit that is rewritten in a software manner to a circuit pattern corresponding to the sensor, and a sensor corresponding to the selected sensor when any of the sensors is selected by an instruction from an operator. The above-mentioned circuit pattern is selected, and the pre-processing FPG is selected.
A signal processing device comprising: a control unit that rewrites a circuit pattern of an A section. 2. The signal processing according to claim 1, wherein the circuit pattern to be rewritten to the selector and the preprocessing FPGA unit is automatically selected and rewritten based on a result of the information processing. apparatus. 3. A signal processing device that performs signal processing and information processing on input data from a plurality of sensors, receives output signals of all the sensors, and outputs a plurality of output signals according to an instruction of an operator. A selector to select, a plurality of preprocessing FPGA units for rewriting a circuit pattern corresponding to the sensor in a software manner, and any one of the sensors is selected by an instruction from an operator, and the priority of the sensor is A control unit that, when instructed by the operator, selects the circuit pattern corresponding to the selected sensor and the instructed priority, and rewrites the circuit pattern of the preprocessing FPGA unit. Characteristic signal processing device. 4. A circuit pattern to be rewritten to a selector and a preprocessing FPGA unit, wherein a plurality of sensors to be used next and priority of the sensors are automatically selected and rewritten based on a result of information processing. The signal processing device according to claim 3. 5. A signal processing device for performing signal processing and information processing on input data from a plurality of sensors, comprising: a plurality of pre-processing units for setting a circuit pattern corresponding to each of the sensors; A preprocessing FPGA unit that rewrites a circuit pattern in a software manner, and the preprocessing unit that monitors the plurality of preprocessing units and receives a fault signal from any of the preprocessing units, in which a fault occurs. And a first selector for inputting output signals of all the sensors and selecting one output signal in accordance with an instruction from the failure detection circuit, and a notification of occurrence of a failure from the failure detection circuit When receiving the above, the circuit pattern of the pre-processing unit in which the failure has occurred is selected and written in the pre-processing FPGA unit, and the sensor and the sensor corresponding to the pre-processing unit in which the failure has occurred are selected. A control unit that connects to the preprocessing FPGA unit and a signal that is set according to each of the sensors and selects a signal from the preprocessing FPGA unit when a failure occurs in the preprocessing unit corresponding to the sensor. And a second selector that performs the operation. 6. A signal processing apparatus for performing signal processing and information processing on input data from a plurality of sensors, a plurality of preprocessing FPGA units for rewriting a circuit pattern corresponding to the sensors in a software manner, And a control unit for setting one circuit pattern according to the instruction in the plurality of preprocessing FPGA units, and output signals of all the sensors,
A selector for selecting one signal in accordance with an instruction of the operator and outputting the signal to the plurality of preprocessing FPGA units, and taking in outputs from the plurality of preprocessing FPGA units and outputting the signals from these preprocessing FPGA units. A majority function unit that outputs a result with the largest number of matches. 7. The signal processing according to claim 6, wherein a circuit pattern to be rewritten to the selector and the preprocessing FPGA unit is automatically selected and rewritten based on a result of the information processing. apparatus. 8. An output signal of all sensors is input, one output signal is selected by a selector according to an instruction of an operator, and a circuit pattern corresponding to the sensor is converted to a preprocessing FPG.
A section is rewritten in software, and when any one of the sensors is selected by an instruction from the operator, the circuit pattern corresponding to the sensor selected by the control section is selected, and the preprocessing FPGA section is selected. A method for reconfiguring a circuit pattern in a signal processing device, comprising rewriting a circuit pattern.