JPS62217347A - Bus diagnosing device - Google Patents

Abstract

PURPOSE:To completely diagnose hardware troubles of both address and data buses by securing loop connection between these buses by a changeover switch. CONSTITUTION:A changeover switch 10 is actuated by a signal received via a control bus 8 and loop connection is secured between an address bus 6 and a data bus 7. Then address data on the bus 6 is fetched by a microprocessor 3 via the bus 7. Then the address data is compared with the address data outputted first via the bus 6 through a microprogram. Thus it is possible to decide a specific abnormal bit of the data. In such a way, the hardware troubles of both buses 6 and 7 can all be diagnosed completely.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a device for diagnosing hardware failures in an address bus and a data bus in a node equipped with a microprocessor.

[Conventional technology]

FIG. 2 is a block diagram showing a device using a conventional microprocessor. In the figure, 1 is a microprogram memory ROM, 2 and 3 are a sequencer and a microprocessor that operate according to instructions from the microprogram memory ROMI, and 4 converts instructions from the microprogram memory ROM1 into control signals necessary for the device. 5 is a memory RAM to which an address bus 6, a data bus 7, and a control bus 8 are connected; 9 is a parity check generator.

Next, the operation of the device using the conventional microprocessor shown in FIG. 2 will be explained. The sequencer 2 outputs an address using the microprogram memory ROM1, and specifies the address of the memory RAM5 via the address bus 6. At this time, a parity check is performed on the address data by a parity check generator 9. Further, the microprocessor 3 is operated by the microprogram memory ROMI, and inputs and outputs data to and from the memory 1JRAM 5 via the data bus 78. At this time, a parity check is performed on the data by a parity check generator 9. Logic circuit 4 converts instructions from microprogram memory ROMI and enables memory RAM 5 via control bus 8.

[Problem that the invention seeks to solve]

Since the device using the conventional microprocessor is configured as described above, for example, if one of the address bus 6 and data bus 7 is disconnected, this will be treated as a one-pit abnormality. Although parity detection is possible, there is a problem in that if two buses are disconnected, parity detection cannot be performed for this and the bus is considered normal.

The present invention has been made to solve these problems, and it is an object of the present invention to provide a bus diagnostic device that can detect and check all hardware failures of address buses and data buses.

[Means for solving problems]

The bus diagnostic device according to the present invention is provided with a changeover switch in a device using a microprocessor, and the changeover switch is operated in response to a signal via a control bus to connect the address bus and data bus in a loop. By using a microprogram to compare and check the address data initially output via the data bus and the data returned via the data bus,
This system is designed to diagnose hardware failures in the address bus and data bus.

[Effect]

In the bus diagnostic device of the present invention, the changeover switch provided in the device using a microprocessor normally separates the address bus and the data bus, and the changeover switch is operated by a signal via the control bus. The address bus and data bus are connected in a loop.

〔Example〕

FIG. 1 is a block configuration diagram showing a bus diagnostic device in a device using a microprocessor, which is an embodiment of the present invention. The same or equivalent parts as in the conventional device shown in FIG. 2 are indicated by the same reference numerals. The detailed explanation will be omitted. In the figure, reference numeral 10 denotes a changeover switch that performs a switching operation in response to a signal via a control bus 8.

Next, the operation of the bus diagnostic device in the device using the microprocessor device, which is an embodiment of the present invention shown in FIG. 1, will be explained. The sequencer 2 outputs the FF pattern address using the microprogram memory ROM1. At this time, the instruction from the microprogram memory ROM 1 is converted by the logic circuit 4, and the changeover switch 1 is sent by a signal via the control bus 8.
0 is operated to connect the address bus 6 and data bus 7 in a loop. Then address bus 6
The address data is taken into the microprocessor 3 on the data bus 7. By comparing and checking the data captured in this way with the address data first output via the address bus 6 using a microprogram, it is possible to find out which bit of the data is abnormal, and this allows the address All hardware failures on bus 6 and data bus 7 can be diagnosed.

〔Effect of the invention〕

As explained above, in a bus diagnostic device, the present invention connects an address bus and a data bus in a loop using a changeover switch, and outputs address data first through the address bus and returns through the data bus. Since the system is configured to compare and check the stored data using a microprogram, hardware failures in the address bus and data bus can be easily and reliably diagnosed simply by using inexpensive switching elements such as changeover switches. It has the excellent effect of being able to.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a bus diagnostic device in a device using a microprocessor according to an embodiment of the present invention, and FIG. 2 is a block diagram showing a conventional device using a microprocessor. In the figure, 1... microprogram memory RO
M, 2... Sequencer, 3... Microprocessor, 4... Logic circuit, 5... Memory RAM, 6...
. . address bus, 7 . . . data bus, 8 . . . control bus, 9 . . . parity check generator, 10 . . . changeover switch. In each figure, the same reference numerals indicate the same or equivalent parts.

Claims (1)

[Claims] In hardware equipped with a microprocessor,
The address bus and the data bus are connected in a loop using a changeover switch, and the address data first output via the address bus and the data returned via the data bus are compared and checked using a microprogram. A bus diagnostic device for diagnosing hardware failures of the address bus and data bus.