JPH0243738A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To increase the concentration in an external base region, to make shallow the depth of an active base region, to make narrow the width of an emitter region and to increase the operating speed of a bipolar transistor by a method wherein the side surface of a poly Si film are oxidized, an impurity implanted in the poly Si film is diffused in a semiconductor layer to form the emitter region and the like. CONSTITUTION:A low-concentration second conductivity type impurity diffused region 7 is selectively formed on a first conductivity type semiconductor substrate 3, and after that, a poly Si film 8 and an Si nitride film 9 are formed one after the other on the whole surface. The films 8 and 9 are etched using a mask 10 of a prescribed pattern and a high-concentration second conductivity type impurity 11 is ion-implanted using the etching mask 10 as a mask. Moreover, after the mask 10 is removed, a heat treatment is performed, and subsequently, the whole is oxidized, a first conductivity type impurity 13 is ion- implanted in the film 8 through said film 9 and the impurity 13 in the film 8 is diffused in said region 7 by a heat treatment.

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device aimed at improving the pace and emitter formation method of a bipolar transistor.

<Prior Art> A conventional general method for manufacturing a bipolar transistor will be described with reference to FIGS. 2(a) to 2(Bd).

First, as shown in FIG. 2(a), a highly concentrated N-type impurity is selectively diffused onto a P-type semiconductor substrate 1, and then a lightly-concentrated N-type epitaxial layer 3 is grown over the entire surface. A high concentration N-type buried layer 2 is formed.

Next, as shown in FIG. 2(b), in order to perform element isolation,
An element isolation region 4 is formed by diffusing P-type impurities or forming an insulating film by selective oxidation, and a high concentration N-type buried layer 2 is formed.
An island-shaped N-type epitaxial layer 3 is formed. Then, high concentration N type impurities are diffused so as to reach the high concentration N type buried layer 2, thereby forming the collector extraction region 5.

Next, as shown in FIG. 2(C), a P-type impurity is selectively diffused into the low concentration N-type epitaxial layer 3 to form a base region 12, and then an N-type impurity is diffused into the base region 12. Diffusion forms an emitter region 14 to complete the NPN transistor.

Thereafter, as shown in FIG. 2(d), the insulating film 6 on each of the emitter, base, and collector regions is removed to form an emitter electrode 5, a base electrode 17, and a collector electrode 16, respectively.

<Problems to be Solved by the Invention> The factors that determine the operating speed of a bipolar transistor are the impurity concentration of the external base region under the base electrode,
The depth of the base region in contact with the bottom surface of the emitter region (hereinafter referred to as the "active base region") and the upper limit of the emitter region are important. It is necessary to reduce the depth of the area and the width of the ivy area.However, it is difficult to achieve all of these using traditional manufacturing methods.
This was an obstacle to increasing the speed of transistors.

Furthermore, when forming an opening in the insulating film on the emitter region to make contact with the emitter electrode, it is necessary to allow a margin for alignment to avoid shorting with the base region. It was a hindrance.

An object of the present invention is to provide a method for manufacturing a semiconductor device that solves the above problems.

Means for Solving the Problem> Selectively forming a low concentration impurity diffusion region of a second conductivity type on a semiconductor substrate of a first conductivity type, and then sequentially forming a polycrystalline silicon film and a silicon nitride film on the entire surface. . Then, the polycrystalline silicon film and the silicon nitride film are etched using a mask with a predetermined pattern, and high concentration second conductivity type impurities are ion-implanted using the etching mask as a mask. Furthermore, after removing the etching mask, heat treatment is performed, followed by oxidation of the entire film, and impurity ions of the first conductivity type are implanted into the polycrystalline silicon film through the silicon nitride film. the first in the membrane
By diffusing conductivity type impurities into the low concentration second conductivity type impurity diffusion region, an emitter is formed in a self-aligned manner, and the base region has two types of impurity concentrations and depths.

Effects> By using the method of manufacturing a semiconductor device of the present invention, it is possible to make the impurity concentrations of the active base region and the external base region different, and only the depth of the active base region can be made shallow.

In addition, the sides of the polycrystalline silicon film used as the emitter electrode are oxidized by selective oxidation, and the impurities implanted into the polycrystalline silicon film are diffused into the semiconductor layer by heat treatment to form the emitter region. It is possible to form an emitter region, and there is no need to provide a margin for mask alignment.

<Embodiment> FIGS. 1(a) to 1(f) are cross-sectional views showing an embodiment of the method for manufacturing a bipolar transistor according to the present invention.

In FIG. 1(a), based on a conventional method, a highly concentrated N-type buried layer 2 is selectively formed on the surface of a P-type semiconductor substrate 1, and an island surrounded by an element isolation region 4 is formed thereon. A lightly doped N-type epitaxial layer 3 is formed, and an N-type collector extraction region 5 is formed so as to reach the N-type buried layer 2 from the surface of the N-type epitaxial layer 3. After that, a silicon oxide film 6 of about 3000λ is provided on the entire surface, and a part of the silicon oxide film 6 on the base region and the collector lead-out region is removed using the photoresist as a mask, and then this photoresist is removed. A low concentration P-type impurity region 7 is formed by ion-implanting a P-type impurity, for example, boron, using a mask. The P-type impurity concentration at this time is about 10''cm-3, and a portion of the P-type impurity is also implanted into the N-type collector lead-out region 5, but since the concentration is low, there is no problem.

Next, as shown in FIG. 1(b), a polycrystalline silicon film 8 and a silicon nitride film 9 are sequentially formed by approximately 100X over the entire surface. Furthermore, as shown in FIG. 1C, the portions of the polycrystalline silicon film 8 that will become the emitter and collector electrodes are covered with a photoresist (10), and using this as a mask, the silicon nitride film 9 and the polycrystalline silicon film 8 are coated. Etch sequentially.

Then, using the photoresist 10 and the silicon oxide film 6 as a mask, a P-type impurity 11, such as boron, is ion-implanted.

At this time, the P-type impurity concentration is higher than that of the P-type impurity region 7 described earlier, and is about 1019 m-3 to 1020 m-3'.

7 After removing the photoresist 1O, heat treatment is performed to oxidize the entire surface using the silicon nitride film 9 as an oxidation-resistant mask.
As shown in FIG. 1D, the external base region 12b1 and the lightly doped P-type impurity region 7 are not diffused as deeply as the external space region 12b, forming a shallow active base region 12a. Since the surface of the polycrystalline silicon film 8 is covered with the silicon nitride film 9, it is not oxidized, and only the side surfaces are oxidized and become smaller, so that it is separated from the high concentration external space region 12b.

Thereafter, an N-type impurity 13, for example arsenic, is implanted into the polycrystalline silicon film 8 through the silicon nitride film 9. By applying heat treatment, the emitter region 1 is formed as shown in Fig. 1(e).
4 is formed, and the polycrystalline silicon film 8 serves as an emitter electrode 15.
．． This becomes the collector electrode 16.

After removing the silicon nitride film 9, the silicon oxide film 6a on the external base region 12b is opened, and as shown in FIG.
An aluminum-based alloy film with a thickness of about 8000 to 100X is formed on the entire surface and etched into a predetermined pattern to form electrode/wiring regions.

The above explanation was about NPN) transistors, but PN
A similar effect can be obtained with a P transistor.

<Effects of the Invention> According to the present invention, the concentration of the external space region does not decrease, the base resistance does not increase, the active base region is formed into a shallow junction, and the emitter can be formed in a self-aligned manner, thereby making it possible to form a fine emitter. By narrowing the width of the ivy region, the base resistance can be lowered and a transistor with excellent high speed and high frequency performance can be formed.

Further, by using a selective oxidation method, it is possible to reduce the step difference, realize a flat device structure, and provide a highly integrated transistor.

[Brief explanation of the drawing]

FIGS. 1(a) to (f) are cross-sectional views showing the manufacturing process of an embodiment of the present invention, and FIGS. 2(a) to (d) are sectional views showing the manufacturing process of a conventional general bipolar transistor. FIG. 1... P-type semiconductor substrate, 2... High concentration N-type buried layer. 3...Low concentration N-type epitaxial layer, 4...Element isolation region, 5...High concentration N-type collector extraction region. 6.6a...Silicon oxide film, 7...Low concentration P type impurity region, 8...Polycrystalline silicon film, 9...Silicon nitride film, 10...Photoresist, 11...P type impurities. 12... Base region, 12a... Active base region. 12b...external pace region, 13...N-type impurity,
14... Emitter region, 15... Emitter electrode, 1
6...Collector electrode, 17...Base electrode. Agent Patent Attorney Takeshi Sugiyama (and 1 other person) Sonodai

Claims (1)

[Claims] 1. A step of selectively forming a low concentration impurity diffusion region of a second conductivity type on a semiconductor substrate of a first conductivity type, and then sequentially forming a polycrystalline silicon film and a silicon nitride film on the entire surface. , a step of sequentially etching the polycrystalline silicon film and the silicon nitride film using an etching mask with a predetermined pattern, and further ion-implanting a highly concentrated second conductivity type impurity using the etching mask as a mask; removing the etching mask; After that, a heat treatment is performed, followed by a step of oxidizing the whole, ion-implanting an impurity of a first conductivity type into the polycrystalline silicon film through the silicon nitride film, and a step of ion-implanting an impurity of a first conductivity type into the polycrystalline silicon film through the heat treatment. A method for manufacturing a semiconductor device, comprising the step of diffusing a type impurity into the low concentration second conductivity type impurity diffusion region.