JPH024316U - - Google Patents

Description

[Brief explanation of drawings]

Fig. 1 is a block diagram of an embodiment of the present invention;
The figure is a signal waveform diagram of the block diagram of FIG. 1...2 ^Quaternary counter, 2...Decoder, 3...
...Data selector, 4...D flip-flop,
5... Duty setting circuit, 6... Clock pulse, 7... Counter output pulse, 8... Set pulse, 9... Decoder output pulse, 10... Reset pulse, 11... Q terminal output signal.

Claims (1)

[Scope of claims for utility model registration] (A) Externally input clock pulses 2 ⁿ
By repeatedly and continuously counting clock pulses one by one, the frequency of the clock pulses is reduced to 1/2 ¹ , ..., 1/2 ⁿ (
2 ⁿ -ary counters that generate n types of pulses having different frequencies (n is a positive integer) and output the n types of pulses from separate terminals; (B) Output from the 2 ^n- ary counters; every time the 2 ^n- ary counter counts 2 ⁿ clock pulses, the received n
^{( C _} ) A duty setting circuit that encodes a setting value input from the outside to determine the duty and outputs it as a duty setting value signal; (D) A duty setting circuit that receives the duty setting value signal and that the ^2n- ary counter generates ²ⁿ clock pulses. Each time counting, the second to second ⁿ single pulses are received from the decoder, and the single pulse corresponding to the set value is selected from among the second to second ⁿ single pulses and output. (E) The above two ^n- ary counters select two clock pulses.
Every time ⁿ pieces are counted, the first single pulse is received as a set pulse, the single pulse output from the data selector is received as a reset pulse, and a pulse with a duty corresponding to the set value is generated and continuously A pulse generation circuit comprising: a D flip-flop that outputs an output.