JPH0241659Y2 - - Google Patents
Info
- Publication number
- JPH0241659Y2 JPH0241659Y2 JP1985170283U JP17028385U JPH0241659Y2 JP H0241659 Y2 JPH0241659 Y2 JP H0241659Y2 JP 1985170283 U JP1985170283 U JP 1985170283U JP 17028385 U JP17028385 U JP 17028385U JP H0241659 Y2 JPH0241659 Y2 JP H0241659Y2
- Authority
- JP
- Japan
- Prior art keywords
- terminal
- light emitting
- terminals
- joint
- mounting board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000000758 substrate Substances 0.000 claims description 18
- 238000003780 insertion Methods 0.000 claims description 15
- 230000037431 insertion Effects 0.000 claims description 15
- 238000010586 diagram Methods 0.000 description 10
- 238000005476 soldering Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 239000004020 conductor Substances 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- 239000011521 glass Substances 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000005011 phenolic resin Substances 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
Landscapes
- Devices For Indicating Variable Information By Combining Individual Elements (AREA)
- Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985170283U JPH0241659Y2 (US07122547-20061017-C00273.png) | 1985-11-05 | 1985-11-05 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1985170283U JPH0241659Y2 (US07122547-20061017-C00273.png) | 1985-11-05 | 1985-11-05 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6279284U JPS6279284U (US07122547-20061017-C00273.png) | 1987-05-21 |
| JPH0241659Y2 true JPH0241659Y2 (US07122547-20061017-C00273.png) | 1990-11-06 |
Family
ID=31104870
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1985170283U Expired JPH0241659Y2 (US07122547-20061017-C00273.png) | 1985-11-05 | 1985-11-05 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0241659Y2 (US07122547-20061017-C00273.png) |
-
1985
- 1985-11-05 JP JP1985170283U patent/JPH0241659Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6279284U (US07122547-20061017-C00273.png) | 1987-05-21 |
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