JPH0241442U - - Google Patents
Info
- Publication number
- JPH0241442U JPH0241442U JP1988120044U JP12004488U JPH0241442U JP H0241442 U JPH0241442 U JP H0241442U JP 1988120044 U JP1988120044 U JP 1988120044U JP 12004488 U JP12004488 U JP 12004488U JP H0241442 U JPH0241442 U JP H0241442U
- Authority
- JP
- Japan
- Prior art keywords
- recess
- wiring
- insulating film
- insulation film
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
- 239000004065 semiconductor Substances 0.000 claims description 5
- 230000002093 peripheral effect Effects 0.000 claims description 4
- 239000011229 interlayer Substances 0.000 claims description 2
- 238000009413 insulation Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
Description
第１図は本考案半導体装置の一つの実施例を示
す周辺部の断面図、第２図Ａ乃至Ｆは第１図に示
した半導体装置の製造方法を工程順に示す半導体
装置周辺部の断面図、第３図は従来例を示す半導
体装置周辺部の断面図である。 符号の説明、２，３…絶縁膜、４…配線、５…
層間絶縁膜、１０…第１の凹部、１１…間隙部、
１２…第２の凹部。
す周辺部の断面図、第２図Ａ乃至Ｆは第１図に示
した半導体装置の製造方法を工程順に示す半導体
装置周辺部の断面図、第３図は従来例を示す半導
体装置周辺部の断面図である。 符号の説明、２，３…絶縁膜、４…配線、５…
層間絶縁膜、１０…第１の凹部、１１…間隙部、
１２…第２の凹部。
Claims (1)
- 【実用新案登録請求の範囲】 周辺部において絶縁膜表面に第１の凹部が形成
され、 上記第１の凹部の略中心部に配線が形成され、 上記絶縁膜の第１の凹部の外側の部分の表面に
、上記配線の幅と略等しい間隔を措いて少なくと
も１つのダミー用の第２の凹部が形成され、 上記絶縁膜上に上記配線及び各凹部を覆う層間
絶縁膜が形成されてなる ことを特徴とする半導体装置。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988120044U JP2538245Y2 (ja) | 1988-09-12 | 1988-09-12 | 半導体装置 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988120044U JP2538245Y2 (ja) | 1988-09-12 | 1988-09-12 | 半導体装置 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0241442U true JPH0241442U (ja) | 1990-03-22 |
| JP2538245Y2 JP2538245Y2 (ja) | 1997-06-11 |
Family
ID=31365798
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988120044U Expired - Lifetime JP2538245Y2 (ja) | 1988-09-12 | 1988-09-12 | 半導体装置 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2538245Y2 (ja) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325951A (ja) * | 1986-07-17 | 1988-02-03 | Nec Corp | 半導体装置 |
| JPS63211739A (ja) * | 1987-02-27 | 1988-09-02 | Nec Corp | 半導体装置 |
-
1988
- 1988-09-12 JP JP1988120044U patent/JP2538245Y2/ja not_active Expired - Lifetime
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6325951A (ja) * | 1986-07-17 | 1988-02-03 | Nec Corp | 半導体装置 |
| JPS63211739A (ja) * | 1987-02-27 | 1988-09-02 | Nec Corp | 半導体装置 |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2538245Y2 (ja) | 1997-06-11 |