JPH024139B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a shotgun barrier gate field effect transistor.

GaAs semiconductors have an electron mobility that is 5 to 6 times higher than that of Si, and because of this high-speed characteristic, they have recently been used as ultra-high-speed integrated circuits (hereinafter referred to as ICs).
Research and development is actively being carried out to apply this technology to As the active element of this GaAsIC, a Schottky barrier gate field effect transistor (hereinafter referred to as MESFET) as shown in FIG. 1 has basically been proposed.

This is called a planar structure, and as shown in Fig. 1, an n-type active layer 5 with a thickness of about 0.2 μm is formed on a semi-insulating GaAs substrate 4 by air epitaxial growth or ion implantation, and a photoresist film is used. The gate electrode 1 is formed by a lift-off method, etc., and the mask is aligned, and the source and drain ohmic electrodes 2, 3 are formed by a similar lift-off method.
It has a relatively simple structure.

However, in the manufacturing method of such a planar structure, alignment is necessary to form an ohmic electrode, and the alignment accuracy is about ±0.5 μm even with the best equipment, and about ±1.0 μm with practical equipment. be. Manufactured using such alignment equipment
In MESFET, it is practically difficult to reduce the electrode spacing between the ohmic electrode and the gate electrode to 1.0 μm or less.

On the other hand, on the surface of the GaAs active layer between the gate electrodes, a surface depletion layer 6 is generated as shown in Figure 2 due to disturbance of crystallinity and adsorption of gas on the surface, and the effective active layer becomes thinner, resulting in ohmic When the distance between the electrode and the gate electrode is long, the active layer resistance between the gate and source (source series resistance) increases, and the mutual conductance gm decreases significantly, resulting in a good FET.
Difficult to obtain characteristics.

The purpose of the present invention was made in view of the above problems, and in order to reduce the influence of the surface depletion layer and obtain good FET characteristics, the electrode spacing between the ohmic electrode and the gate electrode is set to 1.0. It is an object of the present invention to provide a method for manufacturing a field effect transistor, which enables formation of a gate electrode and ohmic electrodes of a source and a drain in a self-aligned manner.

According to the present invention, there are a step of forming a gate electrode on an active layer of a semiconductor substrate, a step of covering the vicinity of the gate electrode with a coating layer, a step of depositing an ohmic electrode, and a step of forming a resist film on the ohmic electrode. A method for manufacturing a semiconductor device is obtained, which comprises the step of removing the ohmic metal on the coating layer by coating and dry etching to form source and drain electrodes.

Next, embodiments of the present invention will be described using the drawings.
FIGS. 3a to 3i are process diagrams showing an embodiment of the method for manufacturing a semiconductor device of the present invention.

As shown in Figure 3a, the impurity concentration is approximately 2×10 ¹⁷ cm formed by ion implantation on a semi-insulating GaAs substrate.
^-3 , on the n-type operating layer 24 with a thickness of about 0.2 μm, the first
Aluminum Al was sputter-deposited to a thickness of 2.0 μm as the layer 21, and silicon dioxide SiO ₂ was deposited as the second layer 22.
A 0.3 μm spatch deposition process is performed, and a 1.0 μm photoresist film is applied as the third layer 23 to form an opening 25 for a gate electrode pattern with a length of 1.0 μm.

Then, as shown in FIG. 3b, the SiO ₂ film 22 is side-etched by 0.5 μm using buffered hydrofluoric acid to form an opening 26 wider than the opening 25, and the Al layer 21 is then etched.
Side etching is performed by 1.5 μm using phosphoric acid at 60° C. to form an opening 27 wider than the opening 26, and as shown in FIG.
is formed, the photoresist film 23 is dissolved with acetone, the excess gate metal layer 30 on the photoresist film 23 is also removed at the same time, and silicon monoxide SiO is deposited on the gate electrode 1 with a thickness of 0.9 μm as shown in FIG. 3d. A covering layer 28 is deposited and defined by the openings 26 in the second layer.
form.

Next, as shown in Fig. 3e, the Al layer 21 is dissolved in phosphoric acid at 60°C to remove the excess layer, leaving the gate electrode 1 covered with the covering layer 28, and as shown in Fig. 3f. Source and drain electrodes 2 and 3 are formed by vertically depositing ohmic electrodes AuGe/Pt with a thickness of 2000 Å.
is formed, and the photoresist film 2 is formed as shown in FIG.
9 was spin-coated to a thickness of 1.0 μm and dried, as shown in Figure 3h.
By rotating the substrate and etching away the ohmic metal layer 31 on the coating film 28 by Ar ion milling at an ion incidence angle of 45° as shown in FIG. 3, the remaining photoresist film 29 is removed as shown in FIG.
By removing with a stripping liquid, a GaAs MESFET in which the source and drain electrodes 2 and 3 are separated by the covering layer 28 and formed in a self-aligned manner is completed.

As the buffered hydrofluoric acid solution for side-etching the SiO ₂ layer 22, when a mixture of 50% hydrofluoric acid water and 40% ammonium fluoride water at a ratio of 1:14 is used at 10°C, it is possible to side-etch the SiO 2 layer 22 by 0.5 μm. The time is 8 minutes, and the variation is as small as ±0.1 μm, making it highly accurate. Furthermore, in order to reduce the width of the coating layer, heater-deposited silicon monoxide SiO was used, but silicon dioxide SiO ₂ , silicon nitride, titanium nitride, etc. may also be used, and these can be deposited by electron beam evaporation or sputter evaporation. Good too.

According to this embodiment, the distance between the gate electrode and the source and drain electrodes is determined by the width of the covering layer. In this example, the width of the covering layer is the second layer 2.
It is determined by the amount of side etching in step 2, and can easily be set to 1 μm or less. The amount of side etching of the silicon dioxide SiO ₂ used as the second layer 22 can be controlled by the etching time by determining conditions such as the composition and temperature of the etching solution.

The gate width formed in this way is 20μ.
m, gate length 1.0μm, electrode spacing 0.5μm.
The mutual conductance gm of the MESFET is 3.2 mS, and the gm of the conventional photoresist film formed with an electrode spacing of 1.2 μm is 1.8 mS.
gm of MESFET with short electrode spacing according to the present invention
is almost double the value of the conventional one.

According to the present invention, the electrode spacing between the ohmic electrode and the gate electrode can be reduced by reducing the influence of the surface depletion layer.
A field effect transistor that can be made smaller than 1.0 μm can be obtained.

[Brief explanation of drawings]

Figure 1 is a cross-sectional view of the most basic conventional Schottky gate MESFET with a planar structure. Figure 3a
-i are process diagrams for explaining one embodiment of the manufacturing method of the present invention. In the figure, 1... gate electrode, 2... source electrode, 3... drain electrode, 4... semi-insulating substrate, 5, 24... semiconductor operating layer, 6... surface depletion layer, 21... first layer, 22... second layer , 23...third layer, 25, 26, 27...openings in each layer, 28...covering layer.

Claims (1)

[Claims] 1. A step of forming a gate electrode on the active layer of the semiconductor substrate, a step of covering the vicinity of the gate electrode with a coating layer, a step of depositing an ohmic metal, and a step of applying a resist film on the ohmic metal and dry etching. 1. A method of manufacturing a semiconductor device, comprising the step of removing the ohmic metal on the coating layer by a method to form source and drain electrodes.