JPS5965484A - Manufactue of semiconductor device - Google Patents

Abstract

PURPOSE:To realize excellent FET characteristics through reducing influence of a surface depletion layer by a method wherein the distance between ohmic electrodes and a gate electrode is not more than 1.0mum and the gate electrode and source/drain ohmic electrodes are formed by self-alignment. CONSTITUTION:An SiO2 film 22 is side-etched for the formation of an opening 26 larger than an opening 25. Further, an Al layer 21 is side-etched for the formation of an opening 27 larger than the opening 26, and a gate electrode 1 is formed, by means of heater-evaporation of Al, with its size dependent upon the size of the opening 25. Unnecessary part is removed of the Al layer 21, and the gate electrode 1 is retained, covered with a coating layer 28. Vertical evaporation of an ohmic metal results in the formation of a source, drain electrodes 2, 3. The substrate is rotated and subjected to etching effected by an ion beam with an angle of incidence of 45 deg. for the elimination of an ohmic metal layer 31 located on the coating film 28. By this, a GaAs MESFET is formed wherein a source, drain electrodes 2, 3 are formed by self-alignment, separated from the coating film 28. With the effect of the surface depletion layer being reduced as such, the distance can be not more than 1.0mum between the ohmic electrodes and the gate electrode.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method for manufacturing a semiconductor device, and more particularly, to a method for manufacturing a Schottky barrier gate field effect transistor.

GaAS semiconductors have an electron mobility that is 5 to 6 times larger than that of Si, and this h-speed is a major feature, so
Recently, research and development has been actively conducted on applications to ultra-high-speed integrated circuits (hereinafter referred to as ICs).

The active element of Jin's G&A111C is basically the first one.
A Schottky barrier gate field effect transistor (hereinafter referred to as MESFET) as shown in the figure has been proposed.

This is called a planar structure, and as shown in FIG. 1, an n-type active layer 5 (about 0.2 μrrl thick) is formed on a semi-insulating QaAa substrate 4 by epitaxial growth or ion implantation. This is a relatively simple structure in which one gate electrode is formed by a method, etc., the mask is fully aligned, and ohmic electrodes 2 and 3 for the source and drain are formed by a lift-off method.

However, in the manufacturing method of such a planar structure, is it possible to use ohmic electrodes? Alignment is necessary to form, and the alignment accuracy is around ±0.5 μm even with the best equipment.
In a practical machine, it is about ±1.0 μm.

An alignment device like this? Ml produced using: 5FE
T is the electrode distance t1 between the ohmic conductor and the gate electrode.
．． It is actually difficult to reduce the thickness to 0 μm or less.

On the other hand, on the surface of the QaAs active layer between the gate %I poles, due to disturbances in crystallinity and gas adsorption on the surface, a surface depletion layer 6 is generated as shown in Figure 2, and the effective active layer becomes thinner. , ohmic electrode and gate electrode e and O'a, when the electrode spacing is long, the a, 0 layer resistance (source series resistance) of the gate saw increases, the mutual conductance gm decreases significantly, and a good It is difficult to obtain FET4''1' characteristics.

The object of the present invention has been made in view of the above-mentioned problems, and is to reduce the shadow #' of the surface depletion layer and improve F
In order to obtain the ET characteristics, it is possible to make the electrode distance between the ohmic Royle electrode and the gate electrode less than hi, oμrn.
[! It is an object of the present invention to provide a method for manufacturing a field effect transistor in which the gate 1m4b and the ohmic electrodes of the source and drain are formed in a self-aligned manner.

According to the present invention, a step of forming a gate electrode on a semiconductor substrate active layer, a step of covering the entire vicinity of the gate electrode with a covering layer,
A step of depositing ohmic gold R16, and a step of removing the ohmic metal on the coating layer to form source and drain electrodes. A method for manufacturing a semiconductor device is obtained.

Next, embodiments of the present invention will be described with reference to the drawings.

3(a) to 3(i) are examples of the method for manufacturing a semiconductor device of the present invention? FIG.

As shown in FIG. 3(a), an impurity concentration of 2×10 Cm was formed by ion implantation on a semi-insulating GaAs substrate.
On the n-type active layer 24 with a thickness of approximately 0.2 μm, aluminum Atk 2.0 μm is sputter-deposited as the first layer 21, and silicon dioxide 5iO2t0.3 is used as the second layer 22.
A 1.0 μm thick photoresist film is applied as the third layer 23 by μm sputter evaporation, and an opening 25i of a gate electrode pattern with a length of 1.0 μm is provided.

3(b) VC, as shown, 2 on the SiO2 film 22.
Buffered hydrofluoric acid was side-etched by 0.5 μm for two days to form an opening 26 wider than the opening 25, and the At layer 21 was then etched by 60 μm.
Opening 2 was side-etched by 1.5 μm using phosphoric acid at °C.
6, and as shown in FIG. 3(e), the gate electrode 1 defined by the opening 25 is formed by evaporating aluminum Atf0.3 μm as gate metal scraps using a heater, and then dissolving the photoresist film 23'lH with acetone. The excess gate metal layer 30 on the photoresist film 23 is also removed at the same time, and as shown in FIG.
The coating layer 28 is formed according to the following. .

Next, as shown in FIG. 3(e), the At layer 21' is dissolved in phosphoric acid at 60°C to remove the excess layer, and the gate electrode 1 is removed from the covered layer 21'.
Something covered in? As shown in Fig. 3(f), ohmic gold FAA u, Ge -P t 2000 A k
Thin source and drain electrodes 2 by vertical deposition
．． 3 is formed, a photoresist film 29 is spin-coated to a thickness of 1.0 μm as shown in FIG. 3(g) and dried, and the substrate is rotated to remove ions by vCARr ion milling 9 as shown in FIG. 3(h). The ohmic metal layer 31 on the coating film 28 is removed by etching at an incident angle of 45° until the ohmic metal layer 31 is removed.
As shown in Figure (i), the remaining photoresist film 29 is removed with a stripping solution, and the source and drain electrodes 2,
3 are separated by a covering layer 28 to complete a self-aligned GaAs MESFET.

The buffered hydrofluoric acid solution for etching all 22 of the SiO□ layers 22 is a mixture of 50% hydrofluoric acid water and 40% ammonium fluoride water vt: t4.
．． It takes 8 minutes to perform the 5 μm side etching, and the variation is as small as ±0.1 μm, making the process highly accurate. Further, in order to reduce the width of the Jaj-, heater-deposited silicon monoxide 5iOt- was used, but silicon dioxide 5io2, silicon nitride, titanium nitride, etc. may also be used, and these can be deposited by electron beam evaporation or sputter evaporation. Good too.

According to this embodiment, the distance between the gate electrode and the source and drain electrodes is determined by the width of the covered layer. In this embodiment, the width of the covering layer is determined by the amount of side etching of the second layer 22, and can easily be set to 1 μm or less. The silicon dioxide 5i02 used as the second layer 22 can be controlled by controlling the side etching amount and etching time by determining conditions such as the composition and temperature of the etching solution.

Then, the gate width 20 μm, gate length 1.0 μm, and electrode spacing 0.5 μm c7) MISF
The mutual 'zy ductance gm of ET is 3.2 mS, and as in the conventional case, the electrode spacing is 1
．． The gm of the MESFET formed with a thickness of 2 μm is 1.8 mS, and the gm of the MESFET with short electrode spacing according to the present invention is nearly twice that of the conventional one.

According to the present invention, it is possible to obtain a field effect transistor in which the influence of the surface depletion layer is reduced and the distance between the ohmic electrode and the gate electrode can be reduced to 1.0 μm or less.

[Brief explanation of the drawing]

Figure 1 is a cross-sectional view of the most basic conventional planar structure Schottky gate MESFET - 1 Figure 2 shows a state in which a surface depletion layer is generated on the active layer surface of this planar structure MESFET? The figures shown in FIGS. 3(a) to 3(i) are process diagrams for explaining one implementation of the manufacturing method of the present invention. In the figure, 1... Gate electrode, 2... Source electrode, 3... Drain electrode, 4... Semi-insulating substrate, 5.24... ...Semiconductor operating layer, 6...
...Surface depletion layer, 21...First layer, 22...
...Second layer, 23...Third layer, 25926
．． 27... Openings in each layer, 28... Covering layer. Fig. 1 Fig. 2 (d) (shi) (C) Fig. 3

Claims (1)

[Claims] A step of forming a gate electrode on a semiconductor substrate active layer, a step of covering the vicinity of the gate electrode with a covering layer, a step of depositing an ohmic metal, and a step of completely removing the ohmic metal on the covering layer to form a source. and a process for forming a drain electrode sound.