JPH0239541A - Semiconductor device - Google Patents

Abstract

PURPOSE:To lower the OFF-current of an N-channel TFT and make the maximum driving frequency higher by making the activated layers of channels N- poly-Si, and besides by making the contact hole area of the source.drain sections of the N-channel transisitor(FET) smaller than that of a P-channel FET, or using Al 2 to 3wt.% Si as an electrode material used for the source.drain contact sections. CONSTITUTION:A gate electrode 11 is provided in the center of an N-poly-Si activated layer 10 for an N-channel TFT and an N-poly-Si activated layer 9 for a P-channel TFT formed in an island shape, and a source region 12 and a drain region 13 are provided by self-alignment on the left and right respectively. The area of the contact hole 14 of the P-channel TFT is made larger than that of the contact hole 15 of the N-channel TFT. As alternative means for increasing a contact resistance value being below a ihreshold value of the N- channel TFT, and Al 2-3wt.% Si may be employed as a material for a contact electrode 16.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention is a thin film transistor (hereinafter referred to as TPT) fabricated on an insulating substrate used in line sensor drive circuits, active matrix LCD drive circuits, etc. The present invention relates to a semiconductor device.

[Conventional technology and its problems]

Currently, office automation (OA) equipment is rapidly becoming lighter, thinner, and smaller. For example, an image reading device, which is important as a sending device in a facsimile, has been miniaturized by a combination of a reduction optical system and a C0D (charge coupled device) using single crystal Si.

Recently, 1x sensors that do not require this reduction optical system have become mainstream. A-5i:H or the like is used for the photoconductive layer of the sensor array of this same-size sensor, and it is formed on an insulating substrate.

Methods for mounting a circuit that reads signals from the sensor array include a method using an external LSI and a method of fabricating a TPT on the same substrate as the sensor array. Considering the miniaturization of devices, the latter method is far more advantageous than the former. Materials for the active layer in which the TPT channel is formed include a-SL and pol.
Y-5L is used, and when high switching speed is required, poly-Si, which has higher carrier mobility than a-5L, is used.

The same thing can be said about LCDs (liquid crystal displays) as another example. In other words, compared to a simple matrix display driven by an external LSI, an active matrix display incorporating TPT has a much smaller device size when the screen size is the same; The display quality is also excellent.

FIG. 2 shows an example of a TPT conventionally used in these equal-magnification sensors and LCD drive circuits. The TPT in FIG. 2 has an active layer 5, a gate insulating film 4, and a gate insulating film 4 on an insulating substrate. After forming a gate electrode 6, a source 2, and a drain 3, an interlayer insulating film 7 is deposited, a contact hole is formed in the interlayer insulating film 7, and then a metal electrode wiring 8 is formed.

In such a TPT, when a poly-Si thin film deposited by LPCVD is used as the active layer, this poly-Si thin film is deposited by LPCVD.
Since the conductivity type of ly-5L is n-, it becomes a depression drive type when an N-channel transistor is manufactured. On the other hand, the P-channel transistor is driven by enhancement. Therefore, if a CMOS shift register is constructed by combining it with a P-channel transistor,
As mentioned above, since the ratio of the on/off current values of the N-channel transistor is small, problems such as a low driving frequency of the shift register and a large current consumption have arisen.

Conventionally, in order to solve these problems, boron was implanted into the active layer of an N-channel transistor by ion implantation to change the conductivity type of the active layer from n- to p-, thereby realizing enhancement drive. However, this method has problems such as high equipment cost and low throughput.

[Problem to be solved by the invention]

In the present invention, when poly-Si deposited by the LPVCD method is used as an active layer forming a channel, these ρol
Although y-Si has an n- conductivity type, it can be used in CMO without changing from n- to p- even in N-channel transistors.
Even if you configure an S shift register.

It is an object of the present invention to provide a semiconductor device that does not have the above-mentioned problems.

[Means to solve the problem]

The present invention provides a semiconductor device composed of thin film transistors fabricated on an insulating substrate, in which the active layer forming the channel of each thin film transistor is n-poly-5i, and the contact hole area of the source and drain portions is larger than that of an N-channel transistor. is smaller than the P-channel transistor, or the electrode material used for the source and drain contact parts is Al-2~3%it%S.
i.

In the present invention, even if the active layer forming the channels of both the N-channel transistor and the P-channel transistor is n-poly-5i, the contact resistance in the gate voltage region below the threshold voltage of the N-channel TPT can be reduced. This was completed based on the finding that increasing the off-current value of the N-channel TPT and increasing the on/off current ratio are brought about.

As a means for this purpose, in the present invention, the contact hole area of the source and drain portions is made smaller for N-channel transistors than for P-channel transistors, or
Alternatively, the electrode material used for the source and drain contact portions is Al1-2 to 3wt%Si.

FIG. 1 shows an embodiment of the present invention.

In this FIG. 1, a P channel TF formed in an island shape
N-poly-Si active layer 9 for T, N-channel TFT
A gate electrode 11 is located at the center of the low poly-5i active layer 10, and a source region 1 is formed on the left and right sides by self-aligned lines.
2. A drain region 13 is provided. The contact hole 14 of the P-channel TPT is formed to have a larger area than the contact hole 15 of the N-channel TPT. usually.

The area of contact hole 14 of P-channel TPT is 8
The area of the contact hole 15 of the N-channel TPT is preferably about 30 to 50% smaller than this.

In Figure 1 above, the contact hole area of the N-channel TPT is smaller than that of the P-channel TPT.
As another means of increasing the contact resistance below the threshold voltage of the N-channel TPT, the contact electrode 1
As the material of No. 6, Al-2 to 3 wt% Si can be used. In this case, the Si content added to Al is 2wt.
%, the contact resistance is small and the N-channel transistor does not perform enhancement drive;
If it exceeds 5, the contact resistance increases and sufficient on-current cannot be obtained, so it is necessary to add 2 to 3 wt%. In addition, this Al-2~3wt%S is used as an electrode material.
i may be used, and the area of the contact hole may be set as in the embodiment shown in FIG.

A CMOS shift register made of TPTs configured in this manner has a higher driving frequency and lower current consumption than conventional ones.

An example of manufacturing such TPT will be explained with reference to FIG.

Example 1 (1) Transparent quartz glass (50
++oeX 250mm
Deposit a ly-Si thin film (1700 nm thick). The conditions are as follows.

Substrate temperature: 629° C. SiH, flow rate: 145 SCCM pressure: 0.13 Torr (2) The poly-Si active layer 18 is formed by patterning (see FIG. 3(a)).

(3) The poly-Si active layer is thermally oxidized in dry oxygen to form a gate insulating film 19 with a thickness of 1300 nm.

The oxidation conditions are as follows.

Insertion/removal temperature: 600℃ thermal oxidation temperature
1050℃ heating rate 3℃/m1n (4) poly-Si gate electrode 20 WOLPCV
D Hounyo IJ Deposits to a thickness of about 5,000 people.

(5) Patterning the ρoly-5i gate electrode 20 and gate insulating film 19 to a predetermined channel length (third
(See figure (b)).

(6) PSG (for N-channel TPT production)
After depositing a film or a BSG (in the case of P-channel TPT fabrication) film by a coating method, the source 2I and drain 22 regions are formed by self-line by thermal diffusion, and then the PSG film or BSG film that has become a diffusion source is removed ( Figure 3 (c
)reference).

(7) A PSG film 23 is deposited to a thickness of 1 μm by the LPCVD method to serve as an interlayer insulating film (see FIG. 3(d)).

The film forming conditions are as follows.

Substrate temperature 430℃SiH4 flow rate
88 SCCMO, If
200#PH, 3n Pressure 0.20 Torr (8) Open the contact hole 24 and take out the Al electrode wiring ts25 from the source and drain (Fig. 3(a)
reference).

Contact hole size is P channel TPT 8μm x 8μm N channel T
PT 4μm×4μm (9) Perform plasma hydrogen treatment.

The conditions are as follows.

Substrate temperature H2 Flow rate pressure RF power time 350°C 1003 CCM 1, OTorr 240 W (13,56 MHz) 5 min Example 2 In process (8) of Example 1, A as the electrode wiring 25
Q-2, 5 wt% Si was used.

N-channel TPT manufactured by the process described above
When a shift register was configured with CMO3 using a P-channel TPT, the maximum drive frequency was 2 MHz or more, and the current consumption was sufficiently small.

[Action/effect of the invention]

In the present invention as described above, the contact hole size of the N-channel TPT is made smaller than that of the P-channel,
Alternatively, Al-2~3wt%Si can be used as the contact electrode material.
Since each transistor is driven by enhancement, the contact resistance in the gate voltage region below the threshold voltage can be increased, and the off-state current of the N-channel TPT can be sufficiently lowered. As a result, side O8
When a shift register is configured with this, its maximum drive frequency is significantly improved compared to the conventional one.

[Brief explanation of the drawing]

FIG. 1 is an explanatory plan view showing one embodiment of the present invention. FIG. 2 is a sectional view showing an example of a conventional TPT. FIG. 3 is an explanatory diagram showing an example of the process of manufacturing TPT in the present invention. 5...Active layer 6,11.20...Gate electrode 7...Interlayer insulating film 8...Metal electrode wiring 9-Pch TFT active layer 1O-Nch
TFT active layer 14...Pch TFT contact hole 15...Nch TFT contact hole 16.
...Contact electrode 17...Transparent quartz glass 1
8-n-poly-5L active layer 23-PSG film 24
...Contact hole 25...ll electrode wiring 1
...Insulating substrate 3.13.22...Drain 2.12.21...Source 4.19...Gate insulating film

Claims (1)

[Claims] 1. In a semiconductor device composed of thin film transistors fabricated on an insulating substrate, the active layer forming the channel of each thin film transistor is n^-poly-Si,
And the contact hole area of the source and drain parts is N.
A semiconductor device characterized in that the channel transistor is smaller than the P-channel transistor, or the electrode material used for the source and drain contact portions is Al-2 to 3 wt% Si.