JPH02137272A - Cmos type thin film transistor - Google Patents
Cmos type thin film transistorInfo
- Publication number
- JPH02137272A JPH02137272A JP63290634A JP29063488A JPH02137272A JP H02137272 A JPH02137272 A JP H02137272A JP 63290634 A JP63290634 A JP 63290634A JP 29063488 A JP29063488 A JP 29063488A JP H02137272 A JPH02137272 A JP H02137272A
- Authority
- JP
- Japan
- Prior art keywords
- channel
- silicon nitride
- thickness
- active layer
- channel region
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims description 7
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 11
- 229910052698 phosphorus Inorganic materials 0.000 claims description 7
- 229910052757 nitrogen Inorganic materials 0.000 claims description 5
- 229910052581 Si3N4 Inorganic materials 0.000 abstract description 13
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract description 13
- 238000005530 etching Methods 0.000 abstract description 9
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052681 coesite Inorganic materials 0.000 abstract 3
- 229910052906 cristobalite Inorganic materials 0.000 abstract 3
- 239000000377 silicon dioxide Substances 0.000 abstract 3
- 235000012239 silicon dioxide Nutrition 0.000 abstract 3
- 229910052682 stishovite Inorganic materials 0.000 abstract 3
- 229910052905 tridymite Inorganic materials 0.000 abstract 3
- 230000001590 oxidative effect Effects 0.000 abstract 2
- 239000010410 layer Substances 0.000 description 26
- 239000010408 film Substances 0.000 description 10
- 238000000034 method Methods 0.000 description 7
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000007789 gas Substances 0.000 description 3
- 239000011521 glass Substances 0.000 description 3
- 239000012535 impurity Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 2
- 229910052785 arsenic Inorganic materials 0.000 description 2
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 2
- 229910052796 boron Inorganic materials 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000011574 phosphorus Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007772 electrode material Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 239000004973 liquid crystal related substance Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1222—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer
- H01L27/1233—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or crystalline structure of the active layer with different thicknesses of the active layer in different devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1296—Multistep manufacturing methods adapted to increase the uniformity of device parameters
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Crystallography & Structural Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明はラインセンサー、アクティブマトリックス型液
晶表示装置等の駆動に用いられるＣＭＯＳ型薄膜トラン
ジスターに関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a CMOS thin film transistor used for driving line sensors, active matrix liquid crystal display devices, and the like.
従来、ρｏＱｙ−Ｓｉを半導体材料としてデバイス化し
た場合１本来イントリンシック（真性）が望まれるチャ
ンネル領域がきわめて僅かではあるが、ｎライク（以下
ｎ−と表わす。）又はｐライク（以下ｐ−と表わす。）
になることが知られている。チャンネル領域がｎ−ｐｏ
（２ｙ−ｐｏｌｙ−Ｓｉからなる場合、Ｎチャンネルト
ランジスターにおいては、しきい値電圧を低い値にコン
トロールし難く、このため駆動周波数が低くなったり、
しきい値電圧以下のゲート電圧領域で、リーク電流（オ
フ電流）が多く流れる結果、消費電流が多くなるという
欠点があった。同様な欠点はチャンネル領域がｐ−ρｏ
ｆｆｙ−ｐｏｌｙ−ＳｉからなるＰチャンネルトランジ
スターでも起こる。なおしきい値電圧のコントロールに
は従来、チャンネル領域に不純物をドープする方法が行
なわれているが、このような方法では工程が複雑化し、
経済的ではない。Conventionally, when ρoQy-Si is used as a semiconductor material to form a device, the channel region which is originally desired to be intrinsic (intrinsic) is very small, but it is n-like (hereinafter referred to as n-) or p-like (hereinafter referred to as p-). )
It is known that Channel area is n-po
(When made of 2y-poly-Si, it is difficult to control the threshold voltage to a low value in an N-channel transistor, so the driving frequency becomes low,
A drawback is that a large amount of leakage current (off-state current) flows in the gate voltage region below the threshold voltage, resulting in increased current consumption. A similar drawback is that the channel region is p−ρo
This also occurs in P-channel transistors made of ffy-poly-Si. Conventionally, the threshold voltage has been controlled by doping the channel region with impurities, but this method complicates the process and
It's not economical.
従って以上のような欠点を有するＮチャンネルトランジ
スター及びＰチャンネルトランジスターを用いた従来の
ＣＭＯ８型ＴＰＴは特性バランスが悪く、また高価であ
った。Therefore, conventional CMO8 type TPTs using N-channel transistors and P-channel transistors, which have the above-mentioned drawbacks, have poor characteristic balance and are expensive.
本発明の目的は従来技術における以上のような欠点を除
去し、Ｐ、Ｎ各チャンネルＴＦＴＬこおけるしきい値電
圧のコントロールを容易にし、且つ駆動周波数を大巾に
向上すると共に、しきい値電圧以下のゲート電圧領域で
のオフ電流を低下せしめ、こうして消費電流も低下せし
めると共にチャンネルドープを不要にした、特性バラン
スが良好で安価なＣＭ ＯＳ型ＴＰＴを提供することで
ある。The purpose of the present invention is to eliminate the above-mentioned drawbacks in the prior art, facilitate control of the threshold voltage in each P and N channel TFTL, greatly improve the driving frequency, and improve the threshold voltage. It is an object of the present invention to provide an inexpensive CMOS type TPT with good characteristic balance, which reduces off-state current in the following gate voltage region, thereby reducing current consumption and eliminating the need for channel doping.
本発明のＣＭＯ８型ＴＰＴは、絶縁基板上にＰチャンネ
ルドープ及びＮチャンネルドープを有するＣＭＯ８型Ｔ
Ｐ Ｔ ニおイテ、Ｐ、Ｎ両チャンネルトランジスタ
ーの各チャンネルを形成する活性層がｎ−ｐｏ＋２ｙ−
３ｉ又はＰ−ｐｏｌｙ−ｐｏｌｙ−Ｓｉからなり、且つ
ｎ−ｐｏ１２ｙ−８ｉ活性層の場合はＮチャンネルトラ
ンジスター活性層のチャンネル領域の厚さをＰチャンネ
ルトランジスターのチャンネル領域よりも薄くし、また
ｐ−ｐｏｌｙ−ｐｏｌｙ−Ｓｉ活性層の場合はＮチャン
ネルトランジスター活性層のチャンネル領域の厚さをＰ
チャンネルトランジスターのチャンネル領域よりも厚く
したことを特徴とするものである。The CMO8 type TPT of the present invention is a CMO8 type TPT having P channel doping and N channel doping on an insulating substrate.
P T niote, the active layer forming each channel of both P and N channel transistors is n-po+2y-
3i or P-poly-poly-Si, and in the case of an n-po12y-8i active layer, the thickness of the channel region of the N-channel transistor active layer is made thinner than that of the P-channel transistor; - In the case of a poly-Si active layer, the thickness of the channel region of the N-channel transistor active layer is P
It is characterized by being thicker than the channel region of the channel transistor.
このように本発明のＣＭＯ８型ＴＰＴはＰ。In this way, the CMO8 type TPT of the present invention is P.
Ｎ両チャンネルトランジスターのチャンネル領域の厚さ
を不均一化することにより、特に従来の前記両チャンネ
ル領域の均一な厚さによる特性上のアンバランスを解消
したものである。By making the thickness of the channel region of the N double channel transistor non-uniform, the unbalance in characteristics caused by the conventional uniform thickness of both channel regions can be solved.
以下、本発明を図面に従って説明する。The present invention will be explained below with reference to the drawings.
第１図にＣＭＯ８型ＴＰＴのレイアウト、第２図に従来
の一般的なＣＭＯ８型ＴＰＴの断面構造、及び第３図に
ｐｏｆｌｙ−ｐｏｌｙ−Ｓｉ活性層がｎ−ｐｏ＋２ｙ−
３Ｌの場合の本発明の一例のＣＭＯ５型ＴＰＴの断面構
造を示す、第２図及び第３図の構造を比較すれば判るよ
うに従来品では、Ｐ、Ｎ両チャンネルトランジスターに
おけるｐｏ（２ｙ−ｐｏｌｙ−Ｓｉ活性層の厚さは均一
（同一）であるのに対し、本発明ではこれら両ｐｏｌｙ
−ｐｏｌｙ−Ｓｉ活性層の厚さはチャンネル領域５で異
なっている。即ち第３図の例（活性層はｎ−ｐｏｆｌｙ
−ｐｏｌｙ−Ｓｉからなる）の場合はＰ、Ｎ両チャンネ
ルトランジスターにおいて、ソース領域及びドレイン領
域３，４の厚さはいずれも均一であるが、チャンネル領
域５の厚さはＮチャンネルトランジスターの方がＰチャ
ンネルトランジスターよりも薄くなっている。なお活性
層がｐ−ｐｏｌｙ−ｐｏｌｙ−Ｓｉからなる場合はその
逆にチャンネル領域の厚さはＮチャンネルトランジスタ
ーの方をＰチャンネルトランジスターよりも厚くする。Figure 1 shows the layout of a CMO8 type TPT, Figure 2 shows the cross-sectional structure of a conventional general CMO8 type TPT, and Figure 3 shows a pofly-poly-Si active layer with n-po+2y-
As can be seen by comparing the structures of FIG. 2 and FIG. -While the thickness of the Si active layer is uniform (same), in the present invention both of these poly
- The thickness of the poly-Si active layer is different in the channel region 5. In other words, the example of FIG. 3 (the active layer is n-pofly
- In the case of P- and N-channel transistors (consisting of -poly-Si), the thickness of the source and drain regions 3 and 4 is uniform in both the P and N channel transistors, but the thickness of the channel region 5 is greater in the N channel transistor. It is thinner than a P-channel transistor. When the active layer is made of p-poly-poly-Si, conversely, the thickness of the channel region of the N-channel transistor is made thicker than that of the P-channel transistor.
次に以上のような本発明のＣＭＯ８型ＴＰＴの製造実施
例を第４図に従って説明する。Next, a manufacturing example of the CMO8 type TPT of the present invention as described above will be described with reference to FIG.
まず透明石英ガラス基板１上に例えばｎ−ｐｏｌｙ−ｐ
ｏｌｙ−Ｓｉを基板温度６３０℃で減圧ＣＶＤ法により
１３００人厚に堆積せしめ、引続きフォトリソグラフィ
ー・エツチングにより島状のｐｏ１２ｙ−３ｉ活性層２
を形成した後、全体に窒化シリコンをプラズマＣＶＤ法
により１０００人厚に堆積せしめ、引続きフォトリソグ
ラフィー・エツチングにより、−方の活性層２上のチャ
ンネル領域相当部分が欠けた窒化シリコン膜１０を形成
する（第４図（ａ））。First, on a transparent quartz glass substrate 1, for example, an n-poly-p
oly-Si was deposited to a thickness of 1300 nm by low-pressure CVD at a substrate temperature of 630°C, followed by photolithography and etching to form island-shaped po12y-3i active layers 2.
After forming silicon nitride, silicon nitride is deposited on the entire surface by plasma CVD to a thickness of 1000 nm, and then photolithography and etching are performed to form a silicon nitride film 10 in which a portion corresponding to the channel region on the - side active layer 2 is missing. (Figure 4(a)).
次にこの基板を１０５０℃の乾燥酸素中で熱酸化処理し
、窒化シリコン膜１０の前記欠落部に１４００人厚のＳ
ｉｎ２酸化層６′を形成する（第４図（ｂ））。Next, this substrate was subjected to thermal oxidation treatment in dry oxygen at 1050°C, and a 1400-layer thick S
An in2 oxide layer 6' is formed (FIG. 4(b)).
次に窒化シリコン膜ｌＯをＢＨＦ（ｆｉ衝弗酸水溶液）
でエツチング除去する。この時、ＳｉＯ□酸化層６′も
同時にエツチングされるが、窒化シリコン膜のエツチン
グ速度は４０人／５ｅｅ（２０°Ｃ）またｐｏｌｙ−Ｓ
ｉｎ２酸化層のエツチング速度は１０人／５ｅｅ（２０
℃）なので、窒化シリコン膜除去後も酸化層は一部残る
。この残存酸化層は以下に述べるチャンネル領域の厚さ
調整のために残してもよいが、引続き前記エツチング液
で完全に除去してもよい（第４図（Ｃ））。ここでチャ
ンネル領域の厚さ調整法として下記方法が挙げられる。Next, the silicon nitride film lO
Remove by etching. At this time, the SiO□ oxide layer 6' is also etched at the same time, but the etching rate of the silicon nitride film is 40 people/5ee (20°C) and the poly-S
The etching rate of the in2 oxide layer is 10 people/5ee (20
℃), so a portion of the oxide layer remains even after the silicon nitride film is removed. This residual oxide layer may be left for the purpose of adjusting the thickness of the channel region as described below, but it may also be completely removed using the etching solution (FIG. 4(C)). Here, the following method can be mentioned as a method for adjusting the thickness of the channel region.
（１）酸化膜の厚さを酸化時の処理時間及び処理温度に
より調整する。(1) The thickness of the oxide film is adjusted by the treatment time and temperature during oxidation.
（２）前記残存酸化層の厚さをエツチング時間で調整す
る。(2) Adjusting the thickness of the remaining oxide layer by adjusting the etching time.
次にこの基板を前記と同じ方法で熱酸化処理して８００
人厚Ｓ３ｉｎ２酸化膜を形成し、その上にｐｏｌｙ−５
Ｌを減圧ＣｖＤ法テ３０００人厚堆積積せしめた後、セ
ルファライン技術でゲート絶縁層６及びゲート電極７を
形成する。引続き硼素をＰチャンネルトランジスター領
域に、また燐又は砒素をＮチャンネルトランジスター領
域にイオン打ち込みにより拡散導入し、ソース領域３及
びドレイン領域４を形成する（第４図（ｄ））。この不
純物拡散はＰＳＧ（燐ガラス）又はＡｓ５Ｇ（砒素ガラ
ス）（以上はＮチャンネルトランジスター作製の場合）
、ＢＳＧ（硼素ガラス）（Ｐチャンネルトランジスター
作製の場合）等の膜による熱拡散で行ってもよい。Next, this substrate was thermally oxidized in the same manner as above to
Form a S3in2 oxide film with a thickness of 3.5 cm, and poly-5
After depositing L to a thickness of 3,000 layers using the low pressure CvD method, a gate insulating layer 6 and a gate electrode 7 are formed using the self-line technique. Subsequently, boron is diffused into the P-channel transistor region and phosphorus or arsenic is diffused into the N-channel transistor region by ion implantation to form a source region 3 and a drain region 4 (FIG. 4(d)). This impurity diffusion is performed in PSG (phosphorus glass) or As5G (arsenic glass) (the above is for N-channel transistor fabrication).
, BSG (boron glass) (in the case of manufacturing a P-channel transistor), or the like may be used for thermal diffusion using a film.
以下、この基板上に減圧ＣＶＤ法によりｐｏｌｙ−Ｓｉ
０２層間絶縁膜８を形成し、コンタクトホールを開け、
Ａ２、Ａｆ１合金等の電極材料の蒸着及びエツチングに
より電極配線９を形成すれば第３図のようなＣＭＯ３型
ＴＰＴが得られる（第４図（ｅ））。Hereinafter, poly-Si was deposited on this substrate by low pressure CVD method.
02 Form an interlayer insulating film 8, open a contact hole,
If the electrode wiring 9 is formed by vapor deposition and etching of an electrode material such as A2 or Af1 alloy, a CMO3 type TPT as shown in FIG. 3 can be obtained (FIG. 4(e)).
なお最後にこのＴＰＴに対し以下のような条件でプラズ
マ水素処理を行なう。Finally, this TPT is subjected to plasma hydrogen treatment under the following conditions.
Ｒｆ比出力 １．ＩＷ／ａｄ
ガス圧 １００ Ｐ ａ
ガス流量 １１００８ＣＣ
原料ガス Ｈ２
基板温度 ３００℃
時 間 ３０分
以上のようにして作製したＣＭＯ８型ＴＰＴでシフトレ
ジスターを構成したところ、最高駆動周波数は５ＭＨｚ
となり、−消費電流も減少した。なお第２図の従来品の
場合は最高駆動周波数は０．５ＭＨｚであった。Rf specific output 1. IW/ad Gas pressure 100 Pa Gas flow rate 11008 CC Source gas H2 Substrate temperature 300°C Time When a shift register was constructed using the CMO8 type TPT manufactured as described above for over 30 minutes, the maximum drive frequency was 5 MHz.
Therefore, the current consumption also decreased. In the case of the conventional product shown in FIG. 2, the maximum driving frequency was 0.5 MHz.
Ｎ又はＰチャンネルドープにおいて、チャンネル領域の
厚さを薄くして行くと、３００人厚ＳｒＰＴ特性が向上
する。第５図にＮチャンネルＴＰＴの場合のＶＩ特性を
示す。図中８曲線はチャンネル領域の厚さが約１０００
人の場合、５曲線は同じく約３００人の場合である。即
ちチャンネル領域活性層の薄層化により、しきい値電圧
をＯ付近の低い値にコントロールして駆動周波数を向上
すると共に、しきい値電圧以下のゲート電圧領域でのオ
フ電流を低下させ、こうして消費電流も少ない、Ｎチャ
ンネルトランジスターとＰチャンネルトランジスターと
のバランスが取れたＣＭＯ５型ＴＰＴをチャンネルドー
プすることなく安価に提供することができる。In N or P channel doping, when the thickness of the channel region is made thinner, the 300-layer thickness SrPT characteristics are improved. FIG. 5 shows VI characteristics in the case of N-channel TPT. In the 8th curve in the figure, the thickness of the channel region is approximately 1000 mm.
In the case of people, the 5th curve is also for about 300 people. That is, by thinning the active layer in the channel region, the threshold voltage can be controlled to a low value near O to improve the driving frequency, and the off-state current in the gate voltage region below the threshold voltage can be reduced. A CMO5 type TPT with low current consumption and a well-balanced N-channel transistor and P-channel transistor can be provided at low cost without channel doping.
第１図はＣＭＯＳ型ＴＰＴのレイアウト、第２図は従来
の一例ＣＭＯ８型ＴＰＴの断面図、第３図は本発明の一
例のＣＭＯ８型ＴＰＴの断面図、第４図（ａ）〜（ｅ）
は本発明の一例のＣＭＯ８型ＴＰＴの製造工程図、第５
図はＮチャンネルＴＰＴのＶＩ特性図である。
１・・・絶縁基板 ２・・・ｐｏ１２ｙ−３Ｌ活性層
３・・・ソース領域 ４・・・ドレイン領域５・・
・チャンネル領域 ６・・・ゲート絶縁層６′・・・Ｓ
ｉｏ２酸化層 ７・・・ゲート電極８・・・層間絶
縁膜 ９・・・電極配線１０・・・窒化シリコン膜
１１・・・不純物イオン特許出願人 株式会社 リ
コ −
市２図
帛３図
ＶＧ（Ｖｌ
帛４回Fig. 1 is a layout of a CMOS type TPT, Fig. 2 is a sectional view of a conventional CMO8 type TPT, Fig. 3 is a sectional view of a CMO8 type TPT as an example of the present invention, and Figs. 4 (a) to (e).
5 is a manufacturing process diagram of CMO8 type TPT as an example of the present invention.
The figure is a VI characteristic diagram of an N-channel TPT. 1... Insulating substrate 2... po12y-3L active layer 3... Source region 4... Drain region 5...
・Channel region 6...Gate insulating layer 6'...S
io2 oxide layer 7... Gate electrode 8... Interlayer insulating film 9... Electrode wiring 10... Silicon nitride film 11... Impurity ion patent applicant Li Co., Ltd.
Ko - City 2 Map 3 VG (Vl 4 times
Claims (1)
Ｎチャンネル薄膜トランジスターを有するＣＭＯＳ型薄
膜トランジスターにおいて、Ｐ、Ｎ両チャンネル薄膜ト
ランジスターの各チャンネルを形成する活性層がｎ＾−
ｐｏｌｙ−Ｓｉ活性層の場合はＮチャンネルトランジス
ター活性層のチャンネル領域の厚さをＰチャンネルトラ
ンジスターのチャンネル領域よりも薄くし、またｐ−ｐ
ｏｌｙ−Ｓｉ活性層の場合はＮチャンネルトランジスタ
ー活性層のチャンネル領域の厚さをＰチャンネルトラン
ジスターのチャンネル領域よりも厚くしたことを特徴と
するＣＭＯＳ型薄膜トランジスター。1. In a CMOS type thin film transistor having a P channel thin film transistor and an N channel thin film transistor on an insulating substrate, the active layer forming each channel of both P and N channel thin film transistors is n^-
In the case of a poly-Si active layer, the thickness of the channel region of the N-channel transistor active layer is made thinner than that of the P-channel transistor, and the thickness of the channel region of the N-channel transistor active layer is made thinner than that of the P-channel transistor.
A CMOS type thin film transistor characterized in that, in the case of an oly-Si active layer, a channel region of an N-channel transistor active layer is thicker than a channel region of a P-channel transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290634A JPH02137272A (en) | 1988-11-17 | 1988-11-17 | Cmos type thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63290634A JPH02137272A (en) | 1988-11-17 | 1988-11-17 | Cmos type thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02137272A true JPH02137272A (en) | 1990-05-25 |
Family
ID=17758515
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63290634A Pending JPH02137272A (en) | 1988-11-17 | 1988-11-17 | Cmos type thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02137272A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5281840A (en) * | 1991-03-28 | 1994-01-25 | Honeywell Inc. | High mobility integrated drivers for active matrix displays |
| US5308779A (en) * | 1991-03-28 | 1994-05-03 | Honeywell Inc. | Method of making high mobility integrated drivers for active matrix displays |
| US5528056A (en) * | 1990-11-30 | 1996-06-18 | Sharp Kabushiki Kaisha | CMOS thin-film transistor having split gate structure |
| JP2009278073A (en) * | 2008-04-18 | 2009-11-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and method for manufacturing the same |
-
1988
- 1988-11-17 JP JP63290634A patent/JPH02137272A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5528056A (en) * | 1990-11-30 | 1996-06-18 | Sharp Kabushiki Kaisha | CMOS thin-film transistor having split gate structure |
| US5281840A (en) * | 1991-03-28 | 1994-01-25 | Honeywell Inc. | High mobility integrated drivers for active matrix displays |
| US5308779A (en) * | 1991-03-28 | 1994-05-03 | Honeywell Inc. | Method of making high mobility integrated drivers for active matrix displays |
| JP2009278073A (en) * | 2008-04-18 | 2009-11-26 | Semiconductor Energy Lab Co Ltd | Semiconductor device, and method for manufacturing the same |
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