JPH0237814A - Delay element and it manufacture - Google Patents

Delay element and it manufacture

Info

Publication number
JPH0237814A
JPH0237814A JP63186928A JP18692888A JPH0237814A JP H0237814 A JPH0237814 A JP H0237814A JP 63186928 A JP63186928 A JP 63186928A JP 18692888 A JP18692888 A JP 18692888A JP H0237814 A JPH0237814 A JP H0237814A
Authority
JP
Japan
Prior art keywords
substrate
ground
pattern
delay line
delay element
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP63186928A
Other languages
Japanese (ja)
Other versions
JPH0530083B2 (en
Inventor
Taeko Ishizaka
石坂 妙子
Yoshihiko Kasai
河西 善彦
Hajime Okamura
岡村 一
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP63186928A priority Critical patent/JPH0237814A/en
Priority to US07/384,729 priority patent/US4949057A/en
Priority to CA000606798A priority patent/CA1314948C/en
Priority to EP89113975A priority patent/EP0352805B1/en
Priority to KR8910731A priority patent/KR920010601B1/en
Priority to DE68919008T priority patent/DE68919008T2/en
Publication of JPH0237814A publication Critical patent/JPH0237814A/en
Publication of JPH0530083B2 publication Critical patent/JPH0530083B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01PWAVEGUIDES; RESONATORS, LINES, OR OTHER DEVICES OF THE WAVEGUIDE TYPE
    • H01P9/00Delay lines of the waveguide type
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03HIMPEDANCE NETWORKS, e.g. RESONANT CIRCUITS; RESONATORS
    • H03H7/00Multiple-port networks comprising only passive electrical elements as network components
    • H03H7/30Time-delay networks
    • H03H7/34Time-delay networks with lumped and distributed reactance
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00

Abstract

PURPOSE:To attain miniaturization by facing ground patterns in the direction of exposing the ground pattern of a corner part opposite to the one whose base is excised, pasting them, connecting and fixing a ground terminal to the ground pattern of the part exposed in the excised part. CONSTITUTION:A first substrate 21 has a zigzag delay line pattern 26 on a surface 25 of a ceramic substrate main body 23 having a form that the right- lower corner part is excised like a circular arc (24 shows the excised part) from the rectangle of a length L3 and a width W3, and has a ground pattern 28 on the almost whole surface of a rear face 27. A second substrate 22 has the same structure as the first substrate 21, the second substrate is turned at 180 deg. and the rear faces 27 and 27a are pasted oppositely. Ground terminals 35 and 35a are connected and fixed to the parts of the ground patterns 28 and 28a. Thus, the connecting and fixing places of the ground terminals can be ensured, the length of the delay line patterns can be lengthened and the miniaturization can be attained.

Description

【発明の詳細な説明】 〔概要〕 遅延線パターンを有する基板を貼り合わせてなる分布定
数型の遅延素子及びその製造方法に関し、小型化を可能
とすることを目的とし、 底辺側の一の角部を切除された形状の基板本体と、この
表面の遅延線パターンと、この裏面のアースパターンと
よりなる第1の基板と、底辺側の一の角部を切除された
形状の基板本体と、この表面の遅延線パターンと、この
裏面の7−スバターンとよりなる第2の基板とが、各切
除部より他の基板のうち底辺の切除された側とは反対側
の角部のアースパターンが露出する向きで上記アースパ
ターン同志を突き合わせて貼り合わされ、且つアース端
子が上記切除部に露出している部分のアースパターンに
接続固定されて構成する。
[Detailed Description of the Invention] [Summary] The present invention relates to a distributed constant type delay element formed by bonding substrates having a delay line pattern and a method for manufacturing the same. A first substrate including a substrate body with a cut-off portion, a delay line pattern on the front surface, and a ground pattern on the back side; a substrate body with a corner portion on the bottom side cut off; A second board consisting of the delay line pattern on the front surface and the 7-strip pattern on the back surface is connected to the ground pattern at the corner of the other board opposite to the cut out side of the bottom side of the other board from each cutout part. The earth patterns are pasted together in an exposed direction, and the earth terminal is connected and fixed to the portion of the earth pattern exposed in the cutout.

〔産業上の利用分野〕[Industrial application field]

本発明は遅延線パターンを有する!8根を貼り合わせて
なる分布定数型の遅延素子及びその製造方法に関する。
The invention has a delay line pattern! The present invention relates to a distributed constant type delay element formed by bonding 8 roots together and a method for manufacturing the same.

ディジタル信号を用いた通信装置等において、信号間の
タイミング調整、部品やパターンで生ずる遅延&の調整
のために分布定数型「延素fが使用される。
In communication devices using digital signals, a distributed constant type "element f" is used to adjust timing between signals and to adjust delays caused by components and patterns.

得ようとする遅延時伺が例えば2ms以上である場合に
は、遅延線パターンを有する一枚の基板では足りず、遅
延素子は夫々遅延線パターンを有する二枚の基板を貼り
合わせた構成とされる。
If the desired delay time is, for example, 2 ms or more, one substrate having a delay line pattern is not sufficient, and the delay element is constructed by bonding two substrates each having a delay line pattern. Ru.

この遅延素子についても、他の電子部品と同様に小型化
が望まれている。
This delay element is also desired to be miniaturized like other electronic components.

〔従来の技術〕[Conventional technology]

第11図乃至第13図は夫々従来の分布定数型遅延素子
1を示す。
FIGS. 11 to 13 each show a conventional distributed constant type delay element 1. FIG.

この遅延素子1は、第14図に示す片面に遅延線パター
ン2.他面に仝面アースパターン3を右する第1の基板
4と、第15図に示す片面に遅延線パターン5.他面に
全面アー スパターン6を有する第2の基板7とをアー
ス面同志貼り合わせてなり、且つ遅延線パターン2.5
がストラップ8゜9により接続され、且つ入出力端子1
0.11及び一対のアース端子12.13が下方に延出
した構成である。
This delay element 1 has a delay line pattern 2 on one side as shown in FIG. A first substrate 4 having a ground pattern 3 on one side on the other side, and a delay line pattern 5 on one side as shown in FIG. A second substrate 7 having a full-surface ground pattern 6 on the other surface is bonded together on the ground planes, and has a delay line pattern 2.5.
is connected by strap 8゜9, and input/output terminal 1
0.11 and a pair of ground terminals 12 and 13 extend downward.

遅延時間は、遅延線パターン2と5との合計の長さによ
り定まる。
The delay time is determined by the total length of delay line patterns 2 and 5.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

第1の基板4は長さが1−1+幅がWlであり、第2の
基板7は長さが121幅がWlである。
The first substrate 4 has a length of 1-1+width Wl, and the second substrate 7 has a length of 121 and a width of Wl.

第2の基板7は、長さL2はL+と等しいが、幅W2は
、各端子10〜13の接続部を避けるように、Wlより
短くしている。
The length L2 of the second substrate 7 is equal to L+, but the width W2 is shorter than Wl so as to avoid the connecting portions of the terminals 10 to 13.

このため、第2の基板7の面積は狭く遅延線パターン5
の長さは長くできにくい。
Therefore, the area of the second substrate 7 is small and the delay line pattern 5
It is difficult to make the length long.

従って、遅延線パターン2と5との合計を所定の長さと
するためには、第2の基板7の幅W2が狭くなって遅延
線パターン5を長くできない分遅延線パターン2の長さ
を長くすべく、第1の基板4のサイズを大きくする必要
があり、これによって遅延素子1の小型化が妨げられて
いた。
Therefore, in order to make the total of delay line patterns 2 and 5 a predetermined length, the length of delay line pattern 2 must be increased by the amount that width W2 of second substrate 7 is narrowed and delay line pattern 5 cannot be made longer. In order to achieve this, it was necessary to increase the size of the first substrate 4, which hindered miniaturization of the delay element 1.

本発明は、小型化を可能とすることのできる遅延素子及
びその製造方法を提供することを目的とする。
An object of the present invention is to provide a delay element that can be miniaturized and a method for manufacturing the same.

〔課題を解決するための手段〕[Means to solve the problem]

本発明は、底辺側の一の角部を切除された形状の基板本
体と、この表面の遅延線パターンと、この裏面のアース
パターンとよりなる第1の基板と、底辺側の一の角部を
切除された形状の基板本体と、この表面の遅延線パター
ンと、この整面のアースパターンとよりなる第2の基板
とが、各切除部より他の基板のうち底辺の切除された側
とは反対側の角部のアースパターンが露出する向きで上
記アースパターン同志を突き合わせて貼り合わされ、且
つアース端子が上記切除部に露出している部分のアース
パターンに接続されて固定されてなる構成としたもので
あることを特徴とする。
The present invention provides a first substrate including a substrate main body having a shape in which one corner on the bottom side is cut off, a delay line pattern on the front surface of this substrate, and a ground pattern on the back side, and one corner on the bottom side. A second board consisting of a main board with a cutout shape, a delay line pattern on this surface, and a ground pattern with a flat surface is connected to the bottom cut side of the other board from each cutout part. has a configuration in which the ground patterns are butted together and pasted together in such a direction that the ground pattern at the opposite corner is exposed, and the ground terminal is connected and fixed to the ground pattern at the part exposed in the cutout. It is characterized by being

〔作用〕[Effect]

基板本体のうち角部は元々遅延線パターンが形成されな
い部分であり、基板本体をその底辺側の一の角部を切除
した形状としても、切除がない場合と実質上同じ長さの
遅延線パターンが形成される。 一対の基板の両方共こ
の基板であるため、遅延線パターンの合計の良さが長く
なる。
The corner of the board body is originally a part where a delay line pattern is not formed, so even if one corner of the base side of the board body is cut off, the delay line pattern will have substantially the same length as without the cutout. is formed. Since both of the pair of substrates are this substrate, the total quality of the delay line pattern becomes longer.

これにより、遅延時間が同じものが、従来に比べて小型
となる。
As a result, a device with the same delay time becomes smaller than the conventional device.

〔実施例〕〔Example〕

第1図乃至第3図は夫々本発明の第1実施例になる分布
定数型遅延素子20を示す。
1 to 3 each show a distributed constant type delay element 20 according to a first embodiment of the present invention.

遅延素子20は、第4図に示す第1の基板21と、第5
図に示す第2の基板22とが貼り合わされた構成である
The delay element 20 includes a first substrate 21 and a fifth substrate shown in FIG.
It has a structure in which the second substrate 22 shown in the figure is bonded together.

第1の基板21は、第4図に示すように、長さL3.幅
W3の矩形のうち右下の一の角部を円弧状に切除された
形状(24は切除部を示す)のセラミック基板本体23
の表面25にジグザグ状に遅延線パターン26を有し、
裏面27の略全面にアースパターン28を有する構成で
ある。
As shown in FIG. 4, the first substrate 21 has a length L3. A ceramic substrate main body 23 having a shape in which one lower right corner of a rectangle with a width W3 is cut out in an arc shape (24 indicates the cutout part).
has a zigzag delay line pattern 26 on the surface 25 of
This configuration has a ground pattern 28 on substantially the entire surface of the back surface 27.

遅延線パターン26の両端にはパッド29゜30を有す
る。パッド29は基板本体23の上辺31のうら基板本
体23の長さ方向上の中心線32と一致した部位に配し
である。別のパッド30は基板本体23の底辺33のう
ち中心線32より切除部24側に寸法e1偏倚した部位
に配しである。
The delay line pattern 26 has pads 29 and 30 at both ends. The pad 29 is arranged behind the upper side 31 of the substrate body 23 at a position that coincides with the center line 32 in the length direction of the substrate body 23. Another pad 30 is arranged at a portion of the bottom side 33 of the substrate body 23 that is deviated by a dimension e1 from the center line 32 toward the cutout portion 24 side.

34は入出力端子であり、パッド29と電気的に接続さ
せて、底辺33にこれより突出して固定しである。
Reference numeral 34 denotes an input/output terminal, which is electrically connected to the pad 29 and is fixed to protrude from the bottom side 33.

35はアース端子であり、底辺33のうち切除部24と
は反対側の部位に、アースパターン28と電気的に接続
させて、底辺33より突出して固定しである。
Reference numeral 35 denotes a ground terminal, which is electrically connected to the ground pattern 28 at a portion of the bottom side 33 opposite to the cutout portion 24, and is fixed so as to protrude from the bottom side 33.

第2の基板22は、第5図に示す構成であり、第4図に
示す第1の基板21と全く同一の構成である。対応する
部位には添字aを付した同一符号を示しその説明は省略
する。
The second substrate 22 has the configuration shown in FIG. 5, and has exactly the same configuration as the first substrate 21 shown in FIG. 4. Corresponding parts are denoted by the same reference numerals with the suffix a, and their explanations will be omitted.

セラミック基板本体23aはセラミック基板本体23と
同じサイズである。
The ceramic substrate body 23a has the same size as the ceramic substrate body 23.

上記構成の第1の基板21と第2の基板22とは、第5
図中矢印36で示すように第2の基板22を中心線32
aに関して180度回動させ、裏面27.27afii
志を背中合せにして貼り合せである。
The first substrate 21 and the second substrate 22 having the above configuration are the fifth substrate.
The second substrate 22 is aligned with the center line 32 as shown by the arrow 36 in the figure.
Rotate 180 degrees about a, back side 27.27afii
It is a combination of aspirations and aspirations.

アース端子35は、第3図に示すように、切除部24a
に露出しである。
The ground terminal 35 is connected to the cutout portion 24a as shown in FIG.
It is exposed to.

別のアース端子35aは、第1図に示すように、切除部
24に露出している。
Another ground terminal 35a is exposed in the cutout 24, as shown in FIG.

即ちアースパターン28.28aのうち切除部24.2
48とは反対側の角部の部分が夫々切除部24a、24
より露出しており、アース端子35.35aは夫々この
露出しているアースパターン部分に接続固定しである。
That is, the cutout portion 24.2 of the earth pattern 28.28a
The corner portions on the opposite side of 48 are cut out portions 24a, 24, respectively.
The ground terminals 35 and 35a are respectively connected and fixed to the exposed ground pattern portions.

入出力端子34.34aは中心線32.32aに関して
対称に位置している。
The input/output terminals 34.34a are located symmetrically with respect to the center line 32.32a.

パッド29と29aとは貼り合わせた基板21゜22の
両側の而の対応する部位にあり、両者間がストラップ3
6により配線しである。
The pads 29 and 29a are located at corresponding positions on both sides of the bonded substrates 21 and 22, and the strap 3 is placed between them.
6 is used for wiring.

入出力端子34と348との間には、遅延線パターン2
6.26aがストラップ37を介して接続されており、
遅延素子20は、遅延線パターン26と26aの合計の
長さに対応した遅延時間を有する。
A delay line pattern 2 is provided between the input/output terminals 34 and 348.
6.26a is connected via strap 37,
Delay element 20 has a delay time corresponding to the total length of delay line patterns 26 and 26a.

第4図に示すように、基板23は一の角部が切除しであ
るが、この切除部24は小ざく、基板23の表面25の
面積は切除部24が無いものと略同じであり、しかも元
々角部は遅延線パターンを形成しにくい場所である。
As shown in FIG. 4, one corner of the substrate 23 is cut away, but this cutout 24 is small, and the area of the surface 25 of the substrate 23 is approximately the same as that without the cutout 24. Furthermore, corners are places where it is difficult to form delay line patterns.

このため、遅延線パターン26の長さは、切除部24が
無い基板に形成されつる遅延線パターンの長さと略同じ
長さとなり、良い。
Therefore, the length of the delay line pattern 26 is approximately the same as the length of the vine delay line pattern formed on the substrate without the cutout portion 24, which is good.

第5図に示す基板23aは上記の基板23と同じ大きさ
及び形状であり、遅延線パターン26aも長さが長いも
のとなる。
The substrate 23a shown in FIG. 5 has the same size and shape as the substrate 23 described above, and the delay line pattern 26a is also longer.

この結果、遅延素子20は、切除部24.24aの無い
基板同志を貼り合わせた構造のものと略同じ遅延時間を
有する。
As a result, the delay element 20 has approximately the same delay time as a structure in which substrates without the cutout portions 24.24a are bonded together.

従って、所定の遅延時間を得るための長さの遅延線パタ
ーンを、従来のものより小さいサイズの遅延素子に形成
することが出来、遅延素子20は従来のものに比べて小
型となる。
Therefore, a delay line pattern having a length to obtain a predetermined delay time can be formed into a delay element smaller in size than the conventional one, and the delay element 20 becomes smaller than the conventional one.

また、上記構成の遅延素子20はサイズを従来のものと
同じとすると、「延時間が従来のものに比べて長くなる
Furthermore, assuming that the delay element 20 having the above configuration has the same size as the conventional one, the delay time will be longer than that of the conventional one.

また、基板21.22が夫々一の入出力端子34.34
aを有するため、遅延線パターン26゜26aの接続は
一個所で足り、遅延素子20は、従来の二四所のものに
比べて、組立作業性が良く且つ信頼性が高い。
In addition, each of the boards 21 and 22 has one input/output terminal 34 and 34.
a, the delay line pattern 26.degree. 26a only needs to be connected at one location, and the delay element 20 is easier to assemble and has higher reliability than the conventional delay element 20, which has 24 locations.

第6図は第1.第2の基板21.22の基板取りを説明
する図である。
Figure 6 is 1. It is a figure explaining the board|substrate removal of 2nd board|substrate 21.22.

第1.第2の基板セラミック元基板40に第6図に示す
ように合理的に基板取りされる。第6図中、第4図、第
5図に示す構成部分と同一部分には同一符号を示す。
1st. The substrate is rationally removed from the second substrate ceramic original substrate 40 as shown in FIG. In FIG. 6, the same components as those shown in FIGS. 4 and 5 are designated by the same reference numerals.

中央の円形孔41を中心に一の対角線方向に位置する一
対の基板のうち、一の基板42が第1の基板21を構成
し、別の基板43が第2の基板22を構成する。別の対
角線方向に位置する一対の基板のうち、一の基板44が
第1の基板21を構成し、別の基板45が第2の基板2
2を構成する。
Among a pair of substrates located in one diagonal direction around the central circular hole 41, one substrate 42 constitutes the first substrate 21, and another substrate 43 constitutes the second substrate 22. Among a pair of substrates located in another diagonal direction, one substrate 44 constitutes the first substrate 21, and another substrate 45 constitutes the second substrate 2.
2.

円形孔41が切除部24.24aを構成する。The circular hole 41 constitutes the cutout 24.24a.

第7図は本発明の第2実施例の分布定数型遅延素子50
を示す。
FIG. 7 shows a distributed constant delay element 50 according to a second embodiment of the present invention.
shows.

この遅延素子50は切除部51.51aが三角形状であ
る以外は、前記第1実施例の遅延素子20と同じ構成で
あり、第7図中、第1図に示ず構成部分と対応する部分
には同一符号を付し、ぞの説明は省略する。
This delay element 50 has the same structure as the delay element 20 of the first embodiment except that the cutout portion 51.51a is triangular, and in FIG. 7, the portion corresponding to the component not shown in FIG. are given the same reference numerals, and their explanation will be omitted.

遅延素子50は、第8図に示す第1の基板52の裏面に
、第9図に示す第2の基板53を矢印54で示すように
180度回動させて貼り合わせた構成である。
The delay element 50 has a structure in which a second substrate 53 shown in FIG. 9 is attached to the back surface of a first substrate 52 shown in FIG. 8 by rotating it by 180 degrees as shown by an arrow 54.

基板52.53は第10図に示すように基板取りされる
The substrates 52 and 53 are removed as shown in FIG.

基板55が第1の基板52を構成し、基板56が第2の
基板53を構成する。中心の菱形の孔57が上記の切除
部51.51aを形成する。
The substrate 55 constitutes the first substrate 52 and the substrate 56 constitutes the second substrate 53. The central diamond-shaped hole 57 forms the above-mentioned cutout 51.51a.

〔発明の効果〕〔Effect of the invention〕

以上説明した様に、本発明によれば、アース端子の接続
固定場所を確保し1ツると共に遅延線パターンの長さを
長くとることが出来、従って、同じ遅延時間特性のもの
を、従来のものに比べて小型に構成することが出来る。
As explained above, according to the present invention, it is possible to secure a fixed place for connecting the ground terminal, and to increase the length of the delay line pattern. It can be configured to be smaller than the conventional one.

また逆に+llスズ同じであれば、従来のものより遅延
時間を長くすることが出来る。
Conversely, if +ll tin is the same, the delay time can be made longer than the conventional one.

また、第1.第2の基板は同一の基板より基板取りされ
たものであるため、別々の基板より基板取りする場合に
比べて製造が簡単となり、製造コストが安価となる。
Also, 1st. Since the second board is cut from the same board, it is easier to manufacture and the manufacturing cost is lower than when the second board is cut from separate boards.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の第1実施例になる遅延素子の斜視図、 第2図は第1図の遅延素子の側面図、 第3図は第1図の遅延素子の裏側よりみた斜視図、 第4図は第1の基板の斜視図、 第5図は第2の基板の斜視図、 第6図は基板取りを説明する図、 第7図は本発明の第2実施例になる遅延素子の斜視図、 第8図は第1の基板の斜視図、 第9図は第2の基板の斜視図、 第10図は基板取りを説明する図、 第11図は従来の遅延素子の斜視図、 第12図は第11図の遅延素子の裏側よりみた斜視図、 第13図は第11図の遅延素子の側面図、第14図は第
1の基板の斜視図、 第15図は第2の基板の斜視図である。 図において、 20.50は分布定数型遅延素子、 21.52は第1の基板、 22.53は第2の基板、 23はセラミック基板本体、 24は切除部、 25は表面、 26は遅延線パターン、 27は裏面、 28はアースパターン、 29.30はパッド、 31は上辺、 32は中心線、 33は底辺、 34は入出力端子、 35はアース端子、 皿!P千徂収型影1子 @ 1 図 フn 37はストラップ、 40はセラミック元基板、 41は中心円形孔、 42〜45.55.56は基板、 5oは分布定数型遅延素子、 57は中心菱形孔 を示す。
FIG. 1 is a perspective view of a delay element according to a first embodiment of the present invention, FIG. 2 is a side view of the delay element of FIG. 1, and FIG. 3 is a perspective view of the delay element of FIG. 1 as seen from the back side. FIG. 4 is a perspective view of the first substrate, FIG. 5 is a perspective view of the second substrate, FIG. 6 is a diagram explaining how to remove the substrate, and FIG. 7 is a delay element according to a second embodiment of the present invention. FIG. 8 is a perspective view of the first substrate, FIG. 9 is a perspective view of the second substrate, FIG. 10 is a diagram explaining how to remove the substrate, and FIG. 11 is a perspective view of a conventional delay element. , FIG. 12 is a perspective view of the delay element shown in FIG. 11 seen from the back side, FIG. 13 is a side view of the delay element shown in FIG. 11, FIG. 14 is a perspective view of the first substrate, and FIG. 15 is a perspective view of the second substrate. FIG. In the figure, 20.50 is a distributed constant delay element, 21.52 is the first substrate, 22.53 is the second substrate, 23 is the ceramic substrate body, 24 is the cutout, 25 is the surface, and 26 is the delay line. Pattern, 27 is the back, 28 is the ground pattern, 29.30 is the pad, 31 is the top, 32 is the center line, 33 is the bottom, 34 is the input/output terminal, 35 is the ground terminal, plate! P 1,000 convergence type shadow 1 child @ 1 Figure n 37 is the strap, 40 is the ceramic original substrate, 41 is the center circular hole, 42 to 45, 55, 56 are the substrate, 5o is the distributed constant type delay element, 57 is the center Showing rhombic holes.

Claims (2)

【特許請求の範囲】[Claims] (1)底辺(33)側の一の角部を切除された形状の基
板本体(23)と、この表面(25)の遅延線パターン
(26)と、この裏面(27)のアースパターン(28
)とよりなる第1の基板(21)と、底辺(33a)側
の一の角部を切除された形状の基板本体(23a)と、
この表面(25a)の遅延線パターン(26a)と、こ
の裏面(27a)のアースパターン(28a)とよりな
る第2の基板(22)とが、各切除部(24,24a)
より他の基板のうち底辺の切除された側とは反対側の角
部のアースパターン(28a,28)が露出する向きで
上記アースパターン同志を突き合わせて貼り合わされ、
且つアース端子(35,35a)が上記切除部(24a
,24)に露出している部分のアースパターン(28,
28a)に接続されて固定されてなる構成としたことを
特徴とする遅延素子。
(1) A board body (23) with one corner cut off on the bottom side (33), a delay line pattern (26) on this front surface (25), and a ground pattern (28) on this back surface (27).
); a substrate main body (23a) having one corner cut off on the bottom side (33a);
A second substrate (22) consisting of a delay line pattern (26a) on the front surface (25a) and a ground pattern (28a) on the back surface (27a) is connected to each cutout portion (24, 24a).
The ground patterns (28a, 28) at the corner of the other board opposite to the side where the bottom side has been cut out are exposed, and the ground patterns are butted against each other and bonded together;
In addition, the ground terminal (35, 35a) is connected to the cutout part (24a).
, 24) of the exposed part of the earth pattern (28,
A delay element characterized in that it is connected to and fixed to 28a).
(2)底辺(33)側の一の角部を切除された形状の基
板本体(23)と、この表面(25)の遅延線パターン
(26)と、この裏面(27)のアースパターン(28
)とよりなる第1の基板(21)と、底辺(33a)側
の一の角部を切除された形状の基板本体(23a)と、
この表面(25a)の遅延線パターン(26a)と、こ
の裏面(27a)のアースパターン(28a)とよりな
る第2の基板(22)とを、同一の基板より夫々上記切
除部(24,24a)が相対向するようにして一の対角
線上の位置より基板取りし、 上記第1の基板(21)と第2の基板(22)とを、各
切除部(24,24a)より他の基板のうち底辺の切除
された側とは反対側の角部のアースパターン(28a,
28)が露出する向きで上記アースパターン同志を突き
合わせて貼り合わし、 アース端子(35,35a)を上記切除部 (24a,24)に露出している部分のアースパターン
(28,28a)に接続させて固定すことを特徴とする
遅延素子の製造方法。
(2) A board body (23) with one corner cut off on the bottom side (33), a delay line pattern (26) on this front surface (25), and a ground pattern (28) on this back surface (27).
); a substrate main body (23a) having one corner cut off on the bottom side (33a);
A second substrate (22) consisting of the delay line pattern (26a) on the front surface (25a) and the ground pattern (28a) on the back surface (27a) is cut out from the same substrate, respectively. ) are facing each other, the first substrate (21) and the second substrate (22) are removed from the other substrate from each cutout part (24, 24a). The ground pattern (28a,
28) are exposed, and the ground patterns are butted together and bonded together, and the ground terminals (35, 35a) are connected to the ground patterns (28, 28a) in the portions exposed in the cutout portions (24a, 24). 1. A method for manufacturing a delay element, characterized in that the delay element is fixed in place.
JP63186928A 1988-07-28 1988-07-28 Delay element and it manufacture Granted JPH0237814A (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
JP63186928A JPH0237814A (en) 1988-07-28 1988-07-28 Delay element and it manufacture
US07/384,729 US4949057A (en) 1988-07-28 1989-07-25 Distributed constant type delay line device and a manufacturing method thereof
CA000606798A CA1314948C (en) 1988-07-28 1989-07-27 Distributed constant type delay line device and a manufacturing method thereof
EP89113975A EP0352805B1 (en) 1988-07-28 1989-07-28 Distributed constant type delay line device and a manufacturing method thereof
KR8910731A KR920010601B1 (en) 1988-07-28 1989-07-28 Distributed constant type delay line device and a manufacturing method thereof
DE68919008T DE68919008T2 (en) 1988-07-28 1989-07-28 Delay line with distributed impedance elements and method for its production.

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63186928A JPH0237814A (en) 1988-07-28 1988-07-28 Delay element and it manufacture

Publications (2)

Publication Number Publication Date
JPH0237814A true JPH0237814A (en) 1990-02-07
JPH0530083B2 JPH0530083B2 (en) 1993-05-07

Family

ID=16197167

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63186928A Granted JPH0237814A (en) 1988-07-28 1988-07-28 Delay element and it manufacture

Country Status (6)

Country Link
US (1) US4949057A (en)
EP (1) EP0352805B1 (en)
JP (1) JPH0237814A (en)
KR (1) KR920010601B1 (en)
CA (1) CA1314948C (en)
DE (1) DE68919008T2 (en)

Families Citing this family (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0446405A (en) * 1990-06-13 1992-02-17 Murata Mfg Co Ltd Delay line and its manufacture
US5939966A (en) * 1994-06-02 1999-08-17 Ricoh Company, Ltd. Inductor, transformer, and manufacturing method thereof
JPH08288462A (en) * 1995-04-14 1996-11-01 Mitsubishi Electric Corp Semiconductor integrated circuit device
JPH09260912A (en) * 1996-03-26 1997-10-03 Murata Mfg Co Ltd Delay line
DE10348722B4 (en) * 2003-10-16 2013-02-07 Epcos Ag Electrical matching network with a transformation line
KR100723531B1 (en) * 2006-06-13 2007-05-30 삼성전자주식회사 Substrates for semiconductor package

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3670270A (en) * 1968-04-15 1972-06-13 Technitrol Inc Electrical component
JPS59202702A (en) * 1983-05-02 1984-11-16 Juichiro Ozawa Delay line element

Also Published As

Publication number Publication date
KR920010601B1 (en) 1992-12-10
EP0352805A2 (en) 1990-01-31
CA1314948C (en) 1993-03-23
EP0352805B1 (en) 1994-10-26
US4949057A (en) 1990-08-14
DE68919008D1 (en) 1994-12-01
DE68919008T2 (en) 1995-04-13
KR910003476A (en) 1991-02-27
JPH0530083B2 (en) 1993-05-07
EP0352805A3 (en) 1991-04-17

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