JPH02177386A - Electronic device - Google Patents

Electronic device

Info

Publication number
JPH02177386A
JPH02177386A JP33170488A JP33170488A JPH02177386A JP H02177386 A JPH02177386 A JP H02177386A JP 33170488 A JP33170488 A JP 33170488A JP 33170488 A JP33170488 A JP 33170488A JP H02177386 A JPH02177386 A JP H02177386A
Authority
JP
Japan
Prior art keywords
electronic devices
terminals
electronic device
devices
rough
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33170488A
Other languages
Japanese (ja)
Inventor
Toshio Suzuki
敏夫 鈴木
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP33170488A priority Critical patent/JPH02177386A/en
Publication of JPH02177386A publication Critical patent/JPH02177386A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/02Details
    • H05K1/14Structural association of two or more printed circuits
    • H05K1/142Arrangements of planar printed circuit boards in the same plane, e.g. auxiliary printed circuit insert mounted in a main printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/36Assembling printed circuits with other printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/40Forming printed elements for providing electric connections to or between printed circuits
    • H05K3/403Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof

Landscapes

  • Connections Arranged To Contact A Plurality Of Conductors (AREA)
  • Combinations Of Printed Boards (AREA)

Abstract

PURPOSE:To make possible the connection of electronic devices with other electronic device by a method wherein part of each surface of the substrates of the electronic devices is formed into a rough form and a plurality of signal terminals are arranged on the surfaces of the rough parts. CONSTITUTION:Part of each surface of substrates 1 and 2 of respective electronic devices is formed into a rough form and a plurality of input/output signal terminals 11 to 14 and 21 to 24 of a circuit or an element are respectively arranged on the surfaces of these rough parts. By this constitution, the fellow rough parts are fitted into one another, the devices can be connected with other electronic device and a reduction in the physical configuration of the electronic devices, an increase in the number of the signal terminals and an increase in the density of mounted electronic devices become possible without restricted by the effect of solder bridges and the like.

Description

【発明の詳細な説明】 [産業上の利用分野] 本発明は複数のデバイスを用い、各デバイス間を信号線
にて接続することにより所望の機能を実現するIC,L
SI等を含む電子デバイスに関し、特に、端子部を凹凸
形状になし、端子の対を直接結合する電子デバイスに関
する。
[Detailed Description of the Invention] [Industrial Application Field] The present invention is an IC, L, which realizes a desired function by using a plurality of devices and connecting each device with a signal line.
The present invention relates to electronic devices including SI and the like, and particularly relates to electronic devices in which terminal portions are formed into uneven shapes and pairs of terminals are directly coupled.

[従来の技術] 従来、複数の電子デバイスを接続する場合、信号線はプ
リント基板上に形成されたプリント配線及び線材等を用
いハンダ付けなどにより実現され、デバイスの配置、固
定等もプリント基板へのハンダ付けで兼用していた。ま
た、デバイスの外観形状も矩形でリード線が端子として
設けられているだけであった。すなわち、複数のデバイ
スを接続して所望の機能を実現する場合、従来は第5図
に示すように接続されるべき信号端子の対11−21.
12−22.13−23.14−24をプリント基板上
に形成されたプリント配線または線材でハンダ付けによ
り接続していた。
[Conventional technology] Conventionally, when connecting multiple electronic devices, signal lines are realized by soldering using printed wiring and wire materials formed on a printed circuit board, and the placement and fixing of devices is also done on the printed circuit board. It was also used for soldering. Further, the external shape of the device was also rectangular, and only lead wires were provided as terminals. That is, when connecting a plurality of devices to realize a desired function, conventionally, pairs of signal terminals 11-21 . to be connected are connected as shown in FIG.
12-22, 13-23, 14-24 were connected by soldering using printed wiring or wires formed on a printed circuit board.

[発明が解決しようとする問題点] 従来のデバイスでは、プリント基板及び線材に対するハ
ンダ付(すの行為によるハンダブリッジなどの影響のた
め各端子間距離が制限されていた。
[Problems to be Solved by the Invention] In conventional devices, the distance between each terminal is limited due to effects such as solder bridges caused by soldering to printed circuit boards and wires.

さらに信号線がデバイス間を縦横に配置されるため、信
号の伝搬遅延、雑音などによる機能品質への影響があっ
た。
Furthermore, since signal lines are arranged vertically and horizontally between devices, functional quality is affected by signal propagation delays, noise, etc.

[問題点を解決するための手段] 本発明は回路または素子が設けられた基体と、この回路
または素子の人力、出力用信号の複数の端子と、を有す
る電子デバイスにおいて、上記基体の一部表面を凹凸状
に形成し、これらの凹凸部分の表面に、上記複数の端子
をそれぞれ配設し、該凹凸部分同士を嵌合させることに
より他の電子デバイスと接続可能とした電子デバイスで
ある。
[Means for Solving the Problems] The present invention provides an electronic device having a base on which a circuit or an element is provided, and a plurality of terminals for human input and output signals of the circuit or element. The electronic device has an uneven surface, the plurality of terminals are arranged on the surface of these uneven parts, and the uneven parts are fitted to each other, thereby making it possible to connect to other electronic devices.

[実施例コ 第1図から第4図は本発明の一実施例を示す図面である
[Embodiment] FIGS. 1 to 4 are drawings showing an embodiment of the present invention.

本発明において、第1図、第2図に示すように対端子の
入力側と出力側それぞれ凹部と凸部に割り当て配置し直
接結合し、接続距離、デバイス配置間ll!最小で最良
条件て信号の伝搬が実現てきる。
In the present invention, as shown in FIGS. 1 and 2, the input and output sides of a pair of terminals are assigned to the concave portion and the convex portion, respectively, and are directly coupled, and the connection distance and device placement distance are 11! Signal propagation can be realized under the minimum and best conditions.

図において11〜14.21〜24は信号端子を、1,
2は各電子デバイスの基体を示している。
In the figure, 11-14.21-24 are signal terminals, 1,
2 indicates the base of each electronic device.

さらに、従来ハンダブリッジ等の影響で制約を受けてい
た隣接端子間隔も、第3図、第4図に示すように、従来
と同一距離L1を確保した場合においても平面距離L2
が短縮できる。ここでデバイスとは、IC,LSI、 
 抵抗、コンデンサ等の電子素子そのものでもまたそれ
らの複合素子でもよい。
Furthermore, as shown in Figs. 3 and 4, the spacing between adjacent terminals, which was conventionally limited by the influence of solder bridges, etc., is also reduced by the planar distance L2 even when the same distance L1 as before is secured.
can be shortened. Here, devices include IC, LSI,
It may be an electronic element itself such as a resistor or a capacitor, or a composite element thereof.

[発明の効果コ 以上説明したように、デバイスの端子部を凹凸形状にす
ることにより、ハンダブリッジ等の影響での制約を受け
ずデバイスの物理形状の縮小化、信号端子数の増加、デ
バイスの高搭載化が可能となり、機能品質の向上が実現
できる。
[Effects of the Invention] As explained above, by making the terminal portion of the device uneven, it is possible to reduce the physical shape of the device, increase the number of signal terminals, and increase the number of signal terminals without being restricted by the effects of solder bridges, etc. This makes it possible to increase the loading capacity and improve functional quality.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例を示す平面図、第2図は電子
デバイス同士を接続した状態を示す平面図、第3図は本
発明における凹凸形状の端子部の形状を示す斜視図、第
4図は各端子間の平面距離を説明する模式図、第5図は
従来例を示す平面図である。 1.2・・・・・・・・デバイス(基体)、If、  
12. 13. 14゜ 21.22,23,24・・・・信号端子、Ll・・・
・・・・・・・・・最小端子間距離、L2・・・・・・
・・・・・・平面端子間距離。
FIG. 1 is a plan view showing an embodiment of the present invention, FIG. 2 is a plan view showing a state in which electronic devices are connected to each other, and FIG. 3 is a perspective view showing the shape of the uneven terminal portion in the present invention. FIG. 4 is a schematic diagram illustrating the planar distance between each terminal, and FIG. 5 is a plan view showing a conventional example. 1.2... Device (substrate), If,
12. 13. 14゜21.22,23,24...Signal terminal, Ll...
・・・・・・・・・Minimum distance between terminals, L2・・・・・・
・・・・・・Distance between flat terminals.

Claims (1)

【特許請求の範囲】 回路または素子が設けられた基体と、この回路または素
子の入力,出力用信号の複数の端子と、を有する電子デ
バイスにおいて、 上記基体の一部表面を凹凸状に形成し、これらの凹凸部
分の表面に、上記複数の端子をそれぞれ配設し、該凹凸
部分同士を嵌合させることにより他の電子デバイスと接
続可能とした電子デバイス。
[Scope of Claims] An electronic device having a substrate provided with a circuit or an element, and a plurality of terminals for input and output signals of the circuit or element, wherein a part of the surface of the substrate is formed into an uneven shape. , an electronic device which can be connected to other electronic devices by disposing the plurality of terminals on the surfaces of these uneven portions and fitting the uneven portions together.
JP33170488A 1988-12-27 1988-12-27 Electronic device Pending JPH02177386A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33170488A JPH02177386A (en) 1988-12-27 1988-12-27 Electronic device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33170488A JPH02177386A (en) 1988-12-27 1988-12-27 Electronic device

Publications (1)

Publication Number Publication Date
JPH02177386A true JPH02177386A (en) 1990-07-10

Family

ID=18246655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33170488A Pending JPH02177386A (en) 1988-12-27 1988-12-27 Electronic device

Country Status (1)

Country Link
JP (1) JPH02177386A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1289351A1 (en) * 2001-08-29 2003-03-05 Gefran S.p.A. "Improved electronic board"
WO2003092343A1 (en) * 2002-04-25 2003-11-06 Nec Corporation Connection structure between printed boards

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1289351A1 (en) * 2001-08-29 2003-03-05 Gefran S.p.A. "Improved electronic board"
WO2003092343A1 (en) * 2002-04-25 2003-11-06 Nec Corporation Connection structure between printed boards

Similar Documents

Publication Publication Date Title
JPH02177386A (en) Electronic device
JPH06310827A (en) Surface mounting component arrangement structure
JPH0530083B2 (en)
JP2921708B2 (en) Electronic components for surface mounting
JPH02913Y2 (en)
JPS60160641A (en) Mounting of leadless package ic for board
JPH053402A (en) Hybrid integrated circuit device
JPH0439668Y2 (en)
JPH04105390A (en) Substrate mechanism
JPH0429585Y2 (en)
JPS6169159A (en) Integrated circuit device
JPH0745977Y2 (en) Board connection structure
JPH03184366A (en) Surface mount package
JPH0471260A (en) Electronic part
JPH0577870U (en) Cross tip
JPH075682Y2 (en) Dielectric device with terminal
JPH0648954Y2 (en) Electromagnetic filter composite parts
JPH04133451U (en) electronic components
JPH0685419A (en) Printed board
JPS63172450A (en) Wiring module
JPH01217869A (en) Hybrid integrated circuit device
JPS61189695A (en) Pattern structure for multi-layer printed circuit board
JPH02122694A (en) Double-sided printed circuit board for sop type smd
JPS63249362A (en) Package for surface-mounting parts
JPH0481112A (en) Method of packaging fixed delay line