JP3334816B2 - Semiconductor device and method of mounting semiconductor device - Google Patents
Semiconductor device and method of mounting semiconductor deviceInfo
- Publication number
- JP3334816B2 JP3334816B2 JP25003293A JP25003293A JP3334816B2 JP 3334816 B2 JP3334816 B2 JP 3334816B2 JP 25003293 A JP25003293 A JP 25003293A JP 25003293 A JP25003293 A JP 25003293A JP 3334816 B2 JP3334816 B2 JP 3334816B2
- Authority
- JP
- Japan
- Prior art keywords
- bonding
- chip
- flip
- semiconductor device
- mounting surface
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/14—Structure, shape, material or disposition of the bump connectors prior to the connecting process of a plurality of bump connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
Landscapes
- Wire Bonding (AREA)
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体装置及び半導体装
置の実装方法に関し、例えばフリツプチツプ型のICチツ
プ（以下これをICフリツプチツプと呼ぶ）及び当該ICフ
リツプチツプの実装方法に適用して好適なものである。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of mounting a semiconductor device, and more particularly to a flip-chip type IC chip (hereinafter referred to as an IC flip chip) and a method suitable for application to the mounting method of the IC flip chip. is there.
【０００２】[0002]
【従来の技術】従来図５及び図６に示すように、基板１
にICフリツプチツプ２を実装してなるICフリツプチツプ
実装基板３では、ICフリツプチツプ２の下側面（以下こ
れを実装面と呼ぶ）に複数設けられた各接合部２Ａと、
これと対応するように基板１の所定面にそれぞれ設けら
れた接合部１Ａとを例えばバンプ等でなる接合材４を用
いて接合することにより形成されている。この場合当該
ICフリツプチツプ２においては、図７に示すように、接
合部２Ａが実装面の各辺に沿つてそれぞれ並ぶように設
けられており、従つて実装面の周辺部において基板１と
接合される。2. Description of the Related Art Conventionally, as shown in FIGS.
In the IC flip-chip mounting substrate 3 having the IC flip-chip 2 mounted thereon, a plurality of joints 2A provided on a lower surface of the IC flip-chip 2 (hereinafter referred to as a mounting surface) are provided.
Correspondingly, it is formed by bonding the bonding portions 1A provided on the predetermined surface of the substrate 1 using a bonding material 4 made of, for example, a bump. In this case
In the IC flip-chip 2, as shown in FIG. 7, the joints 2A are provided so as to be arranged along each side of the mounting surface, and are thus joined to the substrate 1 at the periphery of the mounting surface.
【０００３】[0003]
【発明が解決しようとする課題】ところがこの種のICフ
リツプチツプ実装基板３においては、ICフリツプチツプ
２が接合材４を介して直接基板１上に接合されているた
めに、当該ICフリツプチツプ２と基板１との熱膨張率の
違いから温度変化等によつてICフリツプチツプ２、基板
１及び接合材４に応力や歪みが生じることがあり、この
結果ICフリツプチツプ２や接合材４が破壊することがあ
つた。この場合温度変化によつて任意の第１及び第２の
接合材４間に生じるICフリツプチツプ２の歪みの大きさ
は、当該第１の接合部材４が取り付けられた位置から当
該第２の接合材４が取り付けられた位置までの距離（以
下これを接合材間距離と呼ぶ）が長くなるほど大きくな
る。However, in this type of IC flip-chip mounting board 3, since the IC flip-chip 2 is directly bonded to the board 1 via the bonding material 4, the IC flip-chip 2 and the board 1 are not connected. Due to the difference in the coefficient of thermal expansion from the above, stress or distortion may occur in the IC flip chip 2, the substrate 1, and the bonding material 4 due to a temperature change or the like, and as a result, the IC flip chip 2 or the bonding material 4 may be broken. . In this case, the magnitude of the distortion of the IC flip-chip 2 generated between any of the first and second bonding materials 4 due to the temperature change is determined by the position of the first bonding member 4 attached to the second bonding material. It becomes larger as the distance to the position where 4 is attached (hereinafter referred to as the distance between bonding materials) becomes longer.
【０００４】従つてこの種のICフリツプチツプ２におい
ては、チツプ２が大きくなるほど各接合材間距離が大き
くなるためにICフリツプチツプ２に生じる歪みも大きく
なり、この結果チツプ２及び接合材４が壊れ易くなるこ
とにより温度変化に対する当該ICフリツプチツプ２の信
頼性が低下する問題があつた。Accordingly, in this type of IC flip chip 2, the larger the chip 2 is, the larger the distance between the joining materials is, so that the distortion generated in the IC flip chip 2 is also increased. As a result, the chip 2 and the joining material 4 are easily broken. As a result, there is a problem that the reliability of the IC flip-chip 2 with respect to a temperature change is reduced.
【０００５】本発明は以上の点を考慮してなされたもの
で、信頼性を向上させ得る半導体装置及びその半導体装
置の実装方法を提案しようとするものである。The present invention has been made in view of the above points, and has as its object to propose a semiconductor device capable of improving reliability and a method of mounting the semiconductor device.
【０００６】[0006]
【課題を解決するための手段】かかる課題を解決するた
め本発明においては、実装面にインプツト／アウトプツ
ト電極及びダミー電極でなる複数の第１の接合部がそれ
ぞれ設けられ、各第１の接合部を、それぞれ基板の所定
面に設けられた対応する第２の接合部に所定の接合手段
を用いて接合するようにして基板に実装する半導体装置
において、実装面の中央部から当該実装面の各対角線に
それぞれ沿うように、又は実装面の互いに対向する各辺
の中央部を結ぶように各第１の接合部を配置するように
した。According to the present invention, in order to solve the above-mentioned problems, a plurality of first joints each comprising an input / output electrode and a dummy electrode are provided on a mounting surface, and each of the first joints is provided. Are mounted on a substrate by bonding them to corresponding second bonding portions provided on a predetermined surface of the substrate using predetermined bonding means, respectively, from the center of the mounting surface to each of the mounting surfaces. Each of the first joints is arranged so as to be along a diagonal line or to connect the center of each side of the mounting surface facing each other.
【０００７】実装面にインプツト／アウトプツト電極及
びダミー電極でなる複数の第１の接合部がそれぞれ設け
られ、各第１の接合部を、それぞれ基板の所定面に設け
られた対応する第２の接合部に所定の接合手段を用いて
接合するようにして基板に実装する半導体装置の実装方
法において、半導体装置の実装面の中央部から当該実装
面の各対角線にそれぞれ沿うように、又は実装面の互い
に対向する各辺の中央部を結ぶように各第１の接合部を
配置し、半導体装置を、各第１の接合部をそれぞれ基板
の上記第２の接合部に接合手段を介して接合するように
して基板に実装するようにした。[0007] A plurality of first joints each comprising an input / output electrode and a dummy electrode are provided on the mounting surface, and each of the first joints is connected to a corresponding second joint provided on a predetermined surface of the substrate. In a method of mounting a semiconductor device to be mounted on a substrate so as to be bonded to a portion by using a predetermined bonding means, from a central portion of the mounting surface of the semiconductor device so as to respectively follow each diagonal line of the mounting surface, or The first bonding portions are arranged so as to connect the center portions of the sides facing each other, and the semiconductor device is bonded to the second bonding portions of the substrate via the bonding means, respectively, with the first bonding portions. In this way.
【０００８】さらに本発明においては、各第１の接合部
１１を、半導体チツプ１０の実装面の中央部から所定面
の各対角線に沿うようにそれぞれ配置した。Further, in the present invention, each of the first joints 11 is arranged from the center of the mounting surface of the semiconductor chip 10 along each diagonal line of the predetermined surface.
【０００９】さらに本発明においては、各第１の接合部
１１を、半導体装置２０の実装面の中央部から所定面の
各端辺にそれぞれ垂直な各直線に沿うようにそれぞれ配
置した。Further, in the present invention, the first joints 11 are arranged along respective straight lines perpendicular to the respective edges of the predetermined surface from the center of the mounting surface of the semiconductor device 20.
【００１０】[0010]
【作用】半導体装置１０、２０の実装面の中央部から当
該実装面の各対角線にそれぞれ沿うように、又は実装面
の互いに対向する各辺の中央部を結ぶように各第１の接
合部１１を配置するようにしたことにより、第１の接合
部１１間の距離を小さく抑えることができ、かくして温
度変化等に起因する当該半導体装置１０の歪みを抑制す
ることができる。The first joints 11 extend from the center of the mounting surfaces of the semiconductor devices 10 and 20 along the diagonals of the mounting surface, or connect the centers of the opposing sides of the mounting surface. Is arranged, the distance between the first bonding portions 11 can be reduced, and thus the distortion of the semiconductor device 10 due to a temperature change or the like can be suppressed.
【００１１】[0011]
【実施例】以下図面について、本発明の一実施例を詳述
する。BRIEF DESCRIPTION OF THE DRAWINGS FIG.
【００１２】図１において、１０は全体としてICフリツ
プチツプを示し、実装面に複数の電極及びダミー電極
（以下これらをまとめて単に電極１１と呼ぶ）が中心部
から各対角線にそれぞれ沿うように直線状にそれぞれ設
けられている。このため図２に示すように、当該ICフリ
ツプチツプ１０を実装する基板１２のパターン面上に
は、当該ICフリツプチツプ１０における各電極１１と同
様の配置に複数のランド１３がそれぞれ設けられてい
る。In FIG. 1, reference numeral 10 denotes an IC flip-chip as a whole, in which a plurality of electrodes and dummy electrodes (hereinafter collectively referred to simply as an electrode 11) are linearly formed on a mounting surface from the center to each diagonal line. , Respectively. Therefore, as shown in FIG. 2, on the pattern surface of the substrate 12 on which the IC flip-chip 10 is mounted, a plurality of lands 13 are provided in the same arrangement as the respective electrodes 11 of the IC flip-chip 10.
【００１３】これにより当該ICフリツプチツプ１０にお
いては、各電極１１をバンプ１４を介して当該基板１２
の対応するランドにそれぞれ接合することにより、基板
１２に実装するようになされている。As a result, in the IC flip-chip 10, each electrode 11 is connected to the substrate 12 via the bump 14.
Are mounted on the substrate 12 by bonding to the corresponding lands.
【００１４】以上の構成において、ICフリツプチツプ実
装基板では、任意の２つの接合材間に生じるICフリツプ
チツプ１０の歪みの大きさは接合材間距離に比例する。
この場合図５〜図７に示すような従来のICフリツプチツ
プ２では、図３及び図７からも明らかなように、接合材
間距離が最も長いのは同一の対角線上に位置する互いに
異なる隅部にそれぞれ配置された２つの接合材４Ａ及び
４Ｂ並びに４Ｃ及び４Ｄ間であり、従つて当該ICフリツ
プチツプ２を基板１上に実装した場合には当該２つの接
合材４Ａ及び４Ｂ並びに４Ｃ及び４Ｄ間のICフリツプチ
ツプ２に最も大きな歪みが生じる。In the above configuration, in the IC flip-chip mounting board, the magnitude of the distortion of the IC flip-chip 10 generated between any two bonding materials is proportional to the distance between the bonding materials.
In this case, in the conventional IC flip chip 2 as shown in FIGS. 5 to 7, as is clear from FIGS. 3 and 7, the distance between the joining materials is the longest at the different corners located on the same diagonal line. Between the two bonding materials 4A and 4B and 4C and 4D, respectively. Therefore, when the IC flip-chip 2 is mounted on the substrate 1, the two bonding materials 4A and 4B and 4C and 4D The largest distortion occurs in the IC flip chip 2.
【００１５】ところが実施例のICフリツプチツプ１０で
は、上述のように実装面の中心部に複数のバンプ４が配
置されているために、接合材間距離が最も長いものでも
上述の２つの接合材４Ａ及び４Ｂ並びに４Ｃ及び４Ｄ間
の接合材間距離に比べて十分に短く、従つて当該ICフリ
ツプチツプ１０を基板１２上に実装したときに温度変化
によつて発生する温度変化等に起因するICフリツプチツ
プ１０の歪みの大きさを従来のICフリツプチツプ２に比
べて実用上十分に軽減することができる。However, in the IC flip chip 10 of the embodiment, since the plurality of bumps 4 are arranged at the center of the mounting surface as described above, even if the distance between the bonding materials is the longest, the two bonding materials 4A are used. 4B, and 4C and 4C and 4D, which are sufficiently shorter than the distance between the bonding materials, and thus the IC flip-chip 10 caused by a temperature change or the like caused by a temperature change when the IC flip-chip 10 is mounted on the substrate 12. Can be sufficiently reduced in practical use as compared with the conventional IC flip-chip 2.
【００１６】以上の構成によれば、ICフリツプチツプ１
０の実装面に接合材としての複数のバンプ１４を各対角
線にそれぞれ沿うように順次配置したことにより、従来
のICフリツプチツプ２に比べて温度変化によるチツプの
歪みを抑制できる。従つて温度変化等に起因するICフリ
ツプチツプ１０及びバンプ１４等の損傷を防止でき、か
くしてICフリツプチツプの信頼性を向上させることがで
きる。According to the above configuration, the IC flip-chip 1
By arranging a plurality of bumps 14 as bonding materials on the mounting surface of No. 0 sequentially along each diagonal line, distortion of the chip due to temperature change can be suppressed as compared with the conventional IC flip chip 2. Therefore, damage to the IC flip-chip 10 and the bumps 14 due to a temperature change or the like can be prevented, and the reliability of the IC flip-chip can be improved.
【００１７】またこの場合、ICフリツプチツプ１０に形
成する電極１１の数を従来のICフリツプチツプ２に形成
する電極の数と同一にするものとすると、この実施例の
ICフリツプチツプ１０では隣接する電極１１間の距離を
長くすることができるために基板１２との接合に用いる
バンプ１４を大きくすることができる。従つて各バンプ
１４が破壊し難くなることにより、当該ICフリツプチツ
プ１０の信頼性をさらに向上させることができる。In this case, assuming that the number of electrodes 11 formed on the IC flip-chip 10 is the same as the number of electrodes formed on the conventional IC flip-chip 2,
Since the distance between the adjacent electrodes 11 can be increased in the IC flip chip 10, the bump 14 used for bonding to the substrate 12 can be increased. Accordingly, since the bumps 14 are hardly broken, the reliability of the IC flip-chip 10 can be further improved.
【００１８】さらに当該ICフリツプチツプ１０において
は、電極１１間のピツチを従来のICフリツプチツプ２の
電極１１間のピツチと同一にするものとすると、従来の
ICフリツプチツプ２に形成できるインプツト／アウトプ
ツト電極数よりも多くのインプツト／アウトプツト電極
を形成することができ、かくしてICフリツプチツプの信
頼性を向上させることができる。Further, in the IC flip chip 10, if the pitch between the electrodes 11 is made the same as the pitch between the electrodes 11 of the conventional IC flip chip 2,
More input / output electrodes than the number of input / output electrodes that can be formed on the IC flip-chip 2 can be formed, and thus the reliability of the IC flip-chip can be improved.
【００１９】なお上述の実施例においては、ICフリツプ
チツプ１０の電極１１を図１に示すように各対角線にそ
れぞれ沿うように順次形成するようにした場合について
述べたが、本発明はこれに限らず、例えば図４に示すよ
うに、ICフリツプチツプ２０の実装面の互いに対向する
各辺の中央部を結ぶように電極１１を順次形成するよう
にしても良く、要は、ICフリツプチツプ１０の実装面に
バンプ１４間の距離が大きくならないように電極１１を
形成するのであれば、電極１１の配置パターンとしては
この他種々のパターンを適用できる。In the above-described embodiment, the case has been described where the electrodes 11 of the IC flip chip 10 are sequentially formed along each diagonal line as shown in FIG. 1, but the present invention is not limited to this. For example, as shown in FIG. 4, the electrodes 11 may be sequentially formed so as to connect the center portions of the sides of the mounting surface of the IC flip chip 20 facing each other. In short, the electrodes 11 may be formed on the mounting surface of the IC flip chip 10. If the electrodes 11 are formed so that the distance between the bumps 14 does not increase, various other patterns can be applied as the arrangement pattern of the electrodes 11.
【００２０】また上述の実施例においては、ICフリツプ
チツプ１０の実装面に当該ICフリツプチツプ１０と基板
１２とを接合する手段（接合材）としてのバンプ１４を
各対角線にそれぞれ沿うように形成するようにした場合
について述べたが、本発明はこれに限らず、バンプ１４
とバンプ１４以外の他の接合材とを合わせて全体として
ICフリツプチツプ１０の実装面に図１のようなパンプの
配置パターンを形成するようにしても良い。In the above-described embodiment, the bumps 14 as means (joining material) for joining the IC flip-chip 10 and the substrate 12 are formed on the mounting surface of the IC flip-chip 10 along the respective diagonal lines. However, the present invention is not limited to this, and the bump 14
And other bonding materials other than the bumps 14 as a whole
A pump arrangement pattern as shown in FIG. 1 may be formed on the mounting surface of the IC flip chip 10.
【００２１】この場合当該バンプ１４以外の他の接合材
は、ICフリツプチツプ１０の電極１１と基板１２のラン
ド１３間以外の所において当該ICフリツプチツプ１０及
び基板１２を接合するものであつても良い。In this case, the bonding material other than the bump 14 may be a material for bonding the IC flip chip 10 and the substrate 12 at a place other than between the electrode 11 of the IC flip chip 10 and the land 13 of the substrate 12.
【００２２】[0022]
【発明の効果】上述のように本発明によれば、実装面に
インプツト／アウトプツト電極及びダミー電極でなる複
数の第１の接合部がそれぞれ設けられ、各第１の接合部
を、それぞれ基板の所定面に設けられた対応する第２の
接合部に所定の接合手段を用いて接合するようにして基
板に実装する半導体装置及びその実装方法において、半
導体装置の実装面の中央部から当該実装面の各対角線に
それぞれ沿うように、又は実装面の互いに対向する各辺
の中央部を結ぶように各第１の接合部を配置するように
したことにより、温度変化等に起因する当該半導体装置
の歪みを抑制することができ、かくして信頼性を向上さ
せ得る半導体装置及び半導体装置の実装方法を実現でき
る。As described above, according to the present invention, a plurality of first joints each comprising an input / output electrode and a dummy electrode are provided on the mounting surface, and each first joint is connected to the substrate. In a semiconductor device to be mounted on a substrate so as to be bonded to a corresponding second bonding portion provided on a predetermined surface by using predetermined bonding means, and a mounting method thereof, a mounting surface of the semiconductor device is moved from a center portion of the mounting surface to the mounting surface Are arranged along each diagonal of the semiconductor device, or so as to connect the central portions of the opposite sides of the mounting surface. It is possible to realize a semiconductor device and a semiconductor device mounting method capable of suppressing distortion and thus improving reliability.
【図１】実施例のICフリツプチツプにおける電極の形成
パターンを示す平面図である。FIG. 1 is a plan view showing an electrode formation pattern in an IC flip chip of an embodiment.
【図２】図１に示すICフリツプチツプを実装する基板の
ランドパターンを示す平面図である。FIG. 2 is a plan view showing a land pattern of a substrate on which the IC flip chip shown in FIG. 1 is mounted.
【図３】接合材間距離の説明に供する平面図である。FIG. 3 is a plan view for explaining a distance between bonding materials.
【図４】他の実施例を示す平面図である。FIG. 4 is a plan view showing another embodiment.
【図５】従来のICフリツプチツプを基板に実装した様子
を示す斜視図である。FIG. 5 is a perspective view showing a state in which a conventional IC flip chip is mounted on a substrate.
【図６】接合材を用いてICフリツプチツプ及び基板を接
合したときの様子を示す側面図である。FIG. 6 is a side view showing a state in which an IC flip chip and a substrate are joined using a joining material.
【図７】従来のICフリツプチツプに形成された接合部の
形成パターンを示す平面図である。FIG. 7 is a plan view showing a formation pattern of a joint formed on a conventional IC flip chip.
１、１２……基板、１Ａ、２Ａ……接合部、２、１０、
２０……ICフリツプチツプ、３……ICフリツプチツプ実
装基板、４、４Ａ〜４Ｄ……接合材、１１……電極、１
３……ランド、１４……バンプ。1, 12 ... board, 1A, 2A ... joint, 2, 10,
20 ... IC flip chip, 3 ... IC flip chip mounting board, 4, 4A-4D ... joining material, 11 ... electrode, 1
3 ... land, 14 ... bump.
───────────────────────────────────────────────────── フロントページの続き (56)参考文献 特開 昭62−281343（ＪＰ，Ａ) 特開 平５−218042（ＪＰ，Ａ) 特開 平２−164045（ＪＰ，Ａ) 特開 平１−238148（ＪＰ，Ａ) 特開 昭64−67951（ＪＰ，Ａ) 特開 昭63−233545（ＪＰ，Ａ) 特開 昭56−96631（ＪＰ，Ａ) (58)調査した分野(Int.Cl.7，ＤＢ名) H01L 21/60 311 ──────────────────────────────────────────────────続 き Continuation of front page (56) References JP-A-62-281343 (JP, A) JP-A-5-218042 (JP, A) JP-A-2-164045 (JP, A) JP-A-1- 238148 (JP, A) JP-A-64-67951 (JP, A) JP-A-63-233545 (JP, A) JP-A-56-96631 (JP, A) (58) Fields investigated (Int. 7 , DB name) H01L 21/60 311
Claims (2)
びダミー電極でなる複数の第１の接合部がそれぞれ設け
られ、各第１の接合部を、それぞれ基板の所定面に設け
られた対応する第２の接合部に所定の接合手段を用いて
接合するようにして上記基板に実装する半導体装置にお
いて、上記実装面の中央部から当該実装面の各対角線にそれぞ
れ沿うように、又は上記実装面の互いに対向する各辺の
中央部を結ぶように各上記第１の接合部が配置された こ
とを特徴とする半導体装置。An input / output electrode and an input / output electrode are provided on a mounting surface.
And a plurality of first bonding portions each including a dummy electrode are provided, and each of the first bonding portions is bonded to a corresponding second bonding portion provided on a predetermined surface of the substrate by using predetermined bonding means. In the semiconductor device to be mounted on the substrate as described above , each diagonal line of the mounting surface from the center of the mounting surface
Along each other or on each side of the mounting surface
A semiconductor device , wherein each of the first bonding portions is arranged so as to connect a central portion .
びダミー電極でなる複数の第１の接合部がそれぞれ設け
られ、各第１の接合部を、それぞれ基板の所定面に設け
られた対応する第２の接合部に所定の接合手段を用いて
接合するようにして上記基板に実装する半導体装置の実
装方法において、上記半導体装置の上記実装面の中央部から当該実装面の
各対角線にそれぞれ沿うように、又は上記実装面の互い
に対向する各辺の中央部を結ぶように各上記第１の接合
部を配置し、 上記半導体装置を、 各上記第１の接合部をそれぞれ上記
基板の上記第２の接合部に上記接合手段を介して接合す
るようにして上記基板に実装することを特徴とする半導
体装置の実装方法。2. The mounting surfaceInput / output electrodes and
And dummy electrodesA plurality of first joints respectively provided
And each of the first joints is provided on a predetermined surface of the substrate.
Using predetermined bonding means to the corresponding second bonding portion
Realization of semiconductor device mounted on the above substrate by bonding
In the mounting method,From the center of the mounting surface of the semiconductor device to the mounting surface
Along each diagonal or each of the mounting surfaces
Each of the first joints so as to connect the central portions of the sides facing each other.
Place the department, The above semiconductor device, Each of the first joints is
Bonding to the second bonding portion of the substrate via the bonding means;
ToIn the above wayCharacterized by the fact that
How to mount the body device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25003293A JP3334816B2 (en) | 1993-09-10 | 1993-09-10 | Semiconductor device and method of mounting semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25003293A JP3334816B2 (en) | 1993-09-10 | 1993-09-10 | Semiconductor device and method of mounting semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0786330A JPH0786330A (en) | 1995-03-31 |
| JP3334816B2 true JP3334816B2 (en) | 2002-10-15 |
Family
ID=17201821
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25003293A Expired - Fee Related JP3334816B2 (en) | 1993-09-10 | 1993-09-10 | Semiconductor device and method of mounting semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3334816B2 (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101051013B1 (en) | 2003-12-16 | 2011-07-21 | 삼성전자주식회사 | Driving chip and display device having same |
| JP3925503B2 (en) | 2004-03-15 | 2007-06-06 | カシオ計算機株式会社 | Semiconductor device |
-
1993
- 1993-09-10 JP JP25003293A patent/JP3334816B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0786330A (en) | 1995-03-31 |
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