JP2541005B2 - Semiconductor element mounting structure - Google Patents
Semiconductor element mounting structureInfo
- Publication number
- JP2541005B2 JP2541005B2 JP2264132A JP26413290A JP2541005B2 JP 2541005 B2 JP2541005 B2 JP 2541005B2 JP 2264132 A JP2264132 A JP 2264132A JP 26413290 A JP26413290 A JP 26413290A JP 2541005 B2 JP2541005 B2 JP 2541005B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- semiconductor element
- view
- substrate
- showing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Landscapes
- Wire Bonding (AREA)
Description
【発明の詳細な説明】 ［産業上の利用分野］ 本発明は、テープ・オートメイテッド・ボンディング
（Tape Automated Bonding:以下、TABと記す）方式によ
る半導体素子（以下、ICと記す）の実装構造に関する。The present invention relates to a mounting structure of a semiconductor element (hereinafter, referred to as IC) by a tape automated bonding (hereinafter, referred to as TAB) method. .
［従来の技術］ 第６図，第７図は従来の半導体素子の実装構造を得る
ための実装方法の一工程を示す断面模式図，斜視図、第
８図は第６図のＣ部の拡大断面を示す模式図、第９図は
従来例の他の工程を示す斜視図、第10図は第９図のＤ部
を拡大して示す正面図である。[Prior Art] FIGS. 6 and 7 are schematic cross-sectional views showing a step of a mounting method for obtaining a conventional semiconductor element mounting structure, a perspective view, and FIG. 8 is an enlarged view of a portion C in FIG. FIG. 9 is a schematic view showing a cross section, FIG. 9 is a perspective view showing another step of the conventional example, and FIG. 10 is an enlarged front view showing a portion D of FIG.
従来の半導体素子の実装方法では、第７図に示すよう
に、片面よりエッチングして作られるために台形状にな
る接続用リード２を持ったTABテープ１をIC4の接続用端
子３に対して、台形の広い辺を位置合せして、インナー
・リード・ボンディング（Inner Lead Bonding:以下、I
LBと記す）行なっていた。したがって接続部の断面は第
８図のようになっていた。In the conventional method of mounting a semiconductor element, as shown in FIG. 7, a TAB tape 1 having a trapezoidal connecting lead 2 formed by etching from one side is connected to a connecting terminal 3 of an IC4. , Align the wide sides of the trapezoid, and use Inner Lead Bonding:
LB). Therefore, the cross section of the connecting portion was as shown in FIG.
［発明が解決しようとする課題］ 上述した従来のTAB・ICはICの接続用端子に対して第
８図のように台形状の接続用リードの広い辺を位置合せ
を行ない、ILBする構造であるため、第９図のようにIC
を反転して、フェースダウンにし、基板５に接続すると
き、基板５のパッド６に対して、台形状の接続用リード
２の狭い辺を位置合せを行ない接続される構造となって
いた。この構造では、第10図のように、リード幅やピッ
チが狭い場合には、接続時にリードに振動や荷重をかけ
ると接続用リード２が傾いたり、倒れたりして、隣接す
るリードや、基板５のパッド６とショートを起こすとい
う欠点や、接続が完全に行えないなどの欠点があった。[Problems to be Solved by the Invention] The conventional TAB / IC described above has a structure in which the wide side of the trapezoidal connecting lead is aligned with the connecting terminal of the IC as shown in FIG. 8 to perform ILB. Therefore, as shown in Fig. 9, IC
When it is connected to the substrate 5 by reversing it and making it face down, the narrow side of the trapezoidal connecting lead 2 is aligned and connected to the pad 6 of the substrate 5. In this structure, as shown in FIG. 10, when the lead width and pitch are narrow, the connecting lead 2 tilts or falls when vibration or a load is applied to the lead at the time of connection, and the adjacent lead or substrate There were shortcomings such as short-circuiting with the pad 6 of No. 5 and that the connection could not be made completely.
［課題を解決するための手段］ 本発明の半導体素子の実装構造は、テープ・オートメ
イテッド・ボンディングテープの片面よりエッチングし
て作られた断面形状が台形の接続用リードのその台形の
狭い辺をなす面が半導体素子の接続用端子にインナー・
リード・ボンディングされ、前記接続用リードの前記台
形の広い辺をなす面が基板のパッドにボンディングされ
たことを特徴とする。[Means for Solving the Problems] The semiconductor element mounting structure of the present invention has a trapezoidal narrow side of a trapezoidal connecting lead formed by etching from one side of a tape automated bonding tape. The surface to be formed is the inner terminal for connecting the semiconductor element.
It is characterized in that it is lead-bonded, and the surface of the connecting lead forming the wide side of the trapezoid is bonded to the pad of the substrate.
［実施例］ 次に本発明について図面を参照して説明する。Example Next, the present invention will be described with reference to the drawings.
第１図，第２図は本発明の半導体素子の実装構造を得
るための実装方法の一工程を示す断面模式図，斜視図、
第３図は第１図のＡ部の拡大断面を示す４図は同実施例
の他の工程を示す斜視図、第５図は第４図のＢ部を拡大
して示ある。1 and 2 are schematic cross-sectional views, perspective views, showing one step of a mounting method for obtaining a mounting structure of a semiconductor device of the present invention.
3 is an enlarged cross-sectional view of part A of FIG. 1, FIG. 4 is a perspective view showing another step of the same embodiment, and FIG. 5 is an enlarged view of part B of FIG.
接続用リード２は、IC4の接続用端子３に位置合せを
行ない、ILBされる。The connection lead 2 is aligned with the connection terminal 3 of the IC 4 and is ILB.
第３図に示すように、接続用リード２は、ICの接続用
端子と辺の狭い方で位置合せされ、ILBされる。As shown in FIG. 3, the connection lead 2 is aligned with the connection terminal of the IC at the side with the narrower side, and ILB is performed.
第４図に示すように、TAB・ICを反転し、フェースダ
ウン状態で基板５に接続する。As shown in FIG. 4, the TAB / IC is inverted and connected to the substrate 5 in a face-down state.
第５図に示すように、接続用リード２は底辺の広い方
を基板５のパッド６に合うように位置合せされILBされ
る。As shown in FIG. 5, the connecting lead 2 is aligned and ILB so that the wider bottom side thereof is aligned with the pad 6 of the substrate 5.
［発明の効果］ 以上説明したように本発明は、TABテープの台形状を
した接続用リードの狭い辺をICの接続用端子に位置合せ
を行ないILBすることにより、TAB・ICを反転し、フェー
スダウンにして基板に実装する場合、接続用リードの広
い辺を基板のパッドに位置合せして接続することが可能
であるので、接続時に、振動や荷重をかけても、リード
が倒れたり、傾いたりせず、隣接するリードや、基板の
パッドとショートを起こさないという効果を奏する。ま
た、ICの接続用端子の接続用リードの狭い辺を位置合せ
を行ない、接続用端子に接続用リードをくさびを打ち込
むように接続しているため、ILB部の接続強度が強いと
いう効果も本発明は奏する。[Effects of the Invention] As described above, the present invention reverses the TAB / IC by aligning the narrow side of the trapezoidal-shaped connecting lead of the TAB tape with the connecting terminal of the IC and performing ILB, When mounting on the substrate with the face down, it is possible to align and connect the wide side of the connecting lead to the pad of the substrate, so even if vibration or load is applied at the time of connection, the lead will fall, It has the effect of not tilting and causing no short circuit with adjacent leads or pads on the substrate. In addition, the narrow side of the connecting lead of the connecting terminal of the IC is aligned, and the connecting lead is connected to the connecting terminal so that a wedge is driven in.Therefore, the connection strength of the ILB part is strong. The invention plays.
第１図，第２図は本発明の一実施例を得るための実装方
法の一工程を示す断面模式図，斜視図、第３図は第１図
のＡ部の拡大断面を示す模試図、第４図は同実施例の他
の工程を示す斜視図、第５図は第４図のＢ部を拡大して
示す正面図、第６図，第７図は従来例の一工程を示す断
面模式図，斜視図、第８図は第６図のＣ部の拡大断面を
示す模式図、第９図は従来例の他の工程を示す斜視図、
第10図は第９図のＤ部を拡大して示す正面図である。 １……TABテープ、２……接続用リード、３……接続用
端子、４……IC、５……基板、６……パッド。1 and 2 are schematic sectional views and perspective views showing one step of a mounting method for obtaining an embodiment of the present invention, and FIG. 3 is a schematic diagram showing an enlarged cross section of a portion A of FIG. FIG. 4 is a perspective view showing another step of the same embodiment, FIG. 5 is a front view showing an enlarged part B of FIG. 4, and FIGS. 6 and 7 are cross-sectional views showing one step of the conventional example. Schematic view, perspective view, FIG. 8 is a schematic view showing an enlarged cross-section of the C portion of FIG. 6, FIG. 9 is a perspective view showing other steps of the conventional example,
FIG. 10 is a front view showing an enlarged part D of FIG. 1 ... TAB tape, 2 ... connection lead, 3 ... connection terminal, 4 ... IC, 5 ... substrate, 6 ... pad.
Claims (1)
の片面よりエッチングして作られた断面形状が台形の接
続用リードのその台形の狭い辺をなす面が半導体素子の
接続用端子にインナー・リード・ボンディングされ、前
記接続用リードの前記台形の広い辺をなす面が基板のパ
ッドにボンディングされたことを特徴とすることを特徴
とする半導体素子の接続構造。1. A connecting lead having a trapezoidal cross section formed by etching from one side of a tape automated bonding, the surface forming the narrow side of the trapezoid being an inner lead bonding to a connecting terminal of a semiconductor element. The connection structure of the semiconductor element is characterized in that a surface of the connection lead forming a wide side of the trapezoid is bonded to a pad of a substrate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264132A JP2541005B2 (en) | 1990-10-02 | 1990-10-02 | Semiconductor element mounting structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2264132A JP2541005B2 (en) | 1990-10-02 | 1990-10-02 | Semiconductor element mounting structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH04142048A JPH04142048A (en) | 1992-05-15 |
| JP2541005B2 true JP2541005B2 (en) | 1996-10-09 |
Family
ID=17398907
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2264132A Expired - Fee Related JP2541005B2 (en) | 1990-10-02 | 1990-10-02 | Semiconductor element mounting structure |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2541005B2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63215045A (en) * | 1987-03-04 | 1988-09-07 | Toshiba Corp | Film carrier |
-
1990
- 1990-10-02 JP JP2264132A patent/JP2541005B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH04142048A (en) | 1992-05-15 |
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