JPH02179018A - Surface mount type surface acoustic wave device - Google Patents

Surface mount type surface acoustic wave device

Info

Publication number
JPH02179018A
JPH02179018A JP33528988A JP33528988A JPH02179018A JP H02179018 A JPH02179018 A JP H02179018A JP 33528988 A JP33528988 A JP 33528988A JP 33528988 A JP33528988 A JP 33528988A JP H02179018 A JPH02179018 A JP H02179018A
Authority
JP
Japan
Prior art keywords
base
electrode
conductor layer
frame
board
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP33528988A
Other languages
Japanese (ja)
Inventor
Kimio Seike
政家 公夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Murata Manufacturing Co Ltd
Original Assignee
Murata Manufacturing Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Murata Manufacturing Co Ltd filed Critical Murata Manufacturing Co Ltd
Priority to JP33528988A priority Critical patent/JPH02179018A/en
Publication of JPH02179018A publication Critical patent/JPH02179018A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To provide an electromagnetic shield performance to a surface acoustic wave device and to improve the S/N by forming a lower conductor layer to an upper face provided with an external electrode, providing a ground electrode in continuity with the lower conductor to an outer circumferential face of the base and connecting an upper conductor layer to the ground electrode with a connection electrode provided to a frame. CONSTITUTION:A package 13 containing a surface acoustic wave element 4 consists of a base 3, a frame 5 and a cover 6, and the base 3 forms a lower conductor layer 7 with a comparatively wider area to a middle part of the upper face of a base board 11 such as an epoxy laminated plate. Moreover, a ground electrode 8 is formed to a semi-circular notch 12 provided in the middle of both side faces of the board 11 and the lower conductor layer 7 and the electrode 8 are connected by a connection wiring pattern 14. Furthermore, a couple of input external electrodes 1 and a couple of output external electrodes 2 are formed to semi-circular notches 15, 16 provided to both ends of both side faces of the board 11 and an element connection pad 17 is prolonged to the upper side of the board 11 from electrodes 1, 2 respectively.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、弾性表面波を利用した表面波素子をパッケー
ジ内に納めた表面実装型の表面波デバイスに間する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a surface-mounted surface-wave device in which a surface-wave element utilizing surface acoustic waves is housed in a package.

〔背景技術〕[Background technology]

本発明に用いられるパッケージに類似したものとしては
、LSI等のパッケージングに用いられている第4図に
示すような構造のチップキャリア37がある。これはエ
ポキシ積層板を用いたベース31の上面外周部と外周面
とにそれぞれメツキ等によりポンディングパッド32と
タップ33とを形成し、中央のダイアタッチメント部3
4に搭載されたLSIチップ(図示せず)とポンディン
グパッド32との間にボンディング配線した後、LSI
チップを囲むようにしてベース31の上に枠35を重ね
、さらに枠35の上面に1236を被せ、ベース31と
枠35と菱36を接着剤等により張り合わせてLSIチ
ップをチップキャリア37内に密封するものである。
A package similar to the one used in the present invention is a chip carrier 37 having a structure as shown in FIG. 4, which is used for packaging LSIs and the like. This is done by forming a bonding pad 32 and a tap 33 by plating or the like on the upper and outer circumferential surfaces of a base 31 made of an epoxy laminate, respectively, and forming a die attachment part 33 in the center.
After bonding wiring between the LSI chip (not shown) mounted on 4 and the bonding pad 32, the LSI
A frame 35 is stacked on top of the base 31 so as to surround the chip, and 1236 is further placed on the top surface of the frame 35, and the base 31, frame 35, and diamond 36 are pasted together with adhesive or the like to seal the LSI chip inside the chip carrier 37. It is.

しかしながら、このようなチップキャリアはLSIチッ
プを密封するためのものであり、これまで電磁シールド
機能を備えたチップキャリアは無かった。
However, such chip carriers are for hermetically sealing LSI chips, and until now there has been no chip carrier with an electromagnetic shielding function.

また、従来の表面実装型の表面波デバイスでは、例えば
実開昭60−47321号公報(図示せず)に開示され
ているように、下面に凹みを設けられた蓋を表面波素子
の表面に直接接着して表面波素子の回路を密封している
だけであり、電磁シールド性能を備えたパッケージは無
かった。
In addition, in conventional surface-mounted surface wave devices, as disclosed in Utility Model Application Publication No. 60-47321 (not shown), a lid with a recess on the bottom surface is attached to the surface of the surface wave element. There was no package with electromagnetic shielding performance, as the circuit of the surface wave element was simply sealed by direct adhesion.

このため、従来の表面波デバイスにあっては、外部の電
磁ノイズのために出力信号のノイズが増大するといった
問題があった。
For this reason, conventional surface wave devices have a problem in that noise in the output signal increases due to external electromagnetic noise.

[発明が解決しようとする課題〕 しかして、本発明は上述の背景技術に鑑みてなされたも
のであり、表面波素子を内蔵させる表面実装型のパッケ
ージに電磁シールド性能を持たせることを目的とする6 1課題を解決するための手段〕 このため本発明の表面実装型表面波デバイスは、外部電
極を備えたベースの上に表面波素子を搭載し、表面波素
子を囲むようにしてベースの上面に枠を載置し、枠の上
面に蓋を被せて表面波素子を密封した表面波デバイスに
おいて、前記ベースの」二面に子連体層を形成すると共
にベースの外周面にP′導体層と導通したアース電極を
設け、前記益の下面に、L導体層を形成し、前記枠に設
けられた接続用電極によって前記」二連体層を前記アー
ス電極に電気的に接続させたことを特徴としている。
[Problem to be solved by the invention] However, the present invention has been made in view of the above-mentioned background technology, and its purpose is to provide electromagnetic shielding performance to a surface mount type package in which a surface wave element is incorporated. 6.1 Means for Solving the Problems] For this reason, the surface-mounted surface wave device of the present invention has a surface wave element mounted on a base provided with an external electrode, and a surface wave element mounted on the upper surface of the base so as to surround the surface wave element. In a surface wave device in which a frame is placed and a lid is placed on the top surface of the frame to seal the surface wave element, a chain layer is formed on two sides of the base, and conduction is established with the P' conductor layer on the outer peripheral surface of the base. A ground electrode is provided, an L conductor layer is formed on the lower surface of the wire, and the double layer is electrically connected to the ground electrode by a connecting electrode provided on the frame. .

〔作用〕[Effect]

本発明にあっては、ベースの」−向に設けられた子連体
層と蓋の下面に設けられた1導体層との間に表面波素子
が挟まれた構造となるので、表面波素子を外部の電磁ノ
イズからシールドすることができ、外部のノイズを拾う
ことがなくて S/N比等を向」二させることができる
。しかずう、枠に設けた接続用電極によって菅の−1−
導体層をアース電極に導通させているので、蓋とベース
との間に枠を挟んでパッケージを組み立てるだけでも容
易に−に導体層をアース電極に接続することができる。
In the present invention, since the surface wave element is sandwiched between the child chain layer provided in the - direction of the base and the one conductor layer provided on the lower surface of the lid, the surface wave element is It can be shielded from external electromagnetic noise, and the S/N ratio can be improved without picking up external noise. However, the -1- of the tube is connected by the connection electrode provided on the frame.
Since the conductor layer is electrically connected to the earth electrode, the conductor layer can be easily connected to the earth electrode simply by assembling the package by sandwiching the frame between the lid and the base.

また、基板への実装時にはアース電極をアー・スライン
に接続するだけで上下導体層をアース1゛ることができ
、実装作業も容易に行える。
Furthermore, when mounting on a board, the upper and lower conductor layers can be grounded by simply connecting the ground electrode to the ground line, making the mounting work easy.

〔実施例」 以r 本発明の実施例を添付図に基づいて詳述する。〔Example" Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

表面波素子4を納めるパッケージ13は、第1図に示す
ようにベース3と枠5と菅6とがらなっており、各々エ
ポキシ積層板などの銅張積層板(図面では、銅箔パター
ン部に斜線を施しである。)によって形成されている。
As shown in FIG. 1, the package 13 that houses the surface wave element 4 has a base 3, a frame 5, and a tube 6, each of which is made of a copper-clad laminate such as an epoxy laminate (in the drawing, the copper foil pattern is marked with diagonal lines). is an alms.).

ベース3は、エポキシ積層板等のベース基板1]の上面
中央部に比較的広い面積の子連体N7を形成し、ベース
基板11の両側面中央部に設けられた半円弧状の切欠部
12にアース電極8を形成したものであり、子連体層7
とアース電極8とは接続用配線パターン】4によって電
気的に接続されている。また、ベース基板11の両側面
両端部にも半円弧状の切欠部15.16を設けてあり、
両切尖部1.5,1.6にそれぞれ一対の入力側外部電
極lと一対の出力側外部電極2を形成してあり、各々の
外部電極1,2からはベース基板11の上面へ向けて素
子接続バッド17が延出されている。このベース3は、
ベース親基板(図示せず)を切り離して得られるもので
あり、ベース親基板の上面にはベース3の子連体Iば7
と接続用配線パターン】4と素子接続バッド17に相当
する銅箔の繰り返しパターンが形成されており、またア
ース電極8と外部電極1,2に対応する箇所には各々ス
ルーホールが形成されている。しかして、スルーホール
を2つに分割するようにベース親基板を切り離すことに
より複数枚のベース3が得られるのであり、各スルーポ
ールメツキがアース電極8及び外部な極1,2となる。
The base 3 has a relatively wide area N7 formed in the center of the upper surface of the base substrate 1, such as an epoxy laminate, and a semicircular notch 12 provided in the center of both sides of the base substrate 11. A ground electrode 8 is formed, and a child chain layer 7
and the ground electrode 8 are electrically connected by a connection wiring pattern 4. Further, semicircular arc-shaped notches 15 and 16 are provided at both ends of both sides of the base board 11.
A pair of input-side external electrodes 1 and a pair of output-side external electrodes 2 are formed on both cutting edges 1.5 and 1.6, respectively, and each external electrode 1 and 2 is directed toward the upper surface of the base substrate 11. An element connection pad 17 is extended. This base 3 is
It is obtained by separating the base parent board (not shown), and the child connected body I7 of the base 3 is on the upper surface of the base parent board.
A repeating pattern of copper foil corresponding to the connection wiring pattern 4 and the element connection pad 17 is formed, and through holes are formed at the locations corresponding to the ground electrode 8 and the external electrodes 1 and 2. . Thus, a plurality of bases 3 can be obtained by separating the base substrate so as to divide the through hole into two, and each through pole plating becomes the ground electrode 8 and the external poles 1 and 2.

枠5は、角枠状をした枠基板】8の両側面中央部にそれ
ぞれ円弧状の切欠部19を設け、この切欠部]9に接続
用電極10を形成したものである。枠5の外寸はベース
3の外寸と等しくな−)ており、接続用電極10は枠5
をベース3の上面に重ねた時にベース3のアース電極8
と合致するように配置されている。また、内部に表面波
素子4を納めることができるように枠5の内寸及び厚み
を決めであるにの枠5も、砕穀基板(図示せず)を切り
離して得られるものであり、砕穀基板には枠孔を所定ピ
ッチ毎に開口してあり、接続用電極10に相当する箇所
にはスルーホールが設けられている。しかして、この枠
組基板をスルーホールを2分割するように所定寸法に切
り離すことにより複数枚の枠5が得られるのであり、各
スルーホールメツキが接続用電i10となる。
The frame 5 is a rectangular frame substrate [8] with arc-shaped notches 19 provided at the center of both sides thereof, and connection electrodes 10 formed in the notches [9]. The outer dimensions of the frame 5 are equal to the outer dimensions of the base 3, and the connection electrode 10 is attached to the frame 5.
When placed on top of the base 3, the ground electrode 8 of the base 3
are arranged to match. In addition, the frame 5, whose inner dimensions and thickness are determined so that the surface wave element 4 can be housed therein, is also obtained by cutting off the crushed grain substrate (not shown). Frame holes are opened in the grain substrate at predetermined pitches, and through holes are provided at locations corresponding to the connection electrodes 10. By cutting this frame board into predetermined dimensions so as to divide the through holes into two, a plurality of frames 5 can be obtained, and each through hole plating becomes a connecting wire i10.

蓋6は、ベース基板11と同じ寸法の角板状をした蓋基
板20の下面全面に銅箔を貼って主導体層9を形成した
ものである。この蕎6も、下面全面に銅箔を貼られた銅
張積層板の養親基板(図示せず)を所定寸法に切り離し
て得られるものである。
The lid 6 has a main conductor layer 9 formed by pasting copper foil on the entire lower surface of a lid substrate 20 in the shape of a rectangular plate having the same dimensions as the base substrate 11. This soba 6 is also obtained by cutting into predetermined dimensions a mother board (not shown) of a copper-clad laminate whose entire lower surface is coated with copper foil.

表面波素子4は、第2図では簡略に示しであるが、素子
基板21の表面に一対のくし形電極(■DT)22が設
けられており、素子基板21の両端部にはそれぞれ一対
の入力側引出しバッド23と出力側引出しバッド24が
設けられている。
Although the surface wave element 4 is only shown in a simplified manner in FIG. An input side drawer pad 23 and an output side drawer pad 24 are provided.

次に1表面波デバイスの組立て方法について説明する。Next, a method of assembling one surface wave device will be explained.

跋ず、第2図に示すように、表面波素子4のくし形電極
22を設けられている表面を下方に向け、表面波素子4
を子連体層7から浮かせてくし形電極22を子連体層7
から電気的及び機械的に分離した状態で各々対応する引
出しバッド23.24と素子接続バッド17.17とを
リフロー半田25等によって半田付けする。ついで、ベ
ース3の上に枠5を載置し、接着剤により枠5の下面を
ベース3に接着する。これにより表面波素子4は枠5内
に納められ、ベース3のアース電極8と枠5の接続用電
極10とが上下で電気的に接触させられる。この後、枠
5の上面に蓋6を被せ、接続用電極10を主導体層9に
電気的に接触させ、接着剤によって蓋6を枠5の上面に
接着する。こうして、表面波素子4はベース3と枠5と
126とからなるパッケージ13内に気密的に密封され
、表面実装用として組み立てられるのである。すなわち
、この表面実装型表面波デバイスは、配線基板(図示せ
ず)の上に仮止めされ、各入出力側外部電極1,2とア
ース電極8を配線基板のランド部にリフロー半田法など
によって半田付けされるのである。こうして、アース電
極8が配線基板のアースライン等に接続されると、子連
体層7がアースされ、主導体層9も接続用電極10を介
してアースされるので、内部の表面波素子4はアースさ
れた上下導体層7間に挟まれることになり、電磁シール
ドされる。なお、アース電極8と接続用電極lOと主導
体層9とは、単に接触によって電気的導通を得るだけで
なく、互いに半田被膜で電気的にブリッジさせることに
よって主導体層9のアースを完全にすることができるが
、これは別途工程によることなく表面波デバイスを配線
基板に実装する際にフロー半田によってアース電極8と
接続用電極10と下導体層9間に半田被膜が形成される
ようにしてもよい。
As shown in FIG.
The comb-shaped electrode 22 is lifted from the chain layer 7 and the comb-shaped electrode 22 is
The respective corresponding drawer pads 23 and 24 and element connection pads 17 and 17 are soldered using reflow solder 25 or the like in a state where they are electrically and mechanically separated from each other. Next, the frame 5 is placed on the base 3, and the lower surface of the frame 5 is adhered to the base 3 with adhesive. As a result, the surface wave element 4 is housed in the frame 5, and the ground electrode 8 of the base 3 and the connection electrode 10 of the frame 5 are electrically contacted at the top and bottom. Thereafter, the top surface of the frame 5 is covered with the lid 6, the connection electrode 10 is brought into electrical contact with the main conductor layer 9, and the lid 6 is adhered to the top surface of the frame 5 with an adhesive. In this way, the surface wave device 4 is hermetically sealed within the package 13 consisting of the base 3, frame 5, and 126, and assembled for surface mounting. That is, this surface mount type surface wave device is temporarily fixed on a wiring board (not shown), and each input/output side external electrode 1, 2 and ground electrode 8 are connected to the land part of the wiring board by reflow soldering or the like. It is soldered. In this way, when the ground electrode 8 is connected to the ground line of the wiring board, the child chain layer 7 is grounded, and the main conductor layer 9 is also grounded via the connection electrode 10, so that the internal surface wave element 4 It is sandwiched between the grounded upper and lower conductor layers 7 and is electromagnetically shielded. Note that the grounding electrode 8, the connecting electrode IO, and the main conductor layer 9 not only obtain electrical continuity through mere contact, but also completely connect the main conductor layer 9 by electrically bridging each other with a solder film. However, this method allows a solder film to be formed between the ground electrode 8, the connection electrode 10, and the lower conductor layer 9 by flow soldering when the surface wave device is mounted on the wiring board without a separate process. You can.

上記の組立て方法の説明では、各々親基板から切り離し
た後のベースと枠と蓋を組み合わせる場合を説明したが
、親基板のままで組み立てることにより製造工程を簡単
にすることができる。すなわち、ベース親基板の上面に
子連体層と対応させるようにして複数個の表面波素子を
搭載し、枠孔内に表面波素子を納めるようにして枠組基
板をベース親基板の上に重ねて接着し、この枠組基板の
上に養親基板を重ねて接着し、この後親基板の組立体を
切断して複数個の表面波デバイスを製造するのである。
In the above description of the assembly method, the case where the base, frame, and lid are assembled after being separated from the parent board has been described, but the manufacturing process can be simplified by assembling with the parent board as it is. That is, a plurality of surface wave elements are mounted on the upper surface of the base motherboard so as to correspond to the sub-assembly layer, and the frame substrate is stacked on top of the base motherboard so that the surface wave elements are housed in the frame holes. A foster mother substrate is superimposed and adhered on top of this framework substrate, and then the mother substrate assembly is cut to manufacture a plurality of surface wave devices.

これにより、接着剤の塗布工程や親基板の切断工程など
の工程数を大幅に削減できる。
As a result, the number of steps such as the adhesive application step and the mother board cutting step can be significantly reduced.

なお、上記の説明では4端子の表面波フィルターの場合
について説明したが、本発明はこれに限定されるもので
なく、表面波素子の種類が異なれば外部電極数などは変
化する。さらに、ベース及び枠には両面銅張積層板を用
いてアース電極や接続用電極等の上下の縁にランド部を
形成し、アース電極と接続用電極と主導体層との接触面
積が大きくなるようにしてもよい、また、ベースにはエ
ポキシ積層板等に銅箔を貼っな銅張積層板を用いたが、
セラミック基板等に蒸着膜を形成したものなどでもよい
、また、上記実施例では、スルーホールを利用して各1
を極を設けたので、半円弧状の切欠部に電極が設けられ
ているが、スルーホールを利用しない場合などには、切
欠部を設けることなく各電極を形成してもよい。
Note that although the above description has been made regarding the case of a four-terminal surface wave filter, the present invention is not limited thereto, and the number of external electrodes and the like will vary depending on the type of surface wave element. In addition, double-sided copper-clad laminates are used for the base and frame to form lands on the upper and lower edges of the ground electrode, connection electrode, etc., increasing the contact area between the ground electrode, connection electrode, and main conductor layer. Alternatively, a copper-clad laminate, such as an epoxy laminate with copper foil attached, was used as the base.
It may also be a ceramic substrate with a vapor-deposited film formed thereon.In addition, in the above embodiment, through-holes are used to
Since the poles are provided, the electrodes are provided in the semicircular notch, but if a through hole is not used, each electrode may be formed without providing the notch.

〔発明の効果〕〔Effect of the invention〕

本発明によれば、表面波デバイスに電磁シールド性能を
持たせることができるので、外部の電磁ノイズから表面
波素子を遮蔽することができ、外部のノイズを拾ってS
/N比を低下させたり、誤信号を送り出したりすること
を防止できる。また、ベースと枠と蓋を重ねてパッケー
ジを組み立てるだけで上場体層もアースに導通させるこ
とができ、組立作業を簡単にすることができる。さらに
、アース電極を基板のアースラインなどに半田等で固定
するだけで上下導体層をアースすることができ、実装作
業も容易に行えるものである。
According to the present invention, since the surface wave device can be provided with electromagnetic shielding performance, the surface wave element can be shielded from external electromagnetic noise, and the surface wave element can be shielded from external electromagnetic noise.
It is possible to prevent the /N ratio from decreasing and sending out erroneous signals. In addition, by simply assembling the package by stacking the base, frame, and lid, the listed body layer can also be electrically connected to the ground, simplifying the assembly process. Furthermore, the upper and lower conductor layers can be grounded simply by fixing the ground electrode to the ground line of the board with solder or the like, making the mounting work easy.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の一実施例におけるパッケージの分解斜
視図、第2図は同上のベースの上に表面波素子を搭載し
た状態を示す正面図、第3図は組み立てられた表面波デ
バイスを示す正面図、第4図は従来例のパッケージを示
す分解斜視図である。 1・・・入力側外部電極  2・・・出力側外部電極3
・・・ベース 5・・・枠 7・・・1導体層 9・・・上場体層 4・・・表面波素子 6・・・菱 8・・・アース電極 10・・・接続用電極 第 図
Fig. 1 is an exploded perspective view of a package according to an embodiment of the present invention, Fig. 2 is a front view showing a surface wave element mounted on the same base, and Fig. 3 is an assembled surface wave device. FIG. 4 is an exploded perspective view showing a conventional package. 1... Input side external electrode 2... Output side external electrode 3
... Base 5 ... Frame 7 ... 1 Conductor layer 9 ... Listed body layer 4 ... Surface wave element 6 ... Diamond 8 ... Earth electrode 10 ... Connection electrode diagram

Claims (1)

【特許請求の範囲】[Claims] (1)外部電極を備えたベースの上に表面波素子を搭載
し、表面波素子を囲むようにしてベースの上面に枠を載
置し、枠の上面に蓋を被せて表面波素子を密封した表面
波デバイスにおいて、前記ベースの上面に下導体層を形
成すると共にベースの外周面に下導体層と導通したアー
ス電極を設け、前記蓋の下面に上導体層を形成し、前記
枠に設けられた接続用電極によって前記上導体層を前記
アース電極に電気的に接続させたことを特徴とする表面
実装型表面波デバイス。
(1) A surface where the surface wave element is mounted on a base equipped with external electrodes, a frame is placed on the top of the base so as to surround the surface wave element, and a lid is placed on the top of the frame to seal the surface wave element. In the wave device, a lower conductor layer is formed on the upper surface of the base, a ground electrode that is electrically connected to the lower conductor layer is provided on the outer peripheral surface of the base, an upper conductor layer is formed on the lower surface of the lid, and a lower conductor layer is provided on the frame. A surface-mounted surface wave device, characterized in that the upper conductor layer is electrically connected to the ground electrode by a connecting electrode.
JP33528988A 1988-12-28 1988-12-28 Surface mount type surface acoustic wave device Pending JPH02179018A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP33528988A JPH02179018A (en) 1988-12-28 1988-12-28 Surface mount type surface acoustic wave device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP33528988A JPH02179018A (en) 1988-12-28 1988-12-28 Surface mount type surface acoustic wave device

Publications (1)

Publication Number Publication Date
JPH02179018A true JPH02179018A (en) 1990-07-12

Family

ID=18286856

Family Applications (1)

Application Number Title Priority Date Filing Date
JP33528988A Pending JPH02179018A (en) 1988-12-28 1988-12-28 Surface mount type surface acoustic wave device

Country Status (1)

Country Link
JP (1) JPH02179018A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262513B1 (en) * 1995-06-30 2001-07-17 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6320739B1 (en) 1998-04-18 2001-11-20 Tdk Corporation Electronic part and manufacturing method therefor
KR100462138B1 (en) * 2000-08-25 2004-12-17 히다찌 에이아이시 가부시키가이샤 Electronic device sealing electronic element therein and manufacturing method thereof, and printed wiring board suitable for such electronic device
US20170179920A1 (en) * 2015-12-22 2017-06-22 Murata Manufacturing Co., Ltd. Electronic component
JP2018006931A (en) * 2016-06-29 2018-01-11 株式会社村田製作所 Acoustic wave device

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6262513B1 (en) * 1995-06-30 2001-07-17 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6628043B2 (en) * 1995-06-30 2003-09-30 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6754950B2 (en) * 1995-06-30 2004-06-29 Kabushiki Kaisha Toshiba Electronic component and method of production thereof
US6320739B1 (en) 1998-04-18 2001-11-20 Tdk Corporation Electronic part and manufacturing method therefor
KR100462138B1 (en) * 2000-08-25 2004-12-17 히다찌 에이아이시 가부시키가이샤 Electronic device sealing electronic element therein and manufacturing method thereof, and printed wiring board suitable for such electronic device
US20170179920A1 (en) * 2015-12-22 2017-06-22 Murata Manufacturing Co., Ltd. Electronic component
US10243535B2 (en) * 2015-12-22 2019-03-26 Murata Manufacturing Co., Ltd. Electronic component
JP2018006931A (en) * 2016-06-29 2018-01-11 株式会社村田製作所 Acoustic wave device

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