JPH0237751A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To prevent the malfunction of a circuit by providing a wiring layer for shielding through a layer insulation film at least at an intermediate place of the wiring layer in a crossing region out of two wiring layers impressing signals which are different each other. CONSTITUTION:An insulating film 2 is provided on a semiconductor substrate 1 and wiring layers 3 and 4 for analog signals as well as wiring layers 5 and 6 for digital signals of the first layer which is patterned on the insulating layer 2 are mounted respectively. Then, a layer insulation film 7 is provided on the surface including these wiring layers 3-6 and then, openings 8 for contact are made in layer insulation films 7 located on the wiring layers 5 and 6. Further, electrodes 9 connecting to the openings 8 of the second layer as well as a wiring layer 10 which is separated from the electrodes 9 and has grounding potential on the whole surface except surroundings of the electrodes 9 are mounted on the layer insulation 7. Subsequently, a layer insulation film 11 is formed on the surface including the electrodes 9 and the wiring layer 10 and then, openings 12 for contact in the electrodes 9 are made. Further, wiring layers 13 and 14 for digital signals of the third layer as well as wiring layers 15 and 16 which connect the electrode 9 of the openings 12 are mounted respectively on the layer insulation film 11. The malfunction of a circuit is thus prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit having sophisticated multilayer wiring.

[Conventional technology]

In recent years, efforts have been made to increase the operating speed of semiconductor integrated circuits, to diversify and complicate functions, and the degree of integration has been increasing.

In order to cope with such a situation, semiconductor integrated circuits have been designed to reduce the dimensions of internal transistors and the width of wiring layers, and to increase the number of wiring layers.

FIGS. 3(a) and 3(b) are a plan view and a sectional view taken along the line CC' of a semiconductor chip showing an example of a conventional semiconductor integrated circuit.

As shown in FIGS. 3(a) and 3(b), an insulating film 2 is provided on a semiconductor substrate 1, and includes patterned 1M wiring layers 3, 4 and a wiring layer 34 on the insulating film 2. An interlayer insulating film 7 on the surface, a second wiring layer 5.16 patterned on the interlayer insulating film 7, an intercostal insulating film 11 on the surface including the wiring layer 5.16, P! A protective film 17 is sequentially laminated on the wiring layer 13 patterned on the intermittent insulating film 11 and the wiring J'1W13.

In order to diversify and complicate the functions of semiconductor integrated circuits, the number of circuits in which analog circuits and digital circuits are mixed on the same semiconductor substrate is increasing.

In this case, the analog circuit is very sensitive to external noise, and the digital circuit is not very sensitive to noise because the threshold level at which the digital signal is inverted is large. Under such circumstances, if the digital signal wiring layer overlaps the analog signal wiring layer,
Noise is added to the analog signal wiring layer from the digital signal wiring layer, affecting the analog signal and often leading to malfunction of the analog circuit.

Now, the first wiring layer 3. shown in FIGS.
4 is for analog signals, and the second and third wiring layers 5.16.13 are for digital signals, then the first wiring layer and the second or third wiring layer overlap. A capacitive element is formed by an insulator that separates the wiring layers of each layer in a portion, and capacitive coupling occurs between the wiring layers in these overlapping portions, and the wiring layer 5.16.13
Digital noise is transmitted from the wiring layer to the wiring layers 3 and 4. Here, the thickness of the interlayer insulating film 7 separating the wiring layer 3.4 and the wiring layer 5.16 is calculated as t+(μm)−dielectric constant ε12
(pF/μm), the thickness of the glabella insulating film 11 separating the wiring layer 5.16 and the wiring layer 13 is +2 (μm), the dielectric constant is εtv (pF/, czm), and the wiring layer 3. The area of the overlapping portion of wiring layer 4 and wiring layers 5 and 16 is 512 (μm
2) If the area of the overlapping portion of wiring layer 3.4 and wiring layer 13 is 813 (μm2), and the area of the overlapping portion of wiring layer 5.16 and wiring layer 13 is 523 (μm2). , capacitance C between wiring layer 3.4 and wiring layer 5.16
1□ is C+□(pF)=S+z(ulI12)xg12(pF
/μm)/l+ (um). Also, wiring layer 3.4
And placement 1J? ! Similarly, the capacitance CI3 between the wiring 15.16 and the wiring layer 13 is the capacitance C2 between the wiring 15.16 and the wiring layer 13.
3 is Czs(PF)”Sz3(21m2)X ε23(
pF#m)/12(μm>).

[Problem to be solved by the invention]

In the conventional semiconductor integrated circuit described above, signal changes in digital signals using the second and third wiring layers are superimposed on analog signals using the first wiring layer due to capacitive coupling, resulting in an influence. Eventually, there was a point at which it not only deteriorated the characteristics of analog circuits, but also caused malfunctions.

1'' Means for Solving the Problems] The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having a multilayer wiring structure, in which two wiring layers to which mutually different signals are applied are arranged at least in an intersection region of the two wiring layers. A wiring layer is provided between the two through an interlayer insulating film and connected to a low impedance DC potential.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIGS. 1(a) and 1(a)) are a plan view and a sectional view taken along the line A-A' of a semiconductor chip showing a first embodiment of the present invention.

As shown in FIGS. 1(a) and 1(b), an insulating film 2 is provided on a semiconductor substrate 1, and a first layer of analog signal wiring layers 3, 4 is patterned on the insulating film 2. and wiring layers 5 and 6 for digital signals are provided, respectively. Next, an interlayer insulating film 7 is provided on the surface including these wiring layers 3 to 6, and the wiring layer 5
．． A contact opening 8 is provided in the upper interlayer insulating film 7 of 6.

Next, on the interlayer insulating film 7, an electrode connected to the opening 8 of the second layer is provided, and a wiring layer 10 at a ground potential is provided on the entire surface except around the electrode, separated from the electrode.

Next, an interlayer insulating film 1 is formed on the surface including the electrode 9 and the wiring layer 10.
1 is provided, and a contact opening 12 of the electrode is provided.

Next, wiring layers 15 and 16 for connecting the third layer of digital signal wiring 413 and 14 and the electrodes 9 of the openings 12 are provided on the glabellar insulating film 11, respectively. Next, a protective film 17 is provided on the entire surface.

Here, the first wiring layer 3.4 and the second wiring layer R1
The capacitance C+ (pF) for the area S+ (μm2) of the overlapping portion of 0 is C+ (pF)・S+ (μtz)Xε+2(
pF/μm)/lt (um), and the third wiring layer 13.16 overlapping the wiring layer 3.4 is
Since there is a second wiring layer 10 connected to the ground potential between the wiring layers 3 and 4, the capacity MCI3. CI6 is C10(pF>=Ss (nm2)Xg2.(pF
/μm)/l, z(un)C10(pF)=S++(n
m2) This will not affect wiring layers up to 3.4.

FIGS. 2(a) and 2(b) are a plan view and a sectional view taken along the line B-B' of a semiconductor chip showing a second embodiment of the present invention.

As shown in FIGS. 2(a) and 2(b), the second wiring layer 10 used as a shield is connected to the first wiring layer 3.4 assigned to analog signals and other wirings. It has the same structure as the first embodiment except that it is arranged only around the portion where the layers overlap and is connected to the ground potential. The effect of removing noise from digital signals to analog signals is similar to that of the first embodiment, but in this embodiment, the ground potential of the second layer is selected as in the first embodiment. Since the wiring layer 10 is not arranged over the entire surface, a normal signal wiring layer can also be arranged in the second layer, which has the advantage of increasing the wiring efficiency over the entire area on the semiconductor substrate.

Furthermore, as described in the first and second embodiments,
Of course, the wiring layer used as a shield may be connected not only to the ground potential, but also to a power supply potential, a signal line that performs direct current operation, etc., which has low impedance and stable operation. Furthermore, in a device having more than three wiring layers, not only one wiring layer but several wiring layers may be used as a shield in this manner.

〔Effect of the invention〕

As explained above, the present invention provides multilayer wiring! In a semiconductor integrated circuit having an R structure, a shielding wiring layer is provided between the wiring layers in at least an intersection region of two wiring layers to which different signals are applied, with a glabella insulating film interposed therebetween. This has the effect that interlayer interference can be removed, circuit malfunction can be prevented, and a highly reliable semiconductor integrated circuit can be obtained.

[Brief explanation of the drawing]

1(a) and 1(b) are a plan view and a sectional view taken along the line A-A' of a semiconductor chip showing a first embodiment of the present invention, and FIG.
), (b) are a plan view and a sectional view taken along line B-B' of a semiconductor chip showing a second embodiment of the present invention, and FIG. 3 (a>, (b)
1 is a plan view and a cross-sectional view taken along the line CC' of a semiconductor chip showing an example of a conventional semiconductor integrated circuit. 1... Semiconductor substrate, 2... Insulating film, 3, 4, 5.6
... Wiring layer, 7... Interlayer insulating film, 8... Opening part,
9... Electrode, 1o... Wiring layer, 11... Interlayer insulating film, 12... Opening part, 13, 1.4.15.16.
...Wiring layer, 17...Protective film.

Claims (1)

[Claims] In a semiconductor integrated circuit having a multilayer wiring structure, an interlayer insulating film is provided between two wiring layers to which mutually different signals are applied, at least in the intersection area of the two wiring layers, and the wiring layer is connected to a low impedance DC potential. A semiconductor integrated circuit characterized by having a wiring layer.