JPH0697300A - Inter-wiring structure of semiconductor intgerated circuit - Google Patents

Abstract

PURPOSE:To obtain an inter-wiring structure of a semiconductor integrated circuit where wirings are restrained enough from interfering with each other even if a space is very small between them. CONSTITUTION:A wiring-like conductive layer 11 having no relation with the operation of circuit elements is provided in insulating films 4 and 5 between wirings 1 on the same plane in a semiconductor integrated circuit. As the conductive layer 11 functions as a buffer between the wirings 1, even if noises are generated from a certain wiring 1, the conductive layer 11 prevents the noises from being transmitted to the adjacent wiring 1, so that wirings are restrained front interfering with each other.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring structure of a semiconductor integrated circuit.

[0002]

2. Description of the Related Art Semiconductor integrated circuits include transistors, resistors,
It is composed of an electronic circuit in which circuit elements such as capacitors are connected by a linear conductor such as aluminum, that is, wiring. These wirings are provided so as to be electrically separated from each other by an insulating film. However, as the degree of integration of the circuit increases, the distance between the wirings becomes narrower, and two or three layers are laminated through an interlayer insulating film. Will be provided.

FIG. 3 is a sectional view showing the inter-wiring structure of the conventional semiconductor integrated circuit as described above. In the figure, 1 is a lower layer wiring provided in parallel on the same plane, and 2 is a lower layer wiring 1. A plurality of upper layer wirings stacked above the lower layer wiring 1 in a direction orthogonal to the lower layer wiring 1, 3 is an underlying interlayer insulating film as an insulating film covering the lower surface of the lower layer wiring 1, 4 is a side surface of the lower layer wiring 1, An interlayer insulating film 5 serving as an insulating film covering the upper surface is provided between the interlayer insulating film 4 and the upper layer wiring 2, and an underlying interlayer insulating film serving as an insulating film covering the lower surface of the upper layer wiring 2 is denoted by 6 of the upper layer wiring 2. It is an interlayer insulating film as an insulating film that covers the side surface and the upper surface.

The lower and upper wirings 1 and 2 are electrically completely separated from each other by the interlayer insulating films 3, 4, 5 and 6, and independent electric signals are sent to the connected circuit elements. In the case of a digital element, this electrical signal is normally switched between a low state of 0 V and a high state of several V at nanosecond to microsecond intervals.
This is a Low pattern signal. The lower and upper wirings 1 and 2 are required to accurately and promptly transmit an electric signal to a target circuit element.

[0005]

However, in the lower layer wiring 1 or the upper layer wiring 2 of the circuit which has been highly integrated as described above, since the distance between the wirings in the same layer and between the upper and lower layers is short, the wirings in the same layer are short. There is a problem that inter-wiring interference is likely to occur between the wirings and between the lower wiring 1 and the upper wiring 2.

That is, if noise is generated in one wiring for some reason, this noise is easily transmitted to other wirings adjacent to each other in the vertical and horizontal directions, so that electrical noise can be accurately and promptly applied to many circuit elements. The inconvenience arises that the signal cannot be transmitted.

The present invention has been made to solve the above problems, and provides an inter-wiring structure of a semiconductor integrated circuit capable of sufficiently suppressing inter-wiring interference even if the inter-wiring distance is short. The purpose is to do.

[0008]

According to a first aspect of the present invention, a conductive layer irrelevant to the operation of a circuit element is provided in an insulating film between wirings in the same plane of a semiconductor integrated circuit. That is.

A second aspect of the present invention relates to the operation of a circuit element arranged so as to separate a lower layer wiring and an upper layer wiring in an insulating film between a lower layer wiring and an upper layer wiring of a semiconductor integrated circuit. That is, it has an irrelevant planar conductive layer film.

[0010]

According to the first aspect of the present invention, since the insulating film between the wirings on the same surface has a conductive layer unrelated to the operation of the circuit element, noise is generated in any of these wirings. Even if occurs, this conductive layer acts as a buffer and prevents this noise from being transmitted to another adjacent wiring. That is, the inter-wiring interference between the wirings is prevented.

According to the second aspect of the present invention, a planar conductive layer film irrelevant to the operation of the circuit element is arranged in the insulating film between the lower layer wiring and the upper layer wiring so as to divide them. Even if noise occurs in any of these wirings, this conductive layer film acts as a buffer between the lower layer wiring and the upper layer wiring, and prevents this noise from being transmitted to other adjacent wirings. That is, inter-wiring interference between the lower layer wiring and the upper layer wiring is prevented.

[0012]

Embodiments of the present invention will be described below with reference to the drawings. Example 1. FIG. 1 is a diagram showing an embodiment of an inter-wiring structure of a semiconductor integrated circuit according to the first invention of the present invention. In the figure, it is the same as or equivalent to the inter-wiring structure of the conventional semiconductor integrated circuit shown in FIG. The same reference numerals are given to the parts, and the description thereof will be omitted.

In the figure, numeral 11 denotes a plurality of elements which are formed so as to be embedded in the valleys between the lower layer wirings 1 of the interlayer insulating film 4 and which are irrelevant to the operation of the circuit elements (those which are not applied with an electric signal). It is a wiring-shaped conductive layer, and this conductive layer 11 is W
Polycrystalline silicon doped with impurities such as (tungsten), P (phosphorus), and B (boron) is subjected to CVD (Ch
It is formed by an electronic vapor deposition). The interlayer insulating film 5 is formed above the conductive layer 11.

Next, the operation of the conductive layer 11 will be described.
Since the conductive layer 11 is a conductor arranged in parallel to the lower layer wirings 1 on the same plane and so as to close the space between the lower layer wirings 1, it acts as a buffer (buffer) between the lower layer wirings 1, Inter-wiring interference between the lower layer wirings 1 is prevented. That is, even if noise occurs in any of the lower layer wirings 1 for some reason, this noise is softened by the conductive layer 11 adjacent to the lower layer wirings 1, and this noise is absorbed in the other lower layer wirings adjacent to the lower layer wirings 1. It is prevented from being transmitted to the 1st side. The conductive layer 11 may be provided between the upper wirings 2.

The potential of the conductive layer 11 is set to the lower wiring 1
If the potential is held at an intermediate potential of the electric signal of the High / Low pattern applied to the
When signals in the ow state and the High state coexist instantaneously, it is possible to prevent delay and deterioration (blunting) of electric signals due to capacitive coupling due to inter-wiring capacitance.

That is, since the interlayer insulating film 4 is a dielectric and forms a capacitance (inter-wiring capacitance) between adjacent lower layer wirings 1 adjacent to each other, an electric signal advances in the lower layer wirings 1 while charging this capacitance. I will go. Therefore, if a signal in the Low state and a signal in the High state are generated between the adjacent lower layer wirings 1, the capacitance between the wirings becomes large, causing delay of the electric signal and potential deterioration, which causes a decrease in access time (operating speed) and malfunction. However, in this case, since the conductive layer 11 holds the intermediate potential between the signal potentials in the Low state and the High state, the inter-wiring capacitance can be suppressed to be small, and delay of the electric signal and potential deterioration may occur. Not,
The electric signal can be accurately and quickly transmitted to the circuit element.

Further, since the conductive layer 11 is formed so as to be embedded in the valley between the lower wirings 1 of the interlayer insulating film 4, the step difference is structurally reduced by the formation of the conductive layer 11, and the subsequent processing process is facilitated. And the reliability of the device can be improved.

Example 2. FIG. 2 is a diagram showing an embodiment of an inter-wiring structure of a semiconductor integrated circuit according to the second invention of the present invention. Reference numeral 12 denotes a planar conductive layer film which is thinly formed on the upper surface of the interlayer insulating film 4 and has no relation to the operation of the circuit element, and the material and forming method thereof are the same as those of the conductive layer 11 of the first embodiment. The other structure is the same as the inter-wiring structure of the semiconductor integrated circuit of the first embodiment.

Since the conductive layer film 12 is arranged so as to divide the lower layer wiring 1 and the upper layer wiring 2 into upper and lower layers, it acts as a buffer between the lower layer wiring 1 and the upper layer wiring 2. Further, since the portion between the lower layer wirings 1 of the conductive layer film 12 is arranged so as to bend and enter into the valley portion between the lower layer wirings 1 of the interlayer insulating film 4, it also acts as a buffer between the lower layer wirings 1. To do.

Therefore, for example, when noise occurs in one of the lower layer wirings 1, the conductive layer film 12 prevents the noise from being transmitted to the adjacent lower layer wiring 1 side, and at the same time, the noise is adjacent to the upper layer wirings. It is also prevented from being transmitted to the 2 side. Further, when noise occurs in any of the upper layer wirings 2, the conductive layer film 12 prevents the noise from being transmitted to the adjacent lower layer wiring 1 side.

Further, the conductive layer film 12 is set to High / Lo.
Hold the potential at the midpoint of the w signal and set Low between adjacent wirings.
In the case where the signal in the state and the signal in the High state coexist instantaneously, delay of the electric signal and potential deterioration due to capacitive coupling due to inter-wiring capacitance may be prevented.

In the second embodiment, the conductive layer film 1 is used.
Although the portion between the two lower layer wirings 1 is bent to enter between the lower layer wirings 1, the conductive layer film 12 may be bent to enter between the upper layer wirings 2. In this case, if noise occurs in any of the upper layer wirings 2,
This conductive layer film 12 can prevent the noise from being transmitted to the adjacent upper layer wiring 2 side and the noise from being transmitted to the adjacent lower layer wiring 1 side.

[0023]

Since the present invention is constituted as described above, it has the following effects.

According to the first aspect of the present invention, since the insulating film between each wiring in the same plane of the semiconductor integrated circuit has a conductive layer which is unrelated to the operation of the circuit element, Since the layer acts as a buffer, the inter-wiring interference between the wirings can be sufficiently suppressed even if the inter-wiring distance is short.

According to the second aspect of the present invention, the operation of the circuit element arranged so as to separate the lower wiring and the upper wiring in the insulating film between the lower wiring and the upper wiring of the semiconductor integrated circuit. Since it has a planar conductive layer film unrelated to
Since the conductive layer film acts as a buffer, the inter-wiring interference between the lower layer wiring and the upper layer wiring can be sufficiently suppressed even if the inter-wiring distance is short.

[Brief description of drawings]

FIG. 1 is a schematic cross-sectional view showing an inter-wiring structure of a semiconductor integrated circuit according to a first embodiment of the present invention.

FIG. 2 is a schematic sectional view showing an inter-wiring structure of a semiconductor integrated circuit according to a second embodiment of the invention.

FIG. 3 is a schematic cross-sectional view showing an inter-wiring structure of a conventional semiconductor integrated circuit.

[Explanation of symbols]

 1 Lower layer wiring (wiring) 2 Upper layer wiring (wiring) 4 Interlayer insulating film (insulating film) 5 Interlayer insulating film (insulating film) 11 Conductive layer 12 Conductive layer film

Claims (2)

[Claims] 1. An inter-wiring structure of a semiconductor integrated circuit, comprising a conductive layer irrelevant to the operation of a circuit element in an insulating film between the wirings in the same plane of the semiconductor integrated circuit. 2. A planar surface irrelevant to the operation of a circuit element, which is arranged so as to separate the lower layer wiring and the upper layer wiring in an insulating film between the lower layer wiring and the upper layer wiring of the semiconductor integrated circuit. An interwiring structure of a semiconductor integrated circuit having a conductive layer film.