JPH1098103A - Semiconductor device and manufacturing method thereof - Google Patents

Abstract

(57) [Abstract] (With correction) [Problem] To reduce the wiring interval due to high integration,
Provided are a semiconductor device and a method for manufacturing the same, which can prevent a crosstalk phenomenon occurring between wirings. An insulating film formed on a semiconductor substrate is provided.
A large number of metal wirings 12a, 12b, 12
c is formed by patterning. The spacing between the metal wirings is smaller than the sub-μm and smaller than the thickness of the wiring layer in accordance with the higher integration, so that the parasitic capacitance between the wirings increases. The first interlayer insulating film 13 is formed on the wiring layer to have a constant thickness so as not to be buried between the wirings. Further, a conductive layer 14 made of Al, W, and Si for preventing cross-talk is formed thereon so as to sufficiently fill the metal wiring. Next, the conductive layer is selectively etched and flattened so that the insulating film 13 is exposed.
An interlayer insulating film 15 is formed. By adding the conductive layer between the metal wires, cross crosstalk due to parasitic capacitance between the wires is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly, to a semiconductor device including a multi-layer substrate capable of preventing cross-talk between wirings and a method of manufacturing the same.

[0002]

2. Description of the Related Art Along with high integration and high-speed processing of a semiconductor device, the distance between metal wirings is reduced to submicron or less, and the total length of wirings is extended. Therefore, parasitic capacitance is generated between wirings. Causes cross talk.

A case where a malfunction occurs due to a crosstalk phenomenon occurring between metal wirings will be described with reference to FIGS.

FIG. 1 is a circuit diagram of a buffer composed of a CMOS inverter. A buffer A and a buffer B have input terminals a and c and output terminals b and d, respectively. Not only is the wiring of the output end b of the buffer A and the wiring of the input end c of the buffer B arranged long, but also the spacing between the output end b and the input end c is arranged narrow.

Subsequently, the operation of the buffers A and B in FIG. 1 will be estimated with reference to the timing chart shown in FIG.

[0006] As shown in FIG.
When a HIGH state signal is applied to the buffer A, a LOW state signal is output to the output terminal b of the buffer A. When a LOW state signal is applied to the input terminal c of the buffer B, the buffer B
A signal in the HIGH state is output to the output terminal d of the switch. When the HIGH signal at the input terminal a of the buffer A goes LOW, the LOW signal at the output terminal b of the buffer A goes HIGH. At this time, a cross-talk phenomenon occurs between the wiring at the output end b of the buffer A and the wiring at the input end c of the buffer B due to parasitic capacitance. Due to this phenomenon, the input terminal c of the buffer B is induced to be higher than the constant voltage Vc in the LOW state, and the output terminal d of the buffer B becomes HIGH.
Since the state is changed from the LOW state to the LOW state and a malfunction occurs, the reliability of the semiconductor device is reduced.

[0007]

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a semiconductor device and a method of manufacturing the same, which can prevent a cross-talk phenomenon occurring between wirings due to a narrowing of wiring intervals due to high integration. Is to do.

[0008]

In order to achieve the above object, a semiconductor device according to a first aspect of the present invention comprises a semiconductor substrate having a plurality of wirings arranged at regular intervals formed thereon. And an insulating film formed on the wiring layer to insulate the wiring, and a conductive layer formed in the insulating film between the wirings.

According to another aspect of the present invention, there is provided a semiconductor device, comprising: a semiconductor substrate; an insulating film formed on the substrate; a semiconductor substrate formed on the insulating film; Formed between the plurality of wirings patterned in the above, a first interlayer insulating film formed on the wiring and an insulating film between the wirings, and the wiring on which the first interlayer insulating film is formed. And a second interlayer insulating film formed on the conductive layer and the first interlayer insulating film, and a conductive layer for preventing crosstalk between the wirings.

In order to achieve the above object, a method of manufacturing a semiconductor device according to the present invention includes a step of forming a wiring layer on a semiconductor substrate by forming a large number of wirings arranged at regular intervals; Forming a first insulating film that insulates the exposed portion, forming a conductive layer so as to fill the space between the wirings, and forming a second insulating film over the first insulating film and the conductive layer.
And forming an insulating film.

[0011]

According to the present invention, by adding a conductive layer for preventing cross-talk, which is insulated from the wiring, between the wirings, the cross-talk phenomenon which occurs due to the parasitic capacitance between the wirings which narrows according to the high integration is reduced. Can be prevented.

[0012]

Embodiments of the present invention will be described below with reference to FIGS.

The present invention is not limited to these embodiments.

FIGS. 3 to 7 are cross-sectional views illustrating a method of manufacturing a semiconductor device capable of preventing crosstalk according to an embodiment of the present invention.

As shown in FIG. 3, an insulating film 11 is formed on a semiconductor substrate 10, and a large number of metal wirings 12a, 12b, 12c are formed on the insulating film 11 by patterning at regular intervals. You. At this time, the metal wiring 12
The distance between the metal wirings 12a, 12b, and 12c is smaller than or equal to submicron in accordance with high integration.
Since the thickness is smaller than the thickness 2c, the parasitic capacitance between the wirings increases.

As shown in FIG. 4, a first structure is formed on the structure shown in FIG.
Interlayer insulating film 13 is formed with a constant thickness. At this time, the first interlayer insulating film 13 is not embedded between the metal wirings 12a, 12b, and 12c, and is formed so as to conform to the shapes of the metal wirings 12a, 12b, and 12c.

As shown in FIG. 5, a conductive layer 14 for preventing cross-talk is formed on the structure of FIG. At this time, the conductive layer 14 is formed of aluminum, tungsten, silicon, or the like, and the thickness of the conductive layer 14 is
It is set so that the space between 2b and 12c is sufficiently filled.

On the other hand, when the distance between metal wirings 12a, 12b, and 12c is large, the thickness of conductive layer 14 is set such that the surface of conductive layer 14 is set to be larger than the surface of metal wirings 12a, 12b, and 12c. To be done.

As shown in FIG. 6, the conductive layer 14 is selectively etched back so that the first interlayer insulating film 13 is exposed, and is flattened. At this time, a chemical-mechanical-polishing technique is used for the etch back.

As shown in FIG. 7, a second
An interlayer insulating film 15 is formed.

According to the above-described embodiment, the conductive layer for preventing the cross-talk between the metal wirings is added between the metal wirings, so that the cross-talk caused by the parasitic capacitance between the wirings can be reduced. Can be prevented.

On the other hand, in the above embodiment, the conductive layer for preventing cross-talk is formed so as to fill the space between the metal wiring layers. However, the conductive layer may be selectively formed.

FIGS. 8 and 9 are cross-sectional views illustrating a method of manufacturing a semiconductor device capable of preventing cross-crosstalk according to another embodiment of the present invention. And the conductive layer is etched back by dry etch back.

That is, as shown in FIG.
On the insulating film 41, a large number of metal wirings 42a, 42b, 42c are formed by patterning at regular intervals. At this time, the metal wiring 42
The distance between the metal wirings 42a, 42b, and 4c is smaller than or equal to submicron in accordance with the high integration.
Since the thickness is smaller than the thickness 2c, the parasitic capacitance between the wirings increases.

Thereafter, a first interlayer insulating film 43 is formed on the entire surface of the substrate to a constant thickness. At this time, the first interlayer insulating film 43 is not embedded between the metal wirings 42a, 42b, and 42c, and can be formed in conformity with the shapes of the metal wiring layers 42a, 42b, and 42c. Subsequently, the first interlayer insulating film 43
Is formed on the conductive layer 44 for preventing cross-talk. At this time, the conductive layer 44 is provided between the metal wirings 42a, 44b and 44c.
Can be embedded or not. For example, the metal wiring 4 on which the interlayer insulating film 43 is formed
The space between 2a, 42b, 42c can be left empty or filled with conductive layer 44.

As shown in FIG. 9, the conductive layer 44 is etched back during the dry etching process so that the first interlayer insulating film 43 can be exposed. With this etch back,
A conductive layer 44 is formed so as to be buried between the metal wirings 42a, 42b, and 42c, and is formed in a spacer shape on the side wall of the metal wiring 42c. Subsequently, a second interlayer insulating film 45 is formed on the entire surface of the substrate.

According to the above embodiment, the conductive layer for preventing cross-talk between the metal wirings is added between the metal wirings and on the side walls of the metal wirings, so that the conductive layer is generated by the parasitic capacitance between the wirings. It is possible to prevent the cross-talk phenomenon that occurs.

Although not shown, the conductive layer for preventing cross-talk can be left floating to reduce the cross-talk phenomenon caused by the parasitic capacitance. Alternatively, it may be configured to be connected to the ground voltage VSS.

[0029]

As described above, according to the present invention,
By adding a conductive layer for preventing cross-talk, which is insulated from the metal wiring, between metal wirings, it is possible to prevent a cross-talk phenomenon caused by a parasitic capacitance between the metal wirings which narrows in accordance with high integration.

[Brief description of the drawings]

FIG. 1 is a circuit diagram of a buffer having a narrow wiring interval.

FIG. 2 is an operation timing chart of the buffer of FIG. 1;

FIG. 3 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 4 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 5 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 6 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 7 is a sectional view illustrating a method of manufacturing a semiconductor device according to an embodiment of the present invention.

FIG. 8 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

FIG. 9 is a sectional view illustrating a method of manufacturing a semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

10, 40 Semiconductor substrate 11, 41 Insulating film 12a, 12b, 12c, 42a, 42b, 42c Metal wiring 13, 43 First interlayer insulating film 14, 44 Conductive layer 15, 45 Second interlayer insulating film

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[Procedure amendment]

[Submission date] September 1, 1997

[Procedure amendment 1]

[Document name to be amended] Statement

[Correction target item name] 0002

[Correction method] Change

[Correction contents]

[0002]

2. Description of the Related Art Along with the high integration and high-speed processing of a semiconductor device, the distance between metal wirings is reduced to submicron or less, and the total length of wirings is extended. Cross talk
lk).

Claims (15)

[Claims] A semiconductor substrate on which a plurality of wirings arranged at regular intervals are formed; an insulating film formed on the wiring layer for insulating the wirings; And a conductive layer formed in the insulating film. 2. The wirings are arranged at equal intervals,
2. The semiconductor device according to claim 1, wherein the semiconductor device is formed on a semiconductor substrate. 3. The semiconductor device according to claim 1, wherein said conductive layer is made of one material selected from the group consisting of aluminum, tungsten, and silicon. 4. The semiconductor device according to claim 1, wherein said conductive layer is floating. 5. The semiconductor device according to claim 1, wherein the conductive layer is connected to a power supply voltage VDD. 6. The semiconductor device according to claim 1, wherein the conductive layer is connected to a ground voltage VSS. 7. A semiconductor substrate, an insulating film formed on the substrate, a large number of wirings formed on the insulating film and patterned at regular intervals, and between the wirings and the wirings. First formed on the insulating film of
An interlayer insulating film, a conductive layer formed between the wires on which the first interlayer insulating film is formed, and for preventing cross-talk between the wires, the conductive layer and the first interlayer insulating film Second formed on
A semiconductor device comprising an interlayer insulating film. 8. The semiconductor device according to claim 7, wherein said conductive layer is made of one material selected from the group consisting of aluminum, tungsten, and silicon. 9. The semiconductor device according to claim 7, wherein said conductive layer is selectively formed between wirings covering said second interlayer insulating film. 10. A step of forming a wiring layer on a semiconductor substrate with a large number of wirings arranged at regular intervals; forming a first insulating film for insulating exposed portions of the wirings; A method of manufacturing a semiconductor device, comprising: forming a conductive layer so as to fill a space between wirings; and forming a second insulating film on the first insulating film and on the conductive layer. . 11. The method according to claim 10, wherein the first insulating film is formed to a thickness such that a space can be formed between the first insulating film and the wiring. 12. The step of forming the conductive layer includes the steps of: forming a conductive layer on the first insulating film so as to fill in the power distribution; and exposing the first insulating film on the wiring. 11. The method of manufacturing a semiconductor device according to claim 10, comprising: etching back the conductive layer. 13. The method according to claim 10, wherein the conductive layer is formed of one material selected from the group consisting of aluminum, tungsten, and silicon. 14. The method according to claim 10, wherein the etch-back step is performed by using a CMP technique. 15. The method according to claim 10, wherein the etch-back step is performed by a dry etching method.