US6388328B1 - Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system - Google Patents

Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system Download PDF

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US6388328B1
US6388328B1 US09/143,295 US14329598A US6388328B1 US 6388328 B1 US6388328 B1 US 6388328B1 US 14329598 A US14329598 A US 14329598A US 6388328 B1 US6388328 B1 US 6388328B1
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interconnect
interconnect system
lines
capping layer
interconnect lines
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US09/143,295
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Brian Doyle
Quat T. Vu
Leopold Yau
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Intel Corp
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Intel Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H01L21/76834Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/7682Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5222Capacitive arrangements or effects of, or between wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/76841Barrier, adhesion or liner layers
    • H01L21/7685Barrier, adhesion or liner layers the layer covering a conductive structure
    • H01L21/76852Barrier, adhesion or liner layers the layer covering a conductive structure the layer also covering the sidewalls of the conductive structure
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/012Bonding, e.g. electrostatic for strain gauges
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/914Doping
    • Y10S438/916Autodoping control or utilization
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Abstract

The present invention provides an interconnect system. The interconnect system includes a substrate, a first dielectric layer deposited upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. Each of the at least two interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal to 1. A dielectric film is bonded upon the top surface of the at least two interconnect lines. The dielectric film substantially prevents obstruction of the space by further process.

Description

This is a continuation of application Ser. No. 08/671,968, filed Jun. 28, 1996, U.S. Pat. No. 5,863,832. I hereby claim the benefit under Title 35, United States Code, Section 120 of the U.S. application Ser. No. 08/671,968, filed Jun. 28, 1996.

BACKGROUND OF THE INVENTION

(1) Field of the Invention

The present invention relates generally to integrated electronic circuits. More specifically, the present invention relates to an interconnect system for an integrated circuit and a method of fabricating the interconnect system.

(2) Description of the Related Art

Modern integrated circuits are generally made up of millions of active and passive devices such as transistors, capacitors, and resistors disposed onto a silicon wafer. These devices are initially isolated from one another, but are later interconnected together by an interconnect system to form functional circuits. The quality of the interconnect system drastically affects the performance and reliability of the fabricated circuit.

An interconnect system typically includes metal lines, spaced apart from each other, which interconnect the various active and passive devices found in a silicon wafer onto which the interconnect system had been deposited and fabricated. Insulating dielectric layers are deposited between the metal lines for isolating the metal lines from one another. Inherent in the structure of the interconnect system is a capacitance associated with the metal lines spaced apart from each other. As the capacitance is to first order inversely proportional with the distance between the metal lines, one way to reduce the capacitance between two lines would be to increase the space between the lines. However, this option is limited by the integration capacity of the integrated circuit.

A preferable way to reduce the capacitance between two lines of the interconnect system is to reduce the dielectric constant k of the dielectric material deposited between the metal lines, as the capacitance is directly proportional to the dielectric constant of the dielectric material between the metal lines. Typically, interconnect systems use a dielectric material such as Silicon Dioxide (SiO2). The dielectric constant of SiO2 is approximately 4. Other dielectric materials can be used such as Silicon Oxifluoride (SiOF) with a dielectric constant of 3-3.5, or Aerogel which is a foam with vacuum or air pores with a dielectric constant which can approach the dielectric constant of air, i.e., 1. The problem with dielectric materials having lower dielectric constants is that they may not adequately support the structure of the interconnect system as these materials have a relatively high Young's modulus which makes them relatively soft, especially for materials with the dielectric constant k<2.

FIG. 1 shows a cross-sectional view of an interconnect system 100. The interconnect system 1 has a substrate 2 which typically includes active and passive electronic structures. An insulating layer 4 is deposited over substrate 2. The insulating layer 4 is made of a dielectric material which provides electrical insulation between the substrate 2 and any other electrically conductive layer deposited upon layer 4. Layer 4 could be, by way of non-limiting example, silicon dioxide (SiO2) either doped or undoped, silicon nitride (Si3N4) or silicon oxinitride (SiOxNy). Following the deposition of the insulating layer 4 a metal layer is deposited thereon. Electrically conductive interconnect lines 10 are then formed by etching out selected portions of the metal layer. The electrically conductive interconnect lines 10 serve the purpose of interconnecting various electronic devices, active or passive, which reside in the substrate 2. The interconnect lines 10 are spaced apart from each other in order not to short circuit the various devices to which the interconnect lines are connected. The space between interconnect lines 10 is typically filled with a dielectric material 8 which is deposited upon interconnect lines 10 forming the pattern shown in FIG. 1. A second electrically conductive layer of interconnect lines 26 is formed over the dielectric layer 8 in a direction usually orthogonal to the direction of the interconnect lines 10. Continuing the above process, more insulating layers followed by conducting layers could be deposited to finally form the interconnect system.

The interconnect system illustrated in FIG. 1 uses SiO2 for the dielectric layer 8. While this type of material can provide the mechanical support necessary to withstand the stress of the structures deposited thereupon, the resulting large capacitance between lines, due to the relatively high dielectric constant of SiO2, makes this material less and less desirable in the high performance interconnect systems of the future.

FIG. 2 shows a cross sectional view of an interconnect system 200 wherein the dielectric layer 8 has been applied over interconnect lines 10 so as not to fill out completely the gaps between the interconnect lines 10 and, thus, to provide for air gaps 16 between the interconnect lines 10. However, due to the nature of the structure of the interconnect system and of the various processes for deposition of the dielectric layer 8, which include physical deposition, chemical vapor deposition, and plasma deposition, a certain amount of the dielectric is incorporated between the metal lines 10. As one can see, the dielectric material 8 is still deposited between the metal lines 10 leaving small voids 16. This is undesirable as the dielectric constant and thus the capacitance between the adjacent lines increases with the amount of dielectric material between the lines.

It is desirable to provide for an interconnect system wherein the space between the interconnect lines has a dielectric constant as low as possible and substantially uniform throughout that space.

BRIEF SUMMARY OF THE INVENTION

An interconnect system is disclosed. The interconnect system according to the present invention includes a substrate and a first dielectric layer formed upon the substrate. The interconnect system further includes at least two electrically conductive interconnect lines formed upon the first dielectric layer. The at least two electrically conductive interconnect lines have a top surface and side surfaces. Adjacent side surfaces of two adjacent interconnect lines define therebetween a space that has a dielectric constant substantially equal with 1. A dielectric film is bonded onto the top surfaces of the at least two interconnect lines. The dielectric film substantially prevents obstruction, by further process, of the space formed between the two adjacent side surfaces of the two adjacent interconnect lines.

BRIEF DESCRIPTION OF THE DRAWINGS

The features, aspects, and advantages of the present invention will become more fully apparent from the following Detailed Description, appended claims, and accompanying drawings in which:

FIG. 1 illustrates a cross-sectional view of a prior art interconnect systems;

FIG. 2 illustrates a cross-sectional view of an interconnect system having air gaps interspersed therein;

FIG. 3 illustrates a cross-sectional view of a preferred embodiment according to the present invention;

FIGS. 4a, 4 b and 4 c illustrate a method according to the present invention for bonding a capping layer onto the interconnect lines of an interconnect system; and

FIGS. 5a, 5 b, 5 c and 5 d illustrate an alternative method according to the present invention for bonding a capping layer onto the interconnect lines of an interconnect system.

DETAILED DESCRIPTION OF THE INVENTION

In the following description, numerous specific details are set forth to provide a thorough understanding of the present invention. However, one having ordinary skill in the art will recognize that the invention may be practiced without these specific details. In some instances, well-known circuits, structures, and techniques have not been shown in detail to avoid obscuring the present invention.

Referring now to FIG. 3, a cross-sectional view of a preferred embodiment 300 of the present invention is shown. Substrate 202 can be, by way of non-limiting example, a semiconductor wafer including device regions such as diffused junctions, other structures such as gates, local interconnects, metal layers, or other active or passive device structures or layers. In many cases, depending upon the device being fabricated, device layers or structures, or processing steps used to fabricate the device may have been omitted to avoid obscuring the present invention.

The interconnect system 200 includes a first dielectric layer 204 formed over substrate 202. Layer 204 is generally deposited over substrate 202. First dielectric layer 204 typically has a thickness equal or lower than approximately 1 μm. This layer could be, by way of non-limiting example, Silicon Dioxide (SiO2), doped or undoped, Silicon Nitride (Si3N4), or Silicon Oxinitride (SiOXNY). The first dielectric layer 204 insulates between any conductive structures which are found in the substrate 202 and other conductive layers or lines which are further deposited in the interconnect system 200.

Following the deposition of the oxide layer 204, electrically conductive interconnect lines 210 are fabricated out of an electrically conductive layer formed over oxide layer 204. The electrically conductive layer 210 has a thickness in the range of 0.4 to 2.0 μm. The electrically conductive interconnect lines 210 are generally orthogonal to the plane in which the cross-section of the interconnect system 200 is shown. These interconnect lines 210 can be formed, by way of non-limiting example, by depositing a photoresist layer over the electrically conductive layer. A standard photolithography process is then performed. The photolithography process includes patterning the photoresist layer and etching the electrically conductive layer thereby producing the pattern of interconnect lines 210 shown in FIG. 3.

The interconnect lines 210 are spaced apart by spaces 212 having a width in the range of 0.3 to 2.0 μm. Spaces 212 prevent interconnect lines 210 from being short-circuited. In the embodiment, according to the present invention, the interconnect lines 210 are made of a metal such as aluminum, tungsten, or other similar conducting materials or alloys thereof. The choice of materials may depend on processing considerations. For example, if the substrate 202 is subjected to temperatures of approximately 660° C. or above, aluminum may not be used since the above-mentioned temperature is above aluminum's melting point.

The interconnect lines 210, which are spaced apart from each other, are substantially parallel to one another. Each interconnect line 210 is defined by a top surface 216 and by side surfaces 214 and 218. Adjacent side surfaces of two adjacent interconnect lines 210 define therebetween a space 212. As it is well-known, the capacitance between two interconnect lines is directly proportional to the dielectric constant of the dielectric between the two lines, and first order inversely proportional to the distance separating these lines. The spaces 212 can be filled with a very low dielectric constant material. In this particular embodiment, the dielectric material between the electrically conductive lines 210 is air. As it is well known, the dielectric constant of air is approximately 1. Therefore, the capacitance between the two adjacent interconnect lines having air in the space 212 there between is minimized.

In the preferred embodiment, each interconnect line 210 is coated with a cladding 220, preferably very thin (a few hundred Angstroms) compared to the dimensions of the interconnect line 210. The cladding 220 is deposited over each of the interconnect lines by known processes including physical vapor deposition, chemical vapor deposition, and plasma enhanced deposition. The cladding 220 can act to minimize electro-migration in the interconnect lines 210 and also acts as an adhesion layer to subsequent layers such as films, disposed onto the cladding. By way of non-limiting example, the cladding 220 can be made of TiAl3. In the preferred embodiment illustrated in FIG. 3 both the side surfaces 214 and 218 and the top surface 216, of the interconnect lines 210, are coated by the cladding 220. The process of coating the interconnect lines 210 with the cladding 220 is generally well known to persons skilled in the art.

A dielectric film 222 (hereinafter “capping layer 222”) is laid and bonded over the interconnect lines 210. The capping layer 222 can be made of SiO2 by way of non-limiting example. The capping layer 222 helps provide an interconnect system with air spaces between interconnect lines 210. The capping layer 222 substantially prevents obstruction of the air spaces 212 by further process. These air spaces are thus substantially unencumbered by the capping layer 222 and by the various layers further deposited upon capping layer 222. The capping layer 222 has a thickness sufficient enough to withstand erosion thereof by further process. Such thickness can be, by way of non-limiting example, in the range of a few thousand Angstroms. An interconnect system with low capacitances is therefore provided by having air in spaces 212.

A second level of electrically conductive lines 226 is then formed over the capping layer 222 and the process of forming unencumbered air spaces between the second level of electrically conductive interconnect lines 226 by bonding a capping layer thereupon can be continued up to the desired level of metal lines in the interconnected system 200. A second dielectric layer 224 can be optionally interposed between the capping layer 222 and the interconnect lines 226 (before forming interconnect lines 226). The second dielectric layer 224 is deposited if it is necessary that the interlayer dielectric has a specific thickness.

Also, to better support the electrically conductive lines and the layers of dielectric further deposited upon the capping layer 222, one can insert “dummy” lines 260 and 262 between interconnect lines where the spacing between these interconnect lines is too large. The dummy lines are not coupled to the various active or passive devices residing in the substrate 202. These dummy lines merely serve the purpose of “pillars” in the interconnect system 200.

FIGS. 4a, 4 b, and 4 c illustrate a method for applying and bonding a capping layer 222 onto the interconnect lines of an interconnect system (not shown). At step 1 (FIG. 4a), the capping layer 222 is coated onto a film carrier 250. The film carrier 250 is made of a material which allows for relatively simple debonding of the capping layer 222 later in the process. The film carrier can be an unpatterned silicon wafer by way of non-limiting example. At step 2 (FIG. 4b), capping layer 222, bonded onto a film carrier 250, is placed upon a top surface of a cladding 220 of the interconnect lines 210 of an interconnect system 200. The interconnect system 200 includes the substrate 202 and a layer of SiO2 204 deposited thereon. The interconnect system 200, illustrated in FIGS. 4b and 4 c, is substantially similar to the interconnect system described in conjunction with FIG. 3.

During-step 2, the assembly including the film carrier 250, the capping layer 222, and the interconnect system 200 is heated to a temperature high enough to allow capping layer 222 to debond from film carrier 250. This temperature also allows capping layer 222 to bond onto the cladding 220. This temperature can be, but is not limited to, approximately 400° C. The cladding 220 is made of a material that bonds to the capping layer 222 when the assembly is subjected to heat. The capping layer 222 thus bonds to the claddings 220 of the interconnect lines 210 upon heating the assembly to a temperature of approximately 400°. Concomitantly with the bonding of the capping layer 222 onto the cladding 220, the temperature of approximately 400° C. causes a weakening of the bonding between the capping layer 222 and the film carrier 250. Note that the film carrier 250, onto which the capping layer 222 is bonded at step 1, is particularly selected to have a surface with relatively weak bonding properties. Accordingly, at step 2, while the capping layer 222 bonds to the cladding 220, a simultaneous process occurs-the film carrier 250 gradually debonds from the capping layer 222 due to the weak bonding between the capping layer 222 and the film carrier 250, and to the effect of the temperature upon such weak bonding. The temperature of approximately 400° C. to which the assembly of the interconnect system and the film carrier with the capping layer are subjected acts thus as an agent for bonding the capping layer 222 onto the cladding 220 and also for debonding the capping layer 222 from the film carrier 250.

At step 3 (FIG. 4c), the film carrier 250 is delaminated from the assembly of the interconnect system and the capping layer bonded thereto. Another interconnect isolation layer (the optional second dielectric layer 224 explained in conjunction with FIG. 3) can be deposited on top of the capping layer 222 to yield the desired level of thickness of the dielectric, if the capping layer's thickness itself is not sufficient.

FIGS. 5a, 5 b, 5 c, and 5 d illustrate an alternative method for depositing step 1 (FIG. 5a), capping layer 222 is coated onto a film carrier made of silicon 250. At step 2 (FIG. 5b), the silicon substrate 250 is implanted with ionized Hydrogen H(2×1016-1017 particles/cm3). The implanted ionized Hydrogen creates a stress-dislocated layer which causes delamination of the capping layer at a temperature of approximately 400° C. At step 3 (FIG. 5c), the assembly of the silicon substrate 250 and the capping layer 222 bonded thereto is then placed face down with the capping layer 222 disposed over the cladding 220 of interconnect lines 210 of the interconnect system 200. The assembly of the interconnect system, the silicon substrate, and the film are heated to approximately 400°, thereby causing a delamination of the silicon substrate 204, and forming a thermal bond between capping layer 222 and cladding 220 above each interconnect line. At step 4. (FIG. 5d), a final etch is performed to remove the remaining silicon layer off the capping layer 222. Alternatively, a Hydrogen implant can be performed into the capping layer 222. Upon heating the assembly, the capping layer “splits” into two layers, leaving a first part of a capping layer bonded to the interconnect lines and a second part of capping layer 222 still remaining on silicon substrate 250.

In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will however be evident that various modifications and changes can be made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are, accordingly, to be regarded in an illustrative rather than a restrictive sense. Therefore, the scope of the invention should be limited only by the appended claims.

Claims (8)

What is claimed is:
1. An interconnect system for an integrated circuit comprising:
a substrate;
a first dielectric layer formed upon said substrate;
a plurality of electrically conductive interconnect lines formed upon said first dielectric layer, each of said interconnect lines having top and side surfaces, a space being defined between adjacent side surfaces of adjacent pairs of said interconnect lines, said space being filled with air;
an electrically conductive cladding disposed over said top surface of said interconnect lines; and
a dielectric film having first and second sides, a stress-dislocated layer of silicon covering said first side, said second side of the dielectric film being bonded to said cladding, said space being substantially unencumbered by said dielectric film.
2. The interconnect system of claim 1 wherein said cladding extends of said side surfaces of said interconnect lines.
3. The interconnect system of claim 2 wherein said cladding comprises titanium.
4. The interconnect system of claim 3 wherein said cladding has a thickness in the range of 100-1000 angstroms.
5. The interconnect system of claim 2, wherein cladding comprises a material that minimizes electromigration in said interconnect lines.
6. The interconnect system of claim 1 wherein dielectric film comprises SiO2.
7. The interconnect system of claim 1 wherein said dielectric film has a thickness in the range of a few thousand Angstroms.
8. The interconnect system of claim 6, further including at least one dummy line to support said dielectric film.
US09/143,295 1996-06-28 1998-08-28 Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system Expired - Lifetime US6388328B1 (en)

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US09/143,295 US6388328B1 (en) 1996-06-28 1998-08-28 Capping layer in interconnect system and method for bonding the capping layer onto the interconnect system

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040084749A1 (en) * 2001-03-01 2004-05-06 Werner Pamler Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit
US6737725B2 (en) * 2000-08-31 2004-05-18 International Business Machines Corporation Multilevel interconnect structure containing air gaps and method for making
US20050253269A1 (en) * 2004-05-12 2005-11-17 Semiconductor Leading Edge Technologies, Inc. Semiconductor device

Families Citing this family (40)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6728113B1 (en) * 1993-06-24 2004-04-27 Polychip, Inc. Method and apparatus for non-conductively interconnecting integrated circuits
US5624868A (en) * 1994-04-15 1997-04-29 Micron Technology, Inc. Techniques for improving adhesion of silicon dioxide to titanium
US6232216B1 (en) * 1996-04-16 2001-05-15 Nippon Telegraph And Telephone Corporation Thin film forming method
FR2748851B1 (en) * 1996-05-15 1998-08-07 Commissariat Energie Atomique A method of making a thin layer of semiconductor material
FR2756847B1 (en) * 1996-12-09 1999-01-08 Commissariat Energie Atomique A method of separating at least two elements of a structure in contact with each other by ion implantation
US6054377A (en) * 1997-05-19 2000-04-25 Motorola, Inc. Method for forming an inlaid via in a semiconductor device
JP3431454B2 (en) * 1997-06-18 2003-07-28 株式会社東芝 A method of manufacturing a semiconductor device
US5949108A (en) * 1997-06-30 1999-09-07 Intel Corporation Semiconductor device with reduced capacitance
US6492732B2 (en) * 1997-07-28 2002-12-10 United Microelectronics Corp. Interconnect structure with air gap compatible with unlanded vias
JPH11154675A (en) * 1997-11-20 1999-06-08 Toshiba Corp Semiconductor device and manufacture thereof
US6465339B2 (en) * 1997-12-19 2002-10-15 Texas Instruments Incorporated Technique for intralevel capacitive isolation of interconnect paths
FR2773261B1 (en) 1997-12-30 2000-01-28 Commissariat Energie Atomique Method for transferring a thin film having a step of creating inclusions
US6365488B1 (en) * 1998-03-05 2002-04-02 Industrial Technology Research Institute Method of manufacturing SOI wafer with buried layer
JP3214441B2 (en) 1998-04-10 2001-10-02 日本電気株式会社 Semiconductor device and manufacturing method thereof
US6329718B1 (en) * 1998-06-26 2001-12-11 Advanced Micro Devices, Inc. Method for reducing stress-induced voids for 0.25mμ and smaller semiconductor chip technology by annealing interconnect lines and using low bias voltage and low interlayer dielectric deposition rate and semiconductor chip made thereby
US6054370A (en) * 1998-06-30 2000-04-25 Intel Corporation Method of delaminating a pre-fabricated transistor layer from a substrate for placement on another wafer
US6423614B1 (en) * 1998-06-30 2002-07-23 Intel Corporation Method of delaminating a thin film using non-thermal techniques
US6060383A (en) * 1998-08-10 2000-05-09 Nogami; Takeshi Method for making multilayered coaxial interconnect structure
TW401618B (en) * 1998-09-23 2000-08-11 Nat Science Council Manufacture method of the dielectrics and the structure thereof
US6130151A (en) * 1999-05-07 2000-10-10 Taiwan Semiconductor Manufacturing Company Method of manufacturing air gap in multilevel interconnection
WO2001028000A1 (en) * 1999-10-14 2001-04-19 Shin-Etsu Handotai Co., Ltd. Method for manufacturing soi wafer, and soi wafer
JP3957038B2 (en) * 2000-11-28 2007-08-08 シャープ株式会社 Semiconductor substrate and a manufacturing method thereof
FR2823599B1 (en) 2001-04-13 2004-12-17 Commissariat Energie Atomique Substrate demomtable held mechanical controlled and method of realization
TW559950B (en) * 2002-03-13 2003-11-01 Macronix Int Co Ltd Memory device and method of forming passivation film thereof
FR2848336B1 (en) * 2002-12-09 2005-10-28 Commissariat Energie Atomique Method of realization of a constraint structure destiny has to be dissociated
US7009272B2 (en) * 2002-12-28 2006-03-07 Intel Corporation PECVD air gap integration
KR100510821B1 (en) * 2003-06-09 2005-08-30 한국전자통신연구원 Fabrication method using a temporary substrate of micro structures
FR2856844B1 (en) * 2003-06-24 2006-02-17 Commissariat Energie Atomique Integrated circuit chip high performance
FR2857953B1 (en) 2003-07-21 2006-01-13 Commissariat Energie Atomique STACKED structure, and process for the manufacture
FR2861497B1 (en) * 2003-10-28 2006-02-10 Soitec Silicon On Insulator Process for catastrophic transfer of a thin layer after co-implantation
US7425760B1 (en) 2004-10-13 2008-09-16 Sun Microsystems, Inc. Multi-chip module structure with power delivery using flexible cables
FR2889887B1 (en) * 2005-08-16 2007-11-09 Commissariat Energie Atomique method for transferring a thin layer on a support
FR2891281B1 (en) 2005-09-28 2007-12-28 Commissariat Energie Atomique Process for manufacturing a thin-film element.
FR2910179B1 (en) * 2006-12-19 2009-03-13 Commissariat Energie Atomique METHOD OF MANUFACTURING THIN FILM OF GaN BY LOCATION AND RECYCLING OF DEPARTURE SUBSTRATE
US8237283B2 (en) 2007-06-05 2012-08-07 International Business Machines Corporation Structure and method of reducing electromigration cracking and extrusion effects in semiconductor devices
FR2922359B1 (en) * 2007-10-12 2009-12-18 Commissariat Energie Atomique Method of manufacturing a micro-electronic structure involving molecular bonding
FR2925221B1 (en) * 2007-12-17 2010-02-19 Commissariat Energie Atomique A method of transferring a thin layer
FR2947098A1 (en) * 2009-06-18 2010-12-24 Commissariat Energie Atomique method for transferring a thin film on a target substrate having a different thermal expansion coefficient from that of the thin layer
JP2013197407A (en) * 2012-03-21 2013-09-30 Toshiba Corp Semiconductor device
KR20140095824A (en) 2013-01-25 2014-08-04 삼성전자주식회사 Methods for processing substrates

Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112761A (en) 1990-01-10 1992-05-12 Microunity Systems Engineering Bicmos process utilizing planarization technique
US5257162A (en) 1992-11-20 1993-10-26 Intel Corporation Bellows lid for c4 flip-chip package
US5289337A (en) 1992-02-21 1994-02-22 Intel Corporation Heatspreader for cavity down multi-chip module with flip chip
US5289035A (en) 1990-12-27 1994-02-22 Intel Corporation Tri-layer titanium coating for an aluminum layer of a semiconductor device
JPH0697300A (en) * 1992-09-10 1994-04-08 Mitsubishi Electric Corp Inter-wiring structure of semiconductor intgerated circuit
US5414221A (en) 1991-12-31 1995-05-09 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5431863A (en) 1991-01-28 1995-07-11 Nitto Denko Corporation Method of mounting semiconductor device
US5476817A (en) 1994-05-31 1995-12-19 Texas Instruments Incorporated Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers
US5624868A (en) 1994-04-15 1997-04-29 Micron Technology, Inc. Techniques for improving adhesion of silicon dioxide to titanium
US5665644A (en) * 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US5690749A (en) 1996-03-18 1997-11-25 Motorola, Inc. Method for removing sub-micron particles from a semiconductor wafer surface by exposing the wafer surface to clean room adhesive tape material
US5751056A (en) * 1994-05-31 1998-05-12 Texas Instruments Incorporated Reliable metal leads in high speed LSI semiconductors using dummy leads
US5814888A (en) * 1994-06-06 1998-09-29 Texas Instruments Incorporated Semiconductor device having a multilayer wiring and the method for fabricating the device

Patent Citations (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5112761A (en) 1990-01-10 1992-05-12 Microunity Systems Engineering Bicmos process utilizing planarization technique
US5289035A (en) 1990-12-27 1994-02-22 Intel Corporation Tri-layer titanium coating for an aluminum layer of a semiconductor device
US5431863A (en) 1991-01-28 1995-07-11 Nitto Denko Corporation Method of mounting semiconductor device
US5414221A (en) 1991-12-31 1995-05-09 Intel Corporation Embedded ground plane and shielding structures using sidewall insulators in high frequency circuits having vias
US5289337A (en) 1992-02-21 1994-02-22 Intel Corporation Heatspreader for cavity down multi-chip module with flip chip
JPH0697300A (en) * 1992-09-10 1994-04-08 Mitsubishi Electric Corp Inter-wiring structure of semiconductor intgerated circuit
US5257162A (en) 1992-11-20 1993-10-26 Intel Corporation Bellows lid for c4 flip-chip package
US5624868A (en) 1994-04-15 1997-04-29 Micron Technology, Inc. Techniques for improving adhesion of silicon dioxide to titanium
US5476817A (en) 1994-05-31 1995-12-19 Texas Instruments Incorporated Method of making reliable metal leads in high speed LSI semiconductors using both dummy leads and thermoconductive layers
US5751056A (en) * 1994-05-31 1998-05-12 Texas Instruments Incorporated Reliable metal leads in high speed LSI semiconductors using dummy leads
US5814888A (en) * 1994-06-06 1998-09-29 Texas Instruments Incorporated Semiconductor device having a multilayer wiring and the method for fabricating the device
US5665644A (en) * 1995-11-03 1997-09-09 Micron Technology, Inc. Semiconductor processing method of forming electrically conductive interconnect lines and integrated circuitry
US5690749A (en) 1996-03-18 1997-11-25 Motorola, Inc. Method for removing sub-micron particles from a semiconductor wafer surface by exposing the wafer surface to clean room adhesive tape material

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6737725B2 (en) * 2000-08-31 2004-05-18 International Business Machines Corporation Multilevel interconnect structure containing air gaps and method for making
US20040084749A1 (en) * 2001-03-01 2004-05-06 Werner Pamler Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit
US7259441B2 (en) * 2001-03-01 2007-08-21 Infineon Technologies Ag Hollow structure in an integrated circuit and method for producing such a hollow structure in an integrated circuit
US20050253269A1 (en) * 2004-05-12 2005-11-17 Semiconductor Leading Edge Technologies, Inc. Semiconductor device

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