JPH02105532A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH02105532A JPH02105532A JP25847588A JP25847588A JPH02105532A JP H02105532 A JPH02105532 A JP H02105532A JP 25847588 A JP25847588 A JP 25847588A JP 25847588 A JP25847588 A JP 25847588A JP H02105532 A JPH02105532 A JP H02105532A
- Authority
- JP
- Japan
- Prior art keywords
- wiring
- high impedance
- impedance wiring
- noise
- integrated circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 10
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 abstract description 8
- 229910052782 aluminium Inorganic materials 0.000 abstract description 8
- 229910021420 polycrystalline silicon Inorganic materials 0.000 abstract description 7
- 239000010410 layer Substances 0.000 description 6
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/552—Protection against radiation, e.g. light or electromagnetic waves
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
- H01L2924/301—Electrical effects
- H01L2924/3011—Impedance
Landscapes
- Physics & Mathematics (AREA)
- Health & Medical Sciences (AREA)
- Electromagnetism (AREA)
- Toxicology (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
- Details Of Measuring And Other Instruments (AREA)
- Shielding Devices Or Components To Electric Or Magnetic Fields (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体集積回路装置に関し、特にアナログ回路
等の高インピーダンス配線のｆｉ造に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and particularly to FI construction of high impedance wiring for analog circuits and the like.
近年、デジタル回路とアナログ回路を同−ＬＳＩ上に形
成するいわゆるデジアナ混載ＬＳＩが脚光をあびている
。このデジアナ混載ＬＳＩではデジタル回路で発生する
ノイズ等のノイズの多い環境でアナログ回路の特性を満
足させる必要がある。又、Ａ／Ｄ、Ｄ／Ａ変換器等のア
ナログ回路は特性に対する要求精度が厳しくなっていく
こと、デジタル回路のスピードが速くなって来ているこ
とによって、ノイズが増えることが予想されるので、今
後盤々ノイズ対策が重大な問題となる。従来、ノイズの
影響を受けやすいアナログ系の高インピーダンス配線に
対しては、第３図（ａ）、（ｂ）に示す如く、半導体基
版４と高インピーダンス配線２との間にリンドープの多
結晶シリコン１！ｆｌ、又は、アルミ膜等から成るシー
ルド板を挿入し、これを接地電位に接続することによっ
て半導体基版からのノイズの影響を防ぐ対策がとられて
いた。このようなシールド板を設けることにより、基板
からの容量カップリングによるノイズの影響は低減され
る。In recent years, so-called digital/analog hybrid LSIs in which digital circuits and analog circuits are formed on the same LSI have been attracting attention. This digital/analog integrated LSI needs to satisfy the characteristics of an analog circuit in an environment with a lot of noise such as noise generated in a digital circuit. In addition, it is expected that noise will increase as the accuracy requirements for characteristics of analog circuits such as A/D and D/A converters become stricter, and as the speed of digital circuits becomes faster. In the future, countermeasures against noise will become a serious issue. Conventionally, for analog high-impedance wiring that is easily affected by noise, a phosphorus-doped polycrystalline wire is used between the semiconductor substrate 4 and the high-impedance wiring 2, as shown in FIGS. 3(a) and 3(b). Silicon 1! Measures have been taken to prevent the influence of noise from the semiconductor substrate by inserting a shield plate made of fl, aluminum film, or the like and connecting it to ground potential. By providing such a shield plate, the influence of noise due to capacitive coupling from the substrate is reduced.
このように、上述した従来のノイズ対策手段をとると、
半導体基版の電位が変化するに伴なう容量カップリング
による高インピーダンス配線の電位変化は、接地電位と
されたシールド板によって低減できる。しかし、横方向
の別記線からのノイズに対しては、何ら対策がなされて
いないので、従来から高インピーダンス配線の近傍には
電位変化の少ない配線しか配置できず、レイアウトに著
しい制約を与えている。In this way, if we take the conventional noise countermeasure measures mentioned above,
Changes in the potential of the high impedance wiring due to capacitive coupling due to changes in the potential of the semiconductor substrate can be reduced by the shield plate set to the ground potential. However, since no countermeasures have been taken against noise from separate lines in the horizontal direction, conventionally only wiring with small potential changes can be placed near high-impedance wiring, which places significant restrictions on layout. .
本発明の目的は、高インピーダンス配線を半導体基版の
縦方向°および横方向から取囲むようにシールドし得る
ノイズ対策手段を備えた半導体集積回路装置を提供する
ことである。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor integrated circuit device equipped with noise countermeasure means capable of surrounding and shielding high impedance wiring from the vertical and horizontal directions of a semiconductor substrate.
本発明によれば半導体集積回路装置は、半導体基版と、
前記基板上に少なくとも側面と底面が、一端を低インピ
ーダンス点に接続する導電性の物質で取囲まれシールド
されて形成される回路配線とを含んで構成される。According to the present invention, a semiconductor integrated circuit device includes a semiconductor substrate;
The circuit wiring is formed on the substrate so that at least the side surface and the bottom surface are surrounded and shielded with a conductive material, one end of which is connected to a low impedance point.
次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す高インピーダンス配線近傍の平面図およびそのＡ
−Ａ’断面図である６本実施例によれば半導体基版４と
高インピーダンス配線２との間には従来と同様にリント
−１の多結晶シリコンＮ１から成るシールド板が挿入さ
れ、さらにこの高インピーダンス配線２の両側にアルミ
導体８を設けると共に、このアルミ導体８とリンドープ
の多結晶シリコン層１とをコンタクト領域３でそれぞれ
接続することにより高インピーダンス配線２の両側面に
もシールド板が形成される。このことにより高インピー
ダンス配線２の近（Ｗに自由に他の配線を設けることが
でき、レイアウトの制約を解除することができる。以上
は高インピーダンス配線をシールドする場合に関して述
べたが本発明がノイズの影響を受けたくない配線すべて
に対して実施できることは言うまでもないことである。FIGS. 1(a) and 1(b) are a plan view of the vicinity of high impedance wiring and its A, respectively, showing an embodiment of the present invention.
-A' sectional view According to this embodiment, a shield plate made of polycrystalline silicon N1 of Lint-1 is inserted between the semiconductor substrate 4 and the high impedance wiring 2 as in the conventional case, and Shield plates are also formed on both sides of the high impedance wiring 2 by providing aluminum conductors 8 on both sides of the high impedance wiring 2 and connecting the aluminum conductors 8 and the phosphorus-doped polycrystalline silicon layer 1 through the contact regions 3. be done. As a result, other wiring can be freely provided near the high impedance wiring 2 (W), and layout constraints can be lifted. It goes without saying that this method can be applied to all wiring that is not affected by this.
第２図は本発明の他の実施例を示す高インピーダンス配
線近傍の断面図である。前実施例では、高インピーダン
ス配線２に対し底面と側面からシールドする構造を示し
たが、ＬＳＩ外部からの電磁波の影響で高インピーダン
ス配線の電位が、ゆさぶられる等の可能性に対しては対
策は未だ十分でない。本実施例によればリンドープの多
結晶シリコン層１に対し３層目のアルミ導体９が高イン
ピーダンス配線２の上部を覆うように設けられ、同じく
コンタクト領域および２層目のアルミ等導体８を介し接
地されたリンドープの多結晶シリコン層１と接続される
。これにより、高インピーダンス配線２はその底面、側
面および上部のすべてからシールド板によって囲まれる
ことにより、完全にシールドされる。従って、あらゆる
ノイズの影響をなくすことができる。FIG. 2 is a sectional view of the vicinity of high impedance wiring showing another embodiment of the present invention. In the previous embodiment, a structure was shown in which the high impedance wiring 2 is shielded from the bottom and side surfaces, but there is no countermeasure against the possibility that the potential of the high impedance wiring is fluctuated due to the influence of electromagnetic waves from outside the LSI. It's still not enough. According to this embodiment, a third layer of aluminum conductor 9 is provided on the phosphorus-doped polycrystalline silicon layer 1 so as to cover the upper part of the high impedance wiring 2, and is also connected to the contact region and the second layer of aluminum conductor 8. It is connected to a grounded phosphorus-doped polycrystalline silicon layer 1. As a result, the high impedance wiring 2 is completely shielded by being surrounded by the shield plate from all of its bottom, side and top surfaces. Therefore, the influence of all kinds of noise can be eliminated.
以上説明したごとく本発明によれば、ノイズの影響を受
けたくない配線の少なくとも底面と側面は低インピーダ
ンスのシールド板で囲まれるので、ノイズの影響を受け
ないアナログ回路をＬＳＩ化することが可能となる。As explained above, according to the present invention, at least the bottom and sides of the wiring that is not affected by noise are surrounded by a low-impedance shield plate, so it is possible to implement an analog circuit that is not affected by noise into an LSI. Become.
第１図（ａ）および（ｂ）はそれぞれ本発明の一実施例
を示す高インピーダン配線近傍の平面図およびそのＡ−
Ａ’断面図、第２図は本発明の他の実施例を示す高イン
ピーダンス配線近傍の断面図、第３図（ａ）および（ｂ
）は従来半導体集積回路装置の高インビーダン配線近傍
の平面図およびそのＢ−Ｂ’断面図である。
１・・・リンドープの多結晶シリコン層、２・・・高イ
ンピーダンス配線、３・・・コンタクト領域、４・・・
半導体基版、５・・・シリコン酸化膜、６，７・・・層
間絶縁膜、８．９・・・アルミ導体。FIGS. 1(a) and 1(b) are a plan view of the vicinity of high impedance wiring and its A-
A' sectional view, FIG. 2 is a sectional view near high impedance wiring showing another embodiment of the present invention, and FIGS. 3(a) and (b)
) is a plan view of the vicinity of a high impedance wiring of a conventional semiconductor integrated circuit device and a sectional view thereof taken along line BB'. DESCRIPTION OF SYMBOLS 1... Phosphorus-doped polycrystalline silicon layer, 2... High impedance wiring, 3... Contact region, 4...
Semiconductor substrate, 5... silicon oxide film, 6, 7... interlayer insulating film, 8.9... aluminum conductor.
Claims (1)
、一端を低インピーダンス点に接続する導電性の物質で
取囲まれシールドされて形成される回路配線とを含むこ
とを特徴とする半導体積回路装置。A semiconductor integrated circuit comprising: a semiconductor substrate; and circuit wiring formed on the substrate so that at least the side surfaces and the bottom surface are surrounded and shielded by a conductive material whose one end is connected to a low impedance point. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25847588A JPH02105532A (en) | 1988-10-14 | 1988-10-14 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP25847588A JPH02105532A (en) | 1988-10-14 | 1988-10-14 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02105532A true JPH02105532A (en) | 1990-04-18 |
Family
ID=17320737
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP25847588A Pending JPH02105532A (en) | 1988-10-14 | 1988-10-14 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02105532A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001093329A2 (en) * | 2000-05-30 | 2001-12-06 | Infineon Technologies Ag | Faraday cage for an integrated circuit |
| WO2002050908A2 (en) * | 2000-12-20 | 2002-06-27 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| JP2014022414A (en) * | 2012-07-12 | 2014-02-03 | Mitsumi Electric Co Ltd | Semiconductor integrated circuit |
| WO2014132311A1 (en) * | 2013-02-28 | 2014-09-04 | パナソニック株式会社 | Semiconductor device |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151847A (en) * | 1984-08-22 | 1986-03-14 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| JPS63268257A (en) * | 1987-04-27 | 1988-11-04 | インターナシヨナル・ビジネス・マシーンズ・コーポレーション | Shielded transmission line structure |
| JPH022623A (en) * | 1988-06-17 | 1990-01-08 | Hitachi Ltd | Semiconductor device |
| JPH0265240A (en) * | 1988-08-31 | 1990-03-05 | Seiko Epson Corp | Semiconductor integrated device |
-
1988
- 1988-10-14 JP JP25847588A patent/JPH02105532A/en active Pending
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6151847A (en) * | 1984-08-22 | 1986-03-14 | Hitachi Micro Comput Eng Ltd | Semiconductor device |
| JPS63268257A (en) * | 1987-04-27 | 1988-11-04 | インターナシヨナル・ビジネス・マシーンズ・コーポレーション | Shielded transmission line structure |
| JPH022623A (en) * | 1988-06-17 | 1990-01-08 | Hitachi Ltd | Semiconductor device |
| JPH0265240A (en) * | 1988-08-31 | 1990-03-05 | Seiko Epson Corp | Semiconductor integrated device |
Cited By (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001093329A2 (en) * | 2000-05-30 | 2001-12-06 | Infineon Technologies Ag | Faraday cage for an integrated circuit |
| WO2001093329A3 (en) * | 2000-05-30 | 2002-06-06 | Infineon Technologies Ag | Faraday cage for an integrated circuit |
| WO2002050908A2 (en) * | 2000-12-20 | 2002-06-27 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| WO2002050908A3 (en) * | 2000-12-20 | 2003-03-13 | Honeywell Int Inc | Gate length control for semiconductor chip design |
| US6674108B2 (en) | 2000-12-20 | 2004-01-06 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| US6939758B2 (en) | 2000-12-20 | 2005-09-06 | Honeywell International Inc. | Gate length control for semiconductor chip design |
| JP2014022414A (en) * | 2012-07-12 | 2014-02-03 | Mitsumi Electric Co Ltd | Semiconductor integrated circuit |
| WO2014132311A1 (en) * | 2013-02-28 | 2014-09-04 | パナソニック株式会社 | Semiconductor device |
| JP2014167954A (en) * | 2013-02-28 | 2014-09-11 | Panasonic Corp | Semiconductor device |
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