JPH0237734A - Mounting method for ic chip - Google Patents

Mounting method for ic chip

Info

Publication number
JPH0237734A
JPH0237734A JP18931588A JP18931588A JPH0237734A JP H0237734 A JPH0237734 A JP H0237734A JP 18931588 A JP18931588 A JP 18931588A JP 18931588 A JP18931588 A JP 18931588A JP H0237734 A JPH0237734 A JP H0237734A
Authority
JP
Japan
Prior art keywords
chip
electrode
pattern
printed
signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP18931588A
Other languages
Japanese (ja)
Other versions
JP2615149B2 (en
Inventor
Akira Mase
晃 間瀬
Toshimitsu Konuma
利光 小沼
Shunpei Yamazaki
舜平 山崎
Takeshi Oka
毅 岡
Hiroshi Yamazaki
博史 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Semiconductor Energy Laboratory Co Ltd
Omron Corp
Original Assignee
Semiconductor Energy Laboratory Co Ltd
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Semiconductor Energy Laboratory Co Ltd, Omron Tateisi Electronics Co filed Critical Semiconductor Energy Laboratory Co Ltd
Priority to JP18931588A priority Critical patent/JP2615149B2/en
Publication of JPH0237734A publication Critical patent/JPH0237734A/en
Application granted granted Critical
Publication of JP2615149B2 publication Critical patent/JP2615149B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Abstract

PURPOSE:To improve production yield of product and reduce production cost of the product by allowing an IC bump to contact the signal I/O part of a circuit on a board to perform electrical connection after aligning the height of the signal I/O part of the circuit on the board. CONSTITUTION:A paste with a conductive particle on a board 1 is printed on an electrode or a lead pattern and at least an IC chip 5 of the printed pattern is subject to press treatment for the part to be in contact for aligning the height. Then, heat treatment is performed to the printed pattern, the electrode or the lead is completed, and a pad of the signal I/O part of the lead and the bump of the signal I/O part of the IC chip 5 are allowed to be connected electrically. It allows the height of an electrode pattern 2 formed by the printing method can be made uniform and a complete conduction can be obtained without any improper conductive part on mounting the IC chip 5. Also, resistance of the electrode can be reduced by the press treatment.

Description

【発明の詳細な説明】 r本発明の利用分野」 この発明は低コスト化を図るために、プリント基板、硝
子基板等の絶縁基板もしくは絶縁性表面を有する基板上
に電気配線を精密印刷する方法を用いたICチップの実
装方法。
[Detailed Description of the Invention] [Field of Application of the Present Invention] This invention provides a method for precisely printing electrical wiring on an insulating substrate such as a printed circuit board or a glass substrate or a substrate having an insulating surface in order to reduce costs. A method of mounting an IC chip using.

「従来の技術」 従来、プリント基板上に電気配線を形成するにはガラス
エポキシ等の絶縁基板上に銅箔を貼り付け、公知である
フォトリソグラフィー工程を用いて、ウェットエツチン
グ法により電気配線を形成する手法がとられていた。
"Conventional technology" Conventionally, to form electrical wiring on a printed circuit board, copper foil is pasted on an insulating substrate such as glass epoxy, and electrical wiring is formed by wet etching using a well-known photolithography process. A method was taken to do so.

またサーマルヘッド等の装置の場合においては絶縁体で
あるセラミック基板上にAuを中心とする導電金属を基
板表面全体にイオンブレーティング法等により蒸着し、
プリント基板の場合と同様にフォトリソグラフィー法を
用いて、ウェットエツチング法により電気配線を形成す
る手法が採られていた。
In addition, in the case of devices such as thermal heads, a conductive metal, mainly Au, is deposited on the entire surface of the substrate by ion blating or the like on a ceramic substrate, which is an insulator.
As in the case of printed circuit boards, a method was adopted in which electrical wiring was formed using photolithography and wet etching.

プリント基板等において、半導体素子の端子を入れる穴
と穴とのピン間隔は0.1インチ(2,45mm)で、
この間に3本以上の電気配線回路を描く高密度プリント
配線板のパターン形成はもっばらフォトリソグラフィー
法が用いられていた。プリント配線板にドライフィルム
を貼り、この上に露光、現像という写真技術で配線パタ
ーンを描いて、不要部分を溶剤で溶かしてパターンを形
成する方法が採られてきた。
In printed circuit boards, etc., the pin spacing between the holes for inserting the terminals of semiconductor elements is 0.1 inch (2.45 mm).
During this period, photolithography was used mostly to form patterns for high-density printed wiring boards in which three or more electrical wiring circuits were drawn. A method has been adopted in which a dry film is applied to a printed wiring board, a wiring pattern is drawn on it using a photographic technique of exposure and development, and the unnecessary portions are dissolved with a solvent to form the pattern.

この方法に使用される銅箔およびドライフィルム、現像
液等の材料費が高価であるとともに、露光装置も高価で
あるために、製造原価をあげる一因となっていた。
The materials used in this method, such as copper foil, dry film, and developer, are expensive, and the exposure equipment is also expensive, which is one of the causes of increased manufacturing costs.

さらにフォトリソグラフィー法は、その工程が複雑であ
りまた所要時間も相当必要であり、この方法自身がコス
ト高につながっていた。
Furthermore, the photolithography process is complicated and requires a considerable amount of time, leading to high costs.

またサーマルヘッド、イメージセンサ、液晶表示装置の
電極パターン形成時においても同様にフォトリソグラフ
ィー工程が用いられ、各々の装置の製造原価をあげてい
た。
Furthermore, photolithography processes are similarly used when forming electrode patterns for thermal heads, image sensors, and liquid crystal display devices, increasing the manufacturing cost of each device.

かかる問題を解決するため、印刷法により直接基板上に
形成することで、従来法で必要であった配線のベースと
なる銅箔、フォトレジスト、現像液等の材料費およびそ
の工程にかかわる時間および人件費を省くことができ、
コストの低減を行う方法が提案されている。
In order to solve this problem, by forming the wiring directly on the substrate using a printing method, we can reduce the cost of materials such as copper foil, photoresist, developer, etc. that are the base of the wiring, and the time and time involved in the process, which were required in the conventional method. You can save on labor costs,
Methods have been proposed to reduce costs.

ガラス、ガラスエポキシ、セラミック等の絶縁基板上ま
たは既に配線の設けられた基板上に絶縁層を形成したそ
の上に金属粉または合金属粉を含む導電性印刷用インク
を印刷法により1〜20μm程度の膜厚を有するパター
ンの印刷を行うものである。
An insulating layer is formed on an insulating substrate such as glass, glass epoxy, ceramic, etc. or on a substrate already provided with wiring, and then a conductive printing ink containing metal powder or alloy metal powder is applied to a thickness of about 1 to 20 μm by a printing method. The pattern is printed with a film thickness of .

このような手法により基板上に直接描かれた回路上に電
子装置駆動用のICを実装するにはC0B(チップオン
ボード)技術が知られており、このCOBにおいても従
来はICの電極パッドと基板上の回路の信号入出力部と
を金属細線を用いて1本づつ接続を行っていた。
COB (chip-on-board) technology is known for mounting ICs for driving electronic devices on circuits drawn directly on the substrate using this method, and in this COB, conventionally, IC electrode pads and The signal input/output sections of the circuit on the board were connected one by one using thin metal wires.

しかし生産性及びコスト面などの要求よりICパッドに
バンブを設は基板上の回路の信号入出力部とを直接接触
させるフリノブチップ法が開発されている。
However, due to demands for productivity and cost, a fly-knob chip method has been developed in which bumps are provided on IC pads and are brought into direct contact with signal input/output sections of circuits on a substrate.

この場合ICバンプと基板上の回路の信号入出力部との
接触が完全になされず、導通不良を起こし製品の歩留り
低下をおこすという問題が生じていた。
In this case, the IC bump and the signal input/output section of the circuit on the board are not completely contacted, causing a problem of poor conduction and lowering the yield of the product.

本則発明はその構成として基板上に直接印刷法等に描か
れた電極又はリード等による回路の少なくともIcのバ
ンプと接触する部分に対し、プレス処理を施すことによ
り基板上の回路の信号入出力部の高さを揃えた後IC八
へプを基板上の回路の信号入出力部に接触させ電気的接
続を行うことにより前述の問題を解決し、製品の製造歩
留りを向上せしめ製品の製造コストを下げるという効果
を有するものであります。
The present invention has a structure in which a signal input/output section of a circuit on a substrate is formed by applying a press process to at least a portion of the circuit made of electrodes or leads drawn by a direct printing method or the like on the substrate that contacts the bumps of Ic. After aligning the heights of the ICs, the IC head is brought into contact with the signal input/output section of the circuit on the board to make an electrical connection, which solves the above problem, improves the manufacturing yield of the product, and reduces the manufacturing cost of the product. It has the effect of lowering

以下に実施例により本発明を説明する。The present invention will be explained below with reference to Examples.

「実施例」 導電性印刷インクとして市販されているポリマー型銅ペ
ーストを用いて絶縁性表面を有する基板上に所定の電極
又はリードのパターン(2)を公知のスクリーン印刷法
により印刷した。
"Example" A predetermined electrode or lead pattern (2) was printed on a substrate having an insulating surface using a polymer-type copper paste commercially available as a conductive printing ink by a known screen printing method.

本実施例にて使用したポリマー型銅ペーストは三井金属
鉱業製で商品名S−5000として市販されており5μ
I程度の粒子径を有する銅粒子と、エポキシ樹脂と有機
溶剤とから構成されている。
The polymer type copper paste used in this example is manufactured by Mitsui Mining & Co., Ltd. and is commercially available under the trade name S-5000.
It is composed of copper particles having a particle size of approximately I, an epoxy resin, and an organic solvent.

このような導電性印刷ペーストを2QO〜400メツシ
ユのスクリーンを用いて所定のパターン(2)に印刷す
る。この場合印刷パターンの電極又はリドの巾は最小4
0μm最大100μm程度でありスクリーンメツシュの
空いている間隔が20〜40μm、であり、当然印刷さ
れたパターン(2)にはメツシュに相当する高低差が存
在する。
This conductive printing paste is printed in a predetermined pattern (2) using a 2QO to 400 mesh screen. In this case, the width of the printed pattern electrode or lid is at least 4
The width of the screen mesh is about 0 μm and the maximum is about 100 μm, and the gap between the screen meshes is 20 to 40 μm, and naturally there is a difference in height corresponding to the mesh in the printed pattern (2).

今、厚さ20μm巾40μmで100本の直線状の電極
の印刷を行った場合、最大の厚さ27μm最小の厚さ1
3μmであり、1本の電極間においても高低差が存在し
複数本の電極間においても高低差が存在していた。その
様子を第2図(a)に示す。
Now, if we print 100 linear electrodes with a thickness of 20 μm and a width of 40 μm, the maximum thickness is 27 μm and the minimum thickness is 1
The height difference was 3 μm, and there was a height difference between one electrode as well as between a plurality of electrodes. The situation is shown in FIG. 2(a).

このように約15μmも高低差の存在する電極パターン
に対してICチップを接触させて完全な導通を得ること
は当然ながら不可能であった。
Naturally, it was impossible to obtain complete conduction by bringing an IC chip into contact with an electrode pattern having a height difference of about 15 μm.

そのため本実施ではまず第1図に示す電極又はリードパ
ターン(2)を絶縁性表面を有する基板(1)上に前述
の導電性ペーストを用いて印刷した。第1図はその一部
しか示されていないが80本の電極パターンを印刷した
。この状態では前述の如く電極又はリードパターンは高
低差が存在し、例えば電極(33)の高さは15μmで
あり、電極(3)の高さは29μmで80本の電極の平
均は19.5μmであった。
Therefore, in this embodiment, first, the electrode or lead pattern (2) shown in FIG. 1 was printed on the substrate (1) having an insulating surface using the above-mentioned conductive paste. Although only a portion of which is shown in FIG. 1, 80 electrode patterns were printed. In this state, as mentioned above, there are height differences in the electrodes or lead patterns; for example, the height of the electrode (33) is 15 μm, the height of the electrode (3) is 29 μm, and the average of the 80 electrodes is 19.5 μm. Met.

次にこの印刷したパターンに対し、予備の熱処理を行う
。すなわち導電性ペーストが完全に固形化しない程度に
熱を加え印刷されたパターン中に存在する有機溶剤の一
部を飛ばす処理を行った。
Next, this printed pattern is subjected to preliminary heat treatment. That is, heat was applied to the conductive paste to such an extent that it did not completely solidify, and a portion of the organic solvent present in the printed pattern was blown off.

実際には60°Cで約5分の予備の熱処理を行った。Actually, preliminary heat treatment was performed at 60°C for about 5 minutes.

次にこの電極に対し、プレス処理を施した。本実施例の
場合ロールプレスを用いて面圧力20kg/c+flの
圧力で、この予備の熱処理が施された印刷パターンにプ
レス処理を行った。この後180°C30分間の熱処理
を施し電極パターンの完全固形化を行った。この時に電
極(33)の高さは14μmとなり、電極(3)の高さ
は20μmとなって、80本の電極の平均の高さは18
.0μmであった。プレス後の電極パターンの様子を第
2図[有])に示す。
Next, this electrode was subjected to a press treatment. In the case of this example, the printing pattern subjected to the preliminary heat treatment was subjected to press treatment using a roll press at a surface pressure of 20 kg/c+fl. Thereafter, heat treatment was performed at 180° C. for 30 minutes to completely solidify the electrode pattern. At this time, the height of the electrode (33) is 14 μm, the height of the electrode (3) is 20 μm, and the average height of the 80 electrodes is 18 μm.
.. It was 0 μm. The state of the electrode pattern after pressing is shown in FIG.

このプレス処理は基板(1)上に形成された電極パター
ンのうちのICチップのバンプと接触する部分だけでよ
いが電極パターン全体又はほぼ全体を行うとプレス処理
により形成されたパターン中に存在する銅粒子同志の接
触面積が増し、電極の導電性が向上するという別の特徴
を有する。
This pressing process only needs to be applied to the part of the electrode pattern formed on the substrate (1) that comes into contact with the bumps of the IC chip, but if the entire or almost the entire electrode pattern is subjected to the pressing process, some parts of the electrode pattern formed on the substrate (1) will be present in the pattern formed by the pressing process. Another feature is that the contact area between the copper particles increases and the conductivity of the electrode improves.

次にICチップ(5)のバンプ(6)と基板上のパター
ン(2)の信号入出力部との位置合わせを行い両者を接
触させる。
Next, the bumps (6) of the IC chip (5) and the signal input/output portion of the pattern (2) on the substrate are aligned and brought into contact with each other.

この時150°C程度に加熱しながら紫外光硬化接着剤
(4)をICチップ(5)に塗布し、紫外光を照射して
接着した後、加熱を中止してICチップの基板上への実
装を終了する。この時の様子を第3図に示す。
At this time, apply the ultraviolet light curing adhesive (4) to the IC chip (5) while heating it to about 150°C, and after irradiating it with ultraviolet light to bond it, stop heating and place the IC chip on the substrate. Finish the implementation. The situation at this time is shown in Figure 3.

ICチップ(5)を基板上に接着する接着剤(4)は温
度変化に伴って体積膨張収縮を行う。本実施例では加熱
した状態すなわち体積が膨張した状態で硬化させたので
温度を下げて行っても接着剤は体積収縮しICチップ(
5)を基板に押しつける力が増すのみで、温度サイクル
試験等に十分耐えるという特徴を持っている。
The adhesive (4) that adheres the IC chip (5) to the substrate expands and contracts in volume as the temperature changes. In this example, the adhesive was cured in a heated state, that is, in a state where the volume expanded, so even if the temperature was lowered, the volume of the adhesive would shrink and the IC chip (
5) It has the characteristic that it can withstand temperature cycle tests, etc. simply by increasing the force that presses it against the board.

比較のためにプレス処理を行わない印刷パターンにIC
チップを実装し、その電気的な接続の特性を調べた結果
を以下の表に示す。
For comparison, IC was applied to the printed pattern without press processing.
The table below shows the results of mounting the chip and examining its electrical connection characteristics.

このようにプレス処理が施された本発明方法はすべての
接続部分が良導通性を示し、接続部の歩留りは100%
とすることができた。
In the method of the present invention in which press processing is performed in this way, all the connected parts show good conductivity, and the yield of the connected parts is 100%.
I was able to do this.

本実施例ではプレス後の電極の高さの最高と最低の差が
6μmであった。本来この高低差0が最も良い結果を示
すと考えられるが本発明者らによると高低差が8μmで
も接続可能であることが判明している。
In this example, the difference between the highest and lowest electrode heights after pressing was 6 μm. Originally, it is thought that this height difference of 0 would give the best results, but the inventors have found that connection is possible even with a height difference of 8 μm.

〔効果] 本発明方法により印刷法にて形成された電極パターンの
高さを揃えて形成することができ、ICチップの実装時
の不良導通箇所が全(なく完全な導通が得られた。
[Effects] According to the method of the present invention, the electrode patterns formed by the printing method could be formed with the same height, and complete conduction was obtained with no defective conduction points during the mounting of the IC chip.

又、プレス処理により電極の抵抗値が下がるという特徴
も有する。
Another feature is that the resistance value of the electrode is reduced by the press treatment.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図及び第2図は本発明方法による電極の印刷パター
ンを示す。 第3図はICチップ実装の様子を示す。 ■90.基板     590.ICCタンプ66.電
極パターン 40.、接着剤 ^−一 弔 図
1 and 2 show printed patterns of electrodes according to the method of the invention. FIG. 3 shows how the IC chip is mounted. ■90. Substrate 590. ICC stamp 66. Electrode pattern 40. , Adhesive ^-One Funeral Picture

Claims (2)

【特許請求の範囲】[Claims] 1.絶縁製表面を有する基板上に導電性粒子を有するペ
ーストをスクリーン印刷法により電極又はリードのパタ
ーンに印刷する工程と前記印刷パターンの少なくともI
Cチップと接触する部分に対しプレス処理を施し高さを
揃える工程と前記印刷パターンに対し熱処理を施し電極
又はリードを完成する工程と前記電極又はリードの信号
入出力部のパッドとICチップの信号入出力部のバンプ
とを対抗させ電気的に接続させる工程とを有することを
特徴とするICチップの実装方法。
1. a step of printing a paste having conductive particles on a substrate having an insulating surface into a pattern of electrodes or leads by screen printing; and at least I of the printed pattern.
A step of applying press treatment to the part that contacts the C chip to make the height uniform; a step of applying heat treatment to the printed pattern to complete the electrode or lead; and a step of applying a signal input/output part pad of the electrode or lead to the signal of the IC chip. 1. A method for mounting an IC chip, comprising the step of opposing and electrically connecting bumps of an input/output section.
2.特許請求の範囲第1項において前記印刷パターンの
少なくともICチップと接触する部分に対しプレス処理
を施し電極又はリードの高さを揃える工程に先立って前
記印刷パターンに予備の熱処理を施すことを特徴とする
ICチップの実装方法。
2. Claim 1 is characterized in that the printed pattern is subjected to preliminary heat treatment prior to the step of applying a press treatment to at least a portion of the printed pattern that contacts an IC chip to align the heights of the electrodes or leads. How to mount an IC chip.
JP18931588A 1988-07-27 1988-07-27 IC chip mounting method Expired - Lifetime JP2615149B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18931588A JP2615149B2 (en) 1988-07-27 1988-07-27 IC chip mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18931588A JP2615149B2 (en) 1988-07-27 1988-07-27 IC chip mounting method

Publications (2)

Publication Number Publication Date
JPH0237734A true JPH0237734A (en) 1990-02-07
JP2615149B2 JP2615149B2 (en) 1997-05-28

Family

ID=16239300

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18931588A Expired - Lifetime JP2615149B2 (en) 1988-07-27 1988-07-27 IC chip mounting method

Country Status (1)

Country Link
JP (1) JP2615149B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121062A (en) * 1993-08-13 2000-09-19 Fujitsu Limited Process of fabricating semiconductor unit employing bumps to bond two components
JP2007305741A (en) * 2006-04-10 2007-11-22 Murata Mfg Co Ltd Ceramic multilayer board, and its manufacturing method

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6121062A (en) * 1993-08-13 2000-09-19 Fujitsu Limited Process of fabricating semiconductor unit employing bumps to bond two components
JP2007305741A (en) * 2006-04-10 2007-11-22 Murata Mfg Co Ltd Ceramic multilayer board, and its manufacturing method

Also Published As

Publication number Publication date
JP2615149B2 (en) 1997-05-28

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