JPH02371A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To obtain a semiconductor storage circuit device having high dielectric strength, by utilizing as a semiconductor non-volatile storage element an MNOS including a gate insulating film of two-layer structure consisting of an extremely thin silicon oxide film and a relatively thick silicon nitride film. CONSTITUTION:An SiO2 film 88 of below 10nm is covered with an Si3N4 film 90, part of which in turn is covered with a polysilicon layer 91. By using this polysilicon layer as a mask, a dopant for forming source and drain is introduced into the surface of the substrate. Then, by using the Si3N4 film as a mask, a relatively thick oxide film 102 is formed. Further, by using the oxide film 102 as a mask, the Si3N4 film 90 is partially etched off and oxide films 104 and 105 are formed on the surface of the source and drain regions. In this manner, an MNOS element and an MOS element are produced on the same semiconductor substrate while the Si3N4 film 90 is left only under the gate of the MNOS element, so that the gate dielectric strength of the two elements is improved.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit device, and particularly to a method for manufacturing a semiconductor device such as a semiconductor memory circuit device using a semiconductor nonvolatile memory element in which stored information can be written and erased.

2. Description of the Related Art As a semiconductor nonvolatile memory element, an insulating gout electric field (hereinafter referred to as blank space) effect transistor is known, which utilizes a trap in a gate insulating film or a floating gate. In this type of insulated gate field effect transistor, due to the tunnel effect,
Alternatively, when hot carriers generated by avalanche breakdown inject traps or floating charges in the gate insulating film, the threshold voltage changes from one stable value to the other stable value. . The state of one of the above threshold voltages is made to correspond, for example, to the binary signal 0, and the state of the other threshold voltage is made to correspond to the binary signal 1.

The above charges are removed by a suitable method. Is possible.

Therefore, the above type of insulated gate field effect transistor has the advantage that it can be used as a nonvolatile memory element in which stored information can be written and erased.

A plurality of the above-mentioned semiconductor nonvolatile memory elements are regularly arranged on a semiconductor substrate, and are selected for reading or writing stored information.

The above-mentioned semiconductor nonvolatile memory element requires a high-voltage, high-level signal that reaches several times the signal level when writing, for example, compared to the signal level required for reading stored information.

However, since the signal repp may be limited depending on the characteristics of the circuit elements, the semiconductor memory circuit device requires a circuit device that takes into consideration the above-mentioned high level signals.

In addition, since the overall configuration of a semiconductor memory circuit device becomes complicated due to the use of the giant single-path device that processes the above-mentioned high-level signals, it is necessary to prevent the semiconductor substrate used from increasing in size.
In addition, consideration must be given to ensure that performance such as operating speed is not impaired.

On the other hand, power-driven semiconductor circuit devices are required to be realized mainly using insulated gate field effect transistors, but are also required to use some bibolar transistors for zero-path configuration and functional improvement. Therefore, it is required to realize such a semiconductor circuit device as a so-called semiconductor integrated circuit device formed on a single semiconductor substrate. It is necessary to improve the efficiency of the manufacturing process for semiconductor integrated circuit devices, which are expensive to manufacture.Therefore, it is required to realize the above-mentioned electronic circuit with a simple manufacturing process.

Therefore, one object of the present invention is to provide a semiconductor memory circuit device that uses a non-volatile memory element made of a conductive material and has a high operating speed.

Another object of the present invention is to provide a semiconductor memory circuit device that uses semiconductor nonvolatile memory elements and can be miniaturized.

Another object of the present invention is to provide a semiconductor memory circuit device in which individual circuit devices are arranged at desired positions on a semiconductor substrate.

Another object of the present invention is to provide a novel semiconductor memory using a semiconductor non-volatile memory element in which stored information can be written and erased electrically, such as an insulated gate field effect transistor that utilizes a trough of a gate insulating film. The purpose of the present invention is to provide a circuit device.

Another object of the present invention is to provide a semiconductor memory circuit device having a structure that achieves a semiconductor nonvolatile memory element in which storage information can be electrically written and erased.

Another object of the invention is to provide a circuit device suitable for processing high voltage signals.

Another object of the present invention is to provide a circuit device that is less likely to break down.

Another object of the invention is to provide a novel circuit device including a bipolar transistor and an insulated gate field effect transistor.

Still another object of the present invention is to provide a method of manufacturing a semiconductor memory circuit device for realizing the various electronic circuit devices described above.

The various objects and configurations of the present invention described above will become clear from the following detailed description and accompanying drawings.

Hereinafter, this invention will be explained in detail based on examples.

Although not particularly limited, in the following embodiments, the semiconductor non-volatile memory element is an insulating gate insulating film having a double-layered gate insulating film with an extremely thin silinitrided and relatively thick silicon nitride film (N1tr1de). A K-valve effect transistor (hereinafter referred to as MNO8) is used. With respect to this MNOS, not only storage information can be written but also erased electrically.

FIG. 12 shows a cross-sectional view of the MNOS.

In the figure, an NFI source region 2 and a drain region 3 are formed on the surface of a p-type silicon region 1 to be separated from each other, and on the surface of a p-type silicon region l between the source/drain/regions 2 and 3, for example, a thick 20X silicone cough 4
A gate 111 made of n-type polycrystalline silicon is inserted through a gate insulating film made of a silicon nitride film 5 having a thickness of 500×.
poles are formed. The above p′! The J1 silicon region 1 constitutes the basic gate region of the MNOS.

In an erased state or a state in which no stored information is stored, the gate voltage VG vs. drain current ID characteristic of the MNOS is, for example, as shown in curve A in Figure 13, and the voltage at the threshold fall is 4 volts. It is a negative voltage (hereinafter referred to as -4V in 5).

In order to fill in or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

In a write operation, the substrate gate 1 has e.g.
A circuit ground potential of 0 is applied, and a high voltage of, for example, +25V is applied to the gate 6.

A low voltage of S:OV or a high voltage of +20V is applied to the source region 2 and drain region 3 depending on the information to be written.

Silicon region 1 between source region 2 and drain region 3
A channel 7 is induced on the surface in response to the high positive voltage of the gate 6. The potential of this channel 7 becomes equal to the potentials of the source region 2 and drain region 3.

When a voltage of 0 is applied to the source region 2 and drain region 3 as described above, a high electric field corresponding to the high voltage of the gate 6 acts on the gate-insulated Ni1llK.

As a result, electrons as intermediate electrons are injected from the channel 7 into the gate insulating film due to a tunneling phenomenon. MNO
The VG-ID characteristics of S change from BK to curve 13 in Figure 13. The threshold voltage changes from the above-mentioned 14V to, for example, +IV.

+20 as above for source region 2 and drain region 3
When V is applied, the potential difference between gate 6 and channel 7 is reduced to a few volts. Such a low potential difference is insufficient to cause electron injection by tunneling. Therefore, the characteristics of MNOS do not change from the song mA in FIG. 13.

In a semiconductor memory circuit device, a plurality of MNOSs are combined into one digit playback. In the above write operation, the above voltage is applied to the selected MNOS. yO■ for the gate of MNOS that is considered unselected
, or a high voltage such as the aforementioned +20V is applied to the source and drain regions.

Erasing of stored information is performed by applying a high electric field to the gate insulating film in the opposite direction to the electric field in the above-mentioned dipping. A tunneling phenomenon occurs due to this high electric field in the opposite direction, and holes as carriers flow into the gate insulating film. The electrons injected during the writing are neutralized by the holes, and as a result, the characteristics of MNO5 return from song #B to song aA in FIG. 13 again.

According to this embodiment, for the above-mentioned erasure, instead of applying a negative high voltage to the gate 6 while applying 0 to the base gate 1, for example, OV is applied to the gate 6 as will be clearer from later. The structure is such that a positive high voltage such as +25 V is applied to the base gate 1 while applying the voltage. By applying a positive high voltage to the base gate 1 as described above, the circuit configuration for applying a high voltage to the gate 6 can be simplified. In addition, high voltages of the same polarity can be used for writing and erasing.
As a result, the number of external terminals of the semiconductor memory circuit device and the number of power supplies for driving the semiconductor memory circuit device can be reduced.

Since the characteristics of the MNOS are 10,000 for either song mA or B in Figure 13 above, reading the stored information in the MNOS is as follows:
For example, this is done by detecting the conduction state between the source and drain when the gate voltage VG is Ov. In order to be able to select one of the plurality of MNOS coupled to one digit w by a single polarity (1),
The unit memory g (hereinafter referred to as memory cell) is the 14th
As shown in the equivalent circuit in the figure, MNO8QI and an insulated gate field effect transistor for switching (hereinafter referred to as MISFET for switching) Q connected in series with MNO8QI.
It consists of 2. When starting out, the gate voltage of MNO8Q1 is maintained at Ov, and the switch MISF
The gate voltage of E T is Ov or +5 depending on the selection signal.
It is assumed to be a positive voltage such as v.

FIG. 1 shows a circuit of a semiconductor memory circuit device according to an embodiment.

The memory circuit of this embodiment includes circuits that form relatively low-voltage signals such as an X decoder, Contains.

Although not particularly limited, a low voltage source of +5V is supplied to the power supply terminal VCC for the circuit forming the above-mentioned low voltage signal. Depending on the power supply voltage, the high level of the low voltage signal is set to r+sv, and the low level is set to Ov, which is the ground potential of the y circuit.

A high voltage terminal vPP is provided in the circuit device for circuits such as the above-mentioned filling circuit and erasing circuit. This high voltage terminal v
A high voltage such as y+25V is supplied to PP when the circuit device* performs a write operation and an erase operation. Depending on the above-mentioned high voltage, the high level of each high voltage issue is set to +25V or +20V, and the low level is set to WQV.

In FIG. 1, MA is a memory array and includes memory cells MSil to MS22 arranged in a matrix.

The gates of the switch MISFETs Q2 of the memory cells MSII and M812 arranged in the same row are commonly connected to the second word IWWll,
The gates of QI are commonly connected to the second word line.
Similarly, other memory cells MS21 arranged in the same row
．． M I S F E T and M for MS22 switches
The NOS gates are connected to the first word W21. It is commonly connected to the second word wall W22.

The drain of MI 5FETQ2 for switching of memory cells MSII and MS21 arranged in the same column is a disk)
The source of the MNOS is connected to the line D1 in common, and the source of the MNOS is connected to the reference potential r.
Commonly connected to WED1.

A memory cell MS12 arranged in another same column on the same line,
MS22 switch MISFET drain and MN
The OS sources each have a digit tolerance of 02. Reference potential~
Commonly connected to ED2.

According to this example, positive lWI′N for the ik body gate,
Since the configuration is such that the information stored in the MNOS is erased by applying pressure, the semiconductor region that forms the memory cell is electrically isolated from the semiconductor region that forms the X decoder and peripheral circuits such as the X decoder, which will be explained next. be done. As will be explained later, the above semiconductor region is subjected to MH from, for example, a p-type well region formed on the surface of an n-type semiconductor substrate.

For the above-mentioned erasure, individual memory cells can be formed in independent well regions, or memory cells arranged in the same row or column can be formed in a common well region. Now, the entire memory cells, ie, the memory array MA, are formed in one common well region.

In FIG. 1, the well region Km is connected to the well region Km as a common substrate gate of the memory play MA.

The first word iw11. W21 are connected to the output terminals of the X decoders MDI and XD2, respectively, and the second word lines W12. W22 is connected to the output terminals of the input circuits WAl and WA2.

As shown in the figure, the X decoder It consists of enhancement mMIsFETs Q4 to Q6 whose gates receive non-inverted outputs or inverted outputs from address buffers 7BO to B6, essentially forming a NOR circuit. The X decoder XDI outputs at least one of the addresses %laO to a6 when not selected (
Due to the high level of the ff signal, almost OV is applied to the word line Wit.
When selected, all signals at the address inputs [aO to a6 become low level, and output a high level signal of X5V.

The X decoder XD2 has the same configuration as the X decoder MDI described above except that the connected address input layer is different.

In FIG. 1, a depletion type MI 5FET such as MISFETQ3 is shown with a different symbol from an enhancement type MISFET.

The input circuit WAI is the first word + iiA W 11
and the output terminal (second word solution W12) are connected in series between MISFETQI5. MI 5FE connected between Q16 and the above output terminal and the ``Ilf source terminal VPP to which the above +25V voltage is applied during writing and erasing.
TQI 9 and MISFET QI7゜Q18 connected in series between the above output terminal and the ground terminal. and erase system N line vpK connection, and also MISFE
The gates of TQI 6 and Q18 are connected to the power supply terminal VCCK.

By the control circuit CRL having a configuration that will be explained later, the 1g of the write control #pure Wl is set to the low level of yOv, and the signal under the control line v is set to the low level of
It is considered to be a high level of 5V. Therefore MISFETQ
I5 is in the off state, whereas MISFETQI
8 is in the on state. Output terminal (second word ffMW1
2) is connected to the ground terminal of the circuit via series-connected MISFETs Q17 and Q18, and therefore XOV
be made into

In the write operation, a high voltage of +25V is applied to the ItM terminal VPP, and the write control -Wl is applied to the MISFE
A high level signal of y+5V is applied to turn on TQI5, and MI5FE is applied to control #jvi11.
The i= sign of yOv is added to 5 to turn TQI 8 off.

On state of MISFETQI5 above and MISFETQ
Due to the OFF state of I8, the signal level of the second word helix W12 becomes K so that it is determined according to the 1g level of the first word #W11.

That is, if all of the driving MISFETs Q4 to Q6 of the X decoder MDI are turned off so as to select the first word forest Wll, then the MISFET QI6
．． Current paths of Q15 and the driving MISFETs Q4 to Q6 are not configured.

Therefore, +25V of the S: power supply terminal VPP appears on the second word line W12 via the MISFET QI9. That is, corresponding to the voltage of y+5V being applied to the selected first word ``Ume'', the voltage of r+25V is applied to the selected word ``Gaku''.

If the first word mwtt is not selected, that is, if at least one of the driving MISFETs Q4 to Q6 of the X decoder
6. Q15 and the above drive MISFETs Q4 to Q6
A current path is formed to connect the output terminal (second word line W12) via the current path. As a result, the above output terminal is
It is made into v.

In the above write circuit ＼■A1, a steady K is applied to the gate.
[[MISf'ET receiving pressure V CC Q16, Q17
The high voltage signal applied to the second word line W12 is MISF
Used to prevent being limited by breakage of ETQI 5 or Q18.

That is, for example, if MISFETQ17 is omitted,
2nd ward Mori W1 to drain D of MI 8FETQ18
2 high voltage (+25V) will be applied. As mentioned above, the low voltage rov is applied to the gate of MISFETQ18 from the controller vp, so this M
The depletion layer that should extend around the drain junction of ISFET QlB will be limited in the vicinity of the gate by the low voltage of this gate. As a result, MISFETQ
The drain junction of 18 will break down at relatively low voltages.

If MISFETQI7 is provided as shown, MISFET
What is the voltage applied to the drain of ETQI8? lI voltage VC
C to MISFETQI l) Clamped to a voltage increased by the threshold voltage.

As a result, breakdown of MISFETQI8 is prevented.
Since it is connected to the source vCC, it has a relatively high drain breakdown voltage.

MI 8FETQ16 is also used for the same reason as MI 5FETQI 7 above.

According to this embodiment, the configuration using the well region as described above is effectively utilized.

The load MISFET Q19 in the cooling circuit WAI is a MISFET such as other MISFETs QI5 to Q18.
It is formed in a well region independent from the well region forming the ET. That is, the base gate of MI 5FET QI 9 is electrically isolated from the base gates of other MISFETs.

As shown in the figure, the load MISFET Q19 has its base gate and source short-circuited, and the base gate is connected to the source/drain I! High voltage is prevented from acting on channel 10.

For the connection shown, if the body gate is connected to the ground terminal like other MISFETs, the voltage required at the output terminal (second word #W12) is large, so the threshold of MISFET QI9 due to the body bias effect The increase in value voltage is considerably larger than that of other MISFETs for handling low voltages. As a result, the above output terminal (m
The voltage supplied to the read voltage terminal vPP must be significantly increased compared to the voltage required by the 2-word gW42).

On the other hand, in the case of the connection shown, the voltage of the substrate gate is equal to the voltage of the source, so that the increase in the threshold voltage of MISFET Q19 due to the substrate bias effect can be ignored. become. As a result, the high voltage supplied to the high voltage terminal VPP can be made relatively small.

As described above, by adopting a configuration in which the voltage supplied to the high voltage terminal vPP can be reduced, this high voltage terminal V
It is no longer necessary to make the withstand voltage of each 1ffi pn junction to which PP is connected abnormally high, or various undesirable leakage currents in the pn junction can be reduced. Furthermore, it is possible to prevent undesirable parasitic channels from being generated on the semiconductor surface due to the electric field from the wiring connected to the high voltage terminal VPPK.

Each reference potential mED1 of memory array MA. ED2 is connected to the anti-corrosion circuit IHAI.

In the write baked earth circuit IHA1, the reference potential @EDI
MISFET Q20 connected in series between
and Q21 connect the level switch circuit. The MI 5FETQ21 in this unit switch circuit receives a control signal from the control circuit CRL via the control ghmr. The above-mentioned side (foundation) 16 blade is +5 so that the above-mentioned MI 5FETQ21 is turned on during the information staring operation.
It is set to the level v, and set to the level 0■ so as to be in the off state during the digging operation and the erasing operation.

Therefore, the unit switch circuit sets the reference potential +1ED1 to yOv during the alignment operation.

A MISFET Q22 is connected between the potential line EDI and the high voltage level IHV in the above group 4. The above-mentioned high voltage signal edge IHV includes a write inhibit voltage generation circuit IH, which will be described later.
From A2, r120V during write and erase operations.
The high voltage level is 5:Ov during read operation.
11 is applied.

Therefore, in the digging and erasing operations.

When MI 5FETQ21 of the unit switch circuit is turned off, 2i! For the i quasi-potential MEDI, M l5
A high voltage is applied from the high voltage IHV through the FETQ22.

A MISFET is connected between the reference potential #l'D2 and the ground terminal.
A unit switch circuit similar to the above consisting of Q23 and Q24 is connected, and the reference potential #jED2 and the high ttB[Qm
I kl V (1) (VJ Niha M I S F E
TQ25 is connected.

In the above budding prevention circuit IHAI, +5 is applied to the gate.
■ MISFET Q20 which receives the power supply' reverse pressure VCC. Q
23 is the MISFET Q16.23 provided in the above-mentioned saved circuit WAI, since the above-mentioned high voltage is applied to the reference potential lines EDI and ED2. It is used for the same reason as Q17.

MISFETQ22. Q25 is the MISFETQ1
9, it prevents the increase in threshold voltage due to the substrate bias effect and uses a high voltage No. 1N Kaba IHV.

They are formed in independent well regions in order to prevent the voltages of the reference potentials MIEDI and ED2 from decreasing with respect to high voltages.

A YGO 1 circuit YGO is connected between each digit forest DI and D2 of the memory play MA and the common digit (1m) CD.

In the YGO 1 circuit YGO, 4MVjf is connected in series between the digit Mori D1 and the common dector Iwao CD.
SFETQII and Q12 constitute a unit gate circuit,
The above digit #D1 according to the output of Y decoder YDI
and a common digit machine CD. Similarly, MIS
FETs Q13 and Q14 constitute a unit gate circuit, and this unit gate circuit outputs the data H! according to the output of the Y decoder YD2. i! Connect D2 to the common digit line.

Each digit +lD1 during % write operation and erase operation
．． Since a high voltage signal appears on D2, the unit switch lil! in the Y gate circuit YGO mentioned above is activated. lNI is subjected to +5v mst pressure on the gate as shown in the figure.
Use FET Q 12 and Q 14.

The Y decoders MDI, YD2 are the X decoders XDI,
It has a similar configuration to XD2, and address No. 48 A7 to AIO output from address pack 7Bte or BIO.
By selectively receiving the non-inverted signals a7 to alO and the inverted signals a7 to alO, a decoded signal is output to the respective output lines Yl and Y2, which becomes a high level of +5V when 1 is selected and becomes 0■ when not selected. .

YGO 1 circuit Common digit #CDK connected to YGO
is connected to the sense circuit IO8 and the data input circuit IOW.

The sense circuit I08 includes a load MISFET Q47 whose gate and source are connected as shown in the figure, and a control gate connected to the gate.
It consists of a switch MISFETQ48 that receives the 1 from r. In the lead-out operation, the switch MISFET Q48 is turned on by setting the signal at Iwaro to a high level of +5.

The output of the sense circuit IO8 is connected to the inverter 114.1.
15. NOR circuit NR3, NR4 and MISFETQ49
．． It is supplied to an output buffer circuit IOH consisting of Q50.

In the output buffer Ia path IOR, the NOR circuit NR3,
One input terminal of each of NR4 is connected to control line C81. No. 16 of C8l is set to the low level of Ov during the read operation, and is set to +5V during the 41 input and r6 release operations. The other input terminal of the above NOR circuit NR3 +b inverter lN14
connected to the output terminal.

The other input terminal of N It 4 is the inverter lN1
It is connected to the output terminal of the inverter INI 5 which receives the output of the inverter INI 4.

Therefore, the NOR circuits NR3 and NR4 output signals having opposite phases to each other during the read operation. M connected in series
ISFETs Q49 and Q50 are push-pull driven by the NOR circuits NR3 and N1(4).

If the signal of control #ll1AC81 is at level )1, the NOR circuits NR3 and NR4 both output low level R of Ov, and both MISFETs Q49 and Q50 are turned off. The output terminal of the output balance circuit IOR is connected to the input/output terminal PO. MI above
In the simultaneous off state of 5FETQ49 and Q50 [
, the output balance circuit has its output impedance reasonably high and therefore does not limit the input signal applied to the input/output PO.

In the upper H pin output buffer 7U path IOH, the above M l5FE is connected between the tlL source terminal vCC and the output terminal.
TQ49 is formed in a well region independent from the well regions of other MISFETs. The well region as a substrate gate is connected to its source. As a result, the addition of the threshold voltage due to the body bias effect is virtually eliminated, so that the output buffer circuit IOR becomes y'RL source voltage vC
It becomes possible to output a high level C signal.

The data input circuit IOW includes an input buffer circuit lN16 and an input buffer circuit lN16 as shown in the figure.
1ilJ #MI 5FETQ51 and this MI
Drain of SFETQ51 and common digit +11CD
MISFE'rQ52 is connected to the threshold of the MISFE'rQ52 and receives a signal from the side gate Wl at its gate.

The convolution thread voltage generation circuit IHA2 is connected to M as shown in the figure.
It is composed of ISFETs Q26 to Q36. The MISFETs Q26 to Q28 constitute a first high voltage inverter, and are controlled by receiving a low voltage system control signal from the output terminal, that is, the MISFET
Output the first signal of the high voltage thread to the drain of BTQ27.

With the connections shown, the output signal level varies from yOv to v
Changes up to PP. MISFETQ29 to Q31 constitute a high voltage inverter @2, and by receiving the same signal as the first high voltage inverter, MISFETQ
A high voltage system signal is output to the drain of 30. Its output signal level is from r+5V (vCC) to VPPt”ff
become MI 5FETs Q32 to Q36 constitute a high voltage push-pull circuit. Above 'M1. MISFETQ2B, Q31 . which receive control signals in the second high voltage inverter and push-pull output circuit. Connected between Q36 and each output terminal, +sv to the gate
MISFETQ27゜Q30.
Q35, like the previous MISFET Q16°Q17, is used to ensure a high output voltage of the circuit.

Load MISF in the first and second high voltage inverters
ETQ26. As shown in the figure, Q29 has its body gate connected to each source to eliminate output voltage drop due to body bias effect, and MI8 of the push-pull output circuit.
FETQ33 and Q32. It is configured to be able to sufficiently drive Q34.

In the above push-pull output circuit - (, MISFETQ
32 is used to limit the voltage applied to the )′ line of MISFBT Q33 when the output of the first high voltage inverter is xov.

That is, when the output of the first high voltage inverter is yOv, the reference potential of the second high voltage inverter is +
Since it is considered to be a low voltage of 5v, it outputs +5v. 17) M ffi, M I S F gT Q 32
+5v is applied to the gate of 0Ml5FETQ3, which limits the drain voltage of 1Ml5FETQ33.
4 is the first. After the output line IHV is set to a high voltage of +20V due to the output of the second high voltage inverter becoming a high voltage, when the output of the 1st high voltage inverter becomes a low level of yov, Output MIHV to M
It is used to limit the high voltage applied to the source of ISFET Q33. As a result, undesired breakdown of the source and drain junctions of the switched MI 5FET Q33 is prevented.

The erase circuit ER8 is constituted by a high voltage inverter made up of MISFETQ40 to Q42, and a push-pull circuit made up of MISFgTQ43 to Q46 and a bipolar transistor Q44. The high voltage inverter includes the write stop voltage generation circuit IHA2.
It has a similar configuration.

In the push-pull output circuit, bipolar transistor Q44 and MISFET Q43 are connected in parallel and driven by the output of the high voltage inverter. The well regions forming the memory array constitute a heavy capacitive load for the erase circuit, as will be apparent from the structure of the circuit arrangement described below. Follow [,? The erasing circuit BR8 is required to have sufficiently low output impedance characteristics in order to perform a high-speed erasing operation. Bipolar transistors exhibit sufficiently low operating resistance characteristics compared to MI8FζT even if they are formed with relatively small dimensions ((m product) in a gyroscopic circuit device.

As shown in the figure, the erase circuit ER8 having the bipolar transistor Q44 as an output transistor drives the well region of the memory array MA at a sufficiently high speed even if it is formed with a small L[Ii layer in a semiconductor circuit device. The structure and manufacturing method of a bipolar transistor formed on the same semiconductor substrate as the above-mentioned MISFET will be explained later.

In the erase circuit ER8, when only the bipolar transistor Q44 is used, the threshold voltage (base-emitter voltage) of this bipolar transistor is, for example, 0.6V, so the MISFETs Q40 to Q4
The above A'l consisting of 2! Pressure inverter S:QEII
Even if a signal of the J voltage vPP is output, the voltage signal output to the output IN1 is lowered by the threshold voltage of the transistor Q44.

In the illustrated erase circuit ER8, the body gate is integrated with the body gate of the load MISFET Q40 of the high voltage inverter, and the gate is integrated with the body gate of the load MISFET Q40 of the high voltage inverter.
A depletion type MISFET connected to the source of SFgTQ40, that is, the output terminal of the high voltage inverter.
Q43 is connected in parallel with the bipolar transistor Q44. In the above MI 5FET Q43, the high potential of the base gate rises to the y power supply voltage VPP, so there is virtually no increase in the threshold voltage due to the substrate bias effect, and the Iwi'ThE pressure at the secondary 5'' C1 output mlK is ,
Depending on the above MI 5FETQ43, S: power supply voltage vP
It becomes K so that it can be raised to P.

The body gate of the above MI 5FET Q43 is connected to its source, that is, the output device 1 through the connection shown in the figure. Even in this case, the output m! due to the body bias effect! This can prevent the output level from decreasing and causing [stripes]. However, in this case, due to the structure of the circuit device, the well region serving as the base gate of MI8FET Q400 and the well region serving as the base gate of Q43 cannot be shared and must be separated from each other.

The requirement for a certain spacing between the wells and regions has the disadvantage that the area of the semiconductor substrate required must be increased.

The control circuit CRL includes an inverter INI or N12,
NAND circuit NAI to NA4, NOR circuit NRI, NR
2 and MI 5FET Q37 to Q39 in series
Consisting of This control circuit ORL is connected to the external terminal PGM.
, C8 and VPP, respectively, receive the lead-in control # signal, chip selection No. 18, input and erase signals, and receive the output signal from the writing thread back pressure generation circuit IHA 2, thereby AjJCS 1. r, WL Outputs the cape bond to Wl and vp.

No. 11 supplied to the terminal vPP is commonly used as a power supply voltage for the write circuits WAI, WA2, the thread pressure generation circuit IHA2, and the erase circuit ER8.
This is a 25V high retrovoltage system signal.

The side cape circuit MC'RL uses MISFBT Q37 to Q as described above so as to control *1 inclusion or erasing operation only when the signal at the terminal vPP exceeds a predetermined level.
It includes a level shift circuit consisting of 39 circuits.

The operation of the #P4 body memory circuit shown in FIG. 1 will be explained as follows using the timing charts shown in FIGS. 2 through 4. Note that FIG. 2 shows a timing chart of a read operation, and FIG. 3 shows a timing chart of an erase operation. Further, FIG. 4 shows a timing chart of a write operation.

In the read operation, the input control n signal at the terminal PGM is at the low level of XOV. In addition, the terminal VPP is set to %:0■ or floated, and the t-voltage VCC of +5V is applied to the gate.
It is connected to the drain of MI8FETQ39 which is open.
The o v compliment and erase control signals are present.

The control signal 1ii is controlled by the write control signal 04 at the low level at the terminal VPPK and the oath and erase signal at the level 9 at the drain of the MI 5FETQ39.
The signals at Wl and vp are at high level, and the signal at Wl is at low level.

Therefore, each reference potential WED1 . ED
2 is a write-inhibited circuit If (by Al [ha!1″Ov
Similarly, each of the second word training W12 and W22 is set to rov by the write circuits WAI and WA2.

Although tying is not particularly limited, 1 For example, at time 10, signals at address input terminals AO to AIO are set corresponding to the memory cell to be selected. 6 For example, if the memory cell to be selected is MSll, the signals at address buffers BO to AIO The output of X decoder XDI becomes high level due to the output of B6, and the output of Y decoder MDI becomes high level due to the output of address decoders B7 to BIO.

As a result, a MISFET Q is connected between the drain of MNO8QI of memory cell MSII and the common digit @CD.
1. MISF for Qto, digit-DI and switch
A current path is formed through gTQ2. Also, due to the signal on the control line r, the common digit CD and the load of the sense circuit IO8 are connected to the load MI5FETQ4.
A current path is formed between the terminal and the terminal 7.

If MNOS Q 1 of memory cell MSII is in the on state as shown in the characteristics shown in FIG. 13A, the sense circuit I
The output line of O8 is grounded via the current path and MNO8QI. As a result, the output line of the sense circuit IO8 becomes low level.

MNO8QI of the memory cell Mail is shown in FIG. 13B (
If it is in the off state as shown in characteristic 10, then the load MI
A current path for the 5FET Q47 is not formed, and as a result, the output line of the sense circuit IO8 becomes high level.

At time t1, the chip selection signal at terminal C8K changes from high level to low level, and at the same time t2, the signal at control line C8l goes to low level. As a result, the output buffer circuit IOR is
From the high output impedance state, a positive signal corresponding to the output level of the sense circuit IO3 is output. For example, if the sense circuit IO8 is outputting a high level comment, the output circuit IOR outputs a -high level signal to the output terminal.

When the chip selection signal returns from the low level to the high level at time t3, the control edge C8 changes at the same time t4.
The 1 signal changes from low level to 21 high level, and in response to this, the output parafluid circuit OR returns to a high output impedance state.

For the erase operation, +25V write/erase I#1 is applied in advance to the terminal vPP, and a low-level chip selection signal Ov is applied to the terminal C8.

The signal on the control ##vP is at a high level due to the chip selection signal at the above level, and therefore the convolution circuits WAI and WA2 are connected to the second word line W12. W22 is 5
:OvK.

As shown in FIG. 3, when the input control signal is set to high level at time tlO, the NAND circuit NA responds to this.
The output of 4 becomes low level. Erased 1g1MER8 is erased by each low level of the NAND circuit NA4.
Since the I8FETs Q42 and Q46 are turned off, a +250 high voltage is output to the output M1.

As mentioned above, the second word leg W12. Since the number 1 in W22 is set to Ov, when the well region WELL is set to a high voltage of +25V by the output of the erase circuit ER8, a high voltage for erasing is applied to the gate emu of MNO8 of the memory array. It will be done.

The positive voltage in the well region is the MNO8QI of the memory cell.
and M1 for switch. The direction is to forward bias the source and drain junctions of SFgTQ2. Therefore, the base $ potential line ED1. ED2, Ditzk) Brain D1. D2
If a current path is formed between at least one of the well regions and the ground terminal of the circuit, the voltage to be applied to the well region will be reduced.

The illustrated circuit operates as follows to prevent the voltage drop in the well region described above.

The signal at control mar becomes low level in response to the 4F writing control signal becoming high level at time t11, which is the same as time tlo.

MI8FETQ21. of the write inhibit circuit IHAI is activated by the signal on the control line 8 r. Q24 and MISFET Q36 of the write inhibit voltage generation circuit IHA2 are turned off. As a result, each reference potential line E of the memory array
DI and ED2 are substantially floated.

The signal at the control HmWl is at low level in accordance with the low level of the chip selection signal. Therefore, M in the data input circuit 10WK connected to the common digit CDK
I5FET Q52 is in the off state. On the other hand, the MISFET Q48 in the sense circuit IO8 connected to the common disk) MOD is connected to the above-mentioned side ms! The signal at r turns it off.

Due to the floating of the common digit CD, the valley digits -DI, D2 of the memory array MA become 70-digits regardless of the operation of the YGO.

At time tll, the signal at the terminal PGM returns to the low level, and accordingly, the output of the erase circuit ER8 also returns to the low level.

As described above, the erasing operation is performed in the chip selected state, whereas the fill-in operation is performed in the chip non-selected state, that is, when the signal at the terminal C8 is at a low level. For the write operation, +25V of write, erase and erase voltage is applied to the terminal VPP in advance.

At time t20, address enable signal a is set to select, for example, memory cell MSil.

That is, the X decoder
t is set to high level, and the leg Y is set by the Y decoder YDI.
1 is considered a high level.

At time t21, information to be written is added to terminal PO. If the information to be written is O, the terminal PO is Ov.
and the data input circuit IOW17) MI
8FETQ51 is +5 from the input buffer circuit lN16.
It receives a high level signal of v and turns on. 11 If the information to be read is 1, for example +5v, the above MIsF
gTQ51 is the 0 output from the input buffer circuit lN16.
■The switch turns off.

When the write control signal of the terminal PGM becomes high level at time t22, 18 of
The number becomes low level. As a result, the write inhibit circuit I
HAI's MISFETQ21. Q24. MI5FETQ36 of the write stop voltage generation circuit IHA2 and MISFETQ4s of the sense circuit IO8 are turned off.

At time t24 after a slight delay from time t23, the control mW signal becomes low level. By the signal of the above control line W, #press-M stop pressure is generated IDJ
16 I HA 2 is 1IHV & cll? A high voltage of +20V is now output, and in response, each reference potential #ED1. ED2 becomes the above +20V.

At the same time as the time t24, the control signal We becomes high level. In response, MISFETQ52 of the data input circuit 20W is turned on. At the same time, MI 5 of write circuits WAI and WA2
FETQI 5 is turned on.

Output line IH of the write inhibit voltage generation circuit IHA2
When the V signal becomes a sufficiently high voltage, the control circuit CRL receiving the IHV signal outputs a low level signal to the control line P at time t25. The above control line map P
The signal at &C is the write start signal for clarity. By configuring the write start signal to be output after the %1lfiIHV signal reaches a sufficient write-in prohibition level as described above, it is possible to prevent information from being written into unselected memory cells. can do.

As described above, when the signal in the control controller PIC becomes low level, the write-in circuit WAI is activated.

MISFET Q18 of WA2 is turned off.

The first word #JIWll is selected and is set to X+5V, so the second word is MWAH2.
2 outputs a high voltage of r+25V.

Since @l word + ylIW21 is not selected and is set to almost Ov, the enrichment circuit WA2 selects the second word accordingly.
Approximately Ov is output to word mW22.

MNO8Q1 in the memory cell MSII to be selected is MISFETQ2 for switch, digitizer D1, Y
MISFETQ5 receives the output of input buffer circuit INI6 via MI8FETQ12, Qll, common digit storage CD and MISFgTQ52 of gate YGO.
1. If the 1## to pledge is 1,
Due to the ON state of the MI 5FET Q510, the drain and source of the MNO8QI in the memory cell MSII become almost 0, and due to the high pressure of its gate (second word pass W22), electrons are generated during the gate failure. Injected. If the information to be written is O, the above MI
Due to the OFF state of 8FETQ51, the memory cell MS
The source and drain of MNO8QI in II are set to +20V of the pre-arrangement inhibiting voltage generation circuit IHA2. Therefore, the above electrons are not injected into the memory cell MS21 of the other row coupled to the same memory cell D1.
, the signal of the second word W22 is almost O as described above.
v, so no information is written.

Since the MISFET Q13 in the corresponding Y gate YGO is in the off state, the other disk (mD2) is maintained at +20V by the output of the write inhibit voltage generation circuit IHA2.

When the write-enabled HIK signal at the terminal PGM becomes low level at time t26, as shown in FIG. 3, the signal at time t27. t28. At t29, the signals at the control 141 organs v P , w·, r reach the noi level. Accordingly, the second word w12, the reference potential #E
The signal of D1 also becomes almost O.

The semiconductor memory circuit of the present invention can have a relatively large capacity, for example 16 bits.

FIG. 5 shows a block diagram of a semiconductor memory circuit using the circuit of FIG. 1.

In the 511th memory array MA, for example, 128
It includes 16384 memory cells arranged in rows and 128 columns. For the memory array MA, an X decoder XD is provided which selects 128 memory cell rows by receiving 7-bit address input signals from address buffers BO to B6. Also, one of the memory cell rows
8 Y gates to select 6@ each YGO or YO2
are provided, and these Y gates are connected to address buffer B
It is controlled by a Y decoder YD which receives a 4-bit address input signal from 7 to BIO. Y game above)
Input/output circuits 0 to F including a sense circuit, an output buffer circuit, and a data input circuit as shown in FIG. 1 are provided corresponding to YGO to YO2, respectively. MIS as shown in Figure 1 corresponds to each memory cell column.
A write inhibit circuit IHA including FETs Q20 to Q22 and one write inhibit voltage generating circuit is provided, and a C% write circuit WA is provided corresponding to the memory cell row. Furthermore, a control circuit CRL and an erase circuit ER8 are provided.

Therefore, the semiconductor memory circuit shown in FIG. 5 stores 8 bits of information at 11 bits, that is, 2048 addresses.

As mentioned above, the memory cells are connected to MNOS and switch MI.
By configuring the X decoder and writing circuit with 5FETs and making them independent circuits,
X decoder? h configuration can be simplified. Therefore, it becomes easy to speed up the selection of word size by the Xfl-der, and it becomes possible to provide a memory circuit that operates at high speed.

MISFETQ22jQ25 in write inhibit circuit
The sources are the reference potential lines EDI and ED2 as shown in Figure 1.
Instead of being connected to the digits #D1 and D2, it may be connected to the digits #D1 and D2.Even in the above case, it is possible to supply the write thread voltage to the memory play. However, if we do the above, each digit MDI
, D2 is the junction capacitance of MI8FETQ22jQ25,
Floating capacitors such as the wiring 8h are coupled together, and as a result, care must be taken because the rate of change of 1r for each digit is limited when reading and writing the stored t# information. As shown in Figure 1, MI 5FETQ22. When connecting Q25 to the reference potential gauze EDI, ED2,
It is possible to increase the rate of change of each issue of 1.

Each of the above circuits is created using semiconductor integrated circuit technology.
Formed on one semiconductor substrate.

According to the present invention, each of the circuits described above is formed on a semiconductor substrate in an arrangement that does not limit the circuit characteristics and does not increase the size of the semiconductor substrate used.

FIG. 6 shows a pattern of regions for each circuit and wiring formed on the silicon substrate 1. In the same figure, an X decoder XD is electrically distributed in the center of the surface of the substrate 1. The memory array is divided into two, MAI and MA20, of which MAI is placed on the left side of the X decoder XD, while MA2 is placed on the right side.

A commitment circuit WAa is placed on the left side of the memory array MAI, and an 11111K commitment circuit WA6 is placed on the right side of the memory array MA2.

Above the memory array MAL, a Y game (YGa) is arranged, and similarly above the memory array MA2 is a Y game) Y
Gb is arranged. A Y decoder YD is arranged between YGa and YGb, that is, above the X decoder XD.

The above memory array, X decoder, and IF reading circuit.

The area around the Y gate and Y decoder is a wiring region WIR as indicated by dots.

The above memory arrays MAt, M across the wiring area WIR
A write inhibit circuit IHAa is provided below each of A2.
, IHAb is located.

Around the surface of the board 10, there are input/output circuits IO, control side 1 circuits CRLI and CRL2 . Input 2277 circuits A1 to A
12 are arranged. Further, bonding bags (P1 to P28) for connecting the input terminals and output terminals of the % building to terminals outside the circuit device are arranged around the upstream side.

In order to configure the circuit shown in FIG.
I and MA2 are each sized 128 rows by 64 rows. Corresponding first words of memory arrays MAI and MA2 are allowed to be selected simultaneously by an X decoder XD. The input edge of the X-decoder XD is connected to an input buffer circuit arranged around the substrate 1 via wiring in the wiring region WIR.

Y gates YGa and YGb are simultaneously connected to corresponding memory arrays MAI and M by the output of Y decoder YD.
The A2 digit machine is selected. The Y gates YGa and YGb are connected to the input/output circuit IO through the arrangement of the wiring region WIR.

The write inhibit circuits IHAa and IHAb are connected to the corresponding memory array M via wiring in the arrangement area WIIt, respectively.
Connected to reference potential # of AI and MA2.

As mentioned above, embodiments of the invention use well regions for the memory array and its peripheral circuitry.

FIG. 7 shows a pattern of a well region formed on the surface of the silicon substrate 10, corresponding to the (b) device shown in FIG. FIG. 8 shows a sectional view taken along the line AA in FIG. 7.

In FIGS. 7 and 8, in order to form a memory play, Pm
Well regions M10a and 10b are formed.

Around the upper Nd quel regions 10a and 10b,
Separated from this are the CX decoder, Y decoder, and Y gate.

Honor writing circuit, write protection circuit, input/output circuit.

A pm well region 11 is formed for forming peripheral circuits such as an input 2777 circuit and a control circuit.

Although shown in a large size in the upper part of FIG. 7 due to space limitations, M in the output buffer circuit l0RK of FIG.
In order to form a MISFET that connects the source and the base gate like the I5FET Q49, a P well region 11 is formed which is separated from the Pfl well region 11 and is independent.
& or llb is formed.

Similarly, on the left side of the P-type well region 10m and on the right side of the P-type well region 10b,
In order to form a MISFET such as, independent P-type well regions 11c to lid and lie to llf are formed, respectively. Refreshingly, in the lower part of the paper in FIG. 7, in order to form a MISFET that requires a similar base gate, such as the write inhibit circuit IHAI and the # write inhibit recovery voltage generating circuit IHA2 in FIG. , P-type well regions 11g to llh and 111 to llj, which are independent from other P-type well regions, are formed.

Although not shown in FIGS. 7 and 8, in order to form the MISFET to be described, a predetermined portion of the P-type well region 11 is provided with na! ! K so that silicon substrate 1 comes out 4 times.
be done.

According to this embodiment, as described above, the nW silicon substrate 1
Since each MOP query region is formed on the top, six effective elements such as transistors for a semiconductor memory circuit device can be formed.

For example, a channel stopper for preventing a parasitic channel is formed by impurity ion implantation or the like on the surface of the n-type silicon substrate 10 where a plurality of P-type reel regions are mutually exposed, as will be described later. will be used effectively.

That is, for example, Fig. 9 shows an MI that can obtain high breakdown voltage characteristics.
A cross-sectional view of the SFET is shown. In the same figure, 11 m
is a P-type well region, and 21 is a nu formed on the surface of the substrate 10 so as to span a part of the well region 11m.
Channel stopper, 95.96 is n type source region,
drain area.

63 is a gate P and m film made of silicon oxide; 60 is a base a1 other than the region where an element such as MI 5FET is formed;
and a thick silicon oxide film covering the surface of the well region, 84
120 is a gate electrode made of n-type polycrystalline silicon;
For example, insulation g made of phosphosilicate glass, 121,
Reference numerals 122 denote a drain itt electrode and a source electrode, respectively, which are made of, for example, vapor-deposited aluminum.

In the blank space of FIG. 9 below, the substantial drain region of the MI 5FET is constituted by a region 9S for contacting the electrode 121 and a channel stopper 21. The channel stopper 21 is for preventing a parasitic channel from being formed on the surface of the n-type substrate 10, and has a relatively low impurity concentration. Therefore, the channel stopper 21 in the portion extending to the upper K of the P-yatwel area 11m is
The specific resistance is sufficiently higher than that of the region 95 for contacting the electrode 121. The MISFET shown in FIG. 9 has a channel stopper as a part of the drain region as described above, and thus has a large drain breakdown voltage.

Therefore, in the embodiment, the nff1 board l is connected to the high voltage terminal VPP (see Figure 1), and this high voltage terminal v
The MISFET has the structure shown in FIG. 9 above, in which the drain is connected to PP.

In other words, the write inhibit voltage generation circuit HA in Figure 2g1
2 dipledge type MI8FETQ26,Q
29, Q32, write circuit WAI.

Dibretsun type MISFETQ19 in WA2
, depletion type MISF in erase circuit ER8
E'rQ40. Q43 and the enhancement type MISFET Q37 in the level shift circuit or voltage dividing circuit (Q37 to Q39) in the control circuit CRL are
The MISFET has the structure shown in the figure.

Note that, in the depletion type MISFET, as will become clearer from later description, the P
It is formed by ion-implanting a P-type impurity, such as boron, into the surface of the type well region 11m.

FIG. 1θ shows a cross-sectional view of an npn transistor. In the figure, the nm substrate 1 is used as the collector region of the transistor, the P-type well region 11n is used as the base region, and the n+ region 97 is used as the emitter region. The n+ type deposit 97 is formed at the same time as the source and drain regions of the MI 5FET. The above npn) transistor is used in the erase circuit ER8 of FIG.

The above-mentioned MNOS and various MISFETs may have a structure with an aluminum gate, but it is preferable to have a structure with a silicon gate as described above.

Therefore, when explaining in detail the structure of the elements and wiring constituting each of the above circuits using silicon gate technology below, the manufacturing method will first be explained for easier understanding.

Hereinafter, based on FIGS. 11(2) to ◎, the manufacturing process for forming 8 MNO elements, 8 enhancement (enhancement) WMO elements, 8 depleted MO8 elements, and bipolar transistors on two semiconductor substrates will be described in detail.

4. As a substrate wafer l, an n-type single crystal with a (100) crystal plane, a resistivity of 8 to 12 Ω steel (impurity concentration of approximately 5 x 101
A silicon (St) wafer of 4 types is used. The resistivity of this wafer is preferably as large as possible (low impurity concentration) in order to form wells with low impurity concentration with good reproducibility.
(E 1ectr Lcally Alterable
In the example of the Read Only Memory (electrically rewritable read-only memory), the impurity concentration of the well was set to about 3XlO"crs-", so a silicon (si) wafer with the above impurity concentration was used. Use.

As shown in Figure 11, after cleaning the surface of this silicon wafer with an appropriate cleaning solution (0, -H, 804 solution or HF solution), a silicon oxide film (SiO,) with a thickness of approximately 50 nm is formed by thermal oxidation. 2 and continue CVD (C
Chemical Vapor Deposition：
Silicon nitride (S1sN
4) Form the film 3 to a thickness of approximately 100-140 nm. This 81. Regarding the film formation method, a comparison was made using an atmospheric pressure vertical CVD apparatus, an ordinary pressure horizontal CVD apparatus, a low pressure overflow CVD apparatus, etc., but no particular difference was observed. However, low pressure CV
The uniformity of the film thickness obtained using the D device was the best, and was within ±3% within the wafer, which was convenient for microfabrication. Although there are some differences depending on the method, the appropriate deposition temperature is in the range of 700 to 1000°C.

This result is also the same for the St, N, and film formations used below.

(2) Next, a photoresist film 4 is formed on this silicon nitride film 3 by photoetching only in the area other than the area where the well is to be formed (between the wells). In other words, the SN and N4 films are exposed on the surface of the region where the well is formed. In this state, the exposed portions of 81.8. The film was removed and StO,
Membrane 2 is exposed. After that, use the resist film 4 as a mask.

Boron (B) ions are injected into the Sk substrate in the area where there is no resist film through the S SO* MA 2 exposed on the surface with an energy of 75 KeV)-Tardose 3
10 "ear" implant P-shaped semiconductor region 5.6.

(Q) After this, after removing the resist film 4, well diffusion is performed in dry acid X (Os).

Since boron becomes an acceptor type impurity in Si, Pm
A well is formed. As a result of diffusion at 1200° C. for 16 hours, the formed P-type wells (10, 11) have a surface concentration of 3×10 11 and a diffusion depth of about 6 μm. however,
This value was obtained from the results of measuring the surface sheet resistance using the four-probe method and the diffusion depth using the stain etching method, assuming that the impurity distribution in the well is a Gaussian distribution. . The reason why well diffusion is performed in oxygen is to form a uniform well at a low concentration.

At the time when the well diffusion is completed, as shown in FIG.
An oxide film of about 10 μm is formed on the surface of N, [3. Therefore, by etching the entire surface with StO, a thickness of approximately 50 nm was etched.
810. By removing the membrane, the well surface has
A thick silicon oxide film 12.13 of about 0.8 μm remains,
Between the wells, 81, N, and the surface of the membrane 3 are exposed.

0 Next, Si, N, [3, for example, hot phosphoric acid (H, PO,
) and remove it by etching using a solution such as K between the wells.

The initially formed 5i01 film of approximately 50 nm (Fig. 11 (
[)14, 15, 16) are exposed. In this state, a StO film of about 0.8 μm thick is formed on the wells and about 50 nm thick between the wells. In this state, phosphorus (P) ions are implanted into the entire surface at an energy of 125 KeV and a dose of lXl0''f-2.
Phosphorus ions are not implanted into the well except for the peripheral portion of the well region, and phosphorus ions are implanted between the shells to form N-type medium conductor regions 20, 21, and 22. In addition, the 81
．． The well expands laterally from the edge of the N4 film during diffusion, and a difference of approximately 6 μm and 1 m exists between the edge of the Sl and N4 films (that is, the edge of the thick S fog film above the well) and the well edge. In other words, the phosphorus ion implantation layer is formed approximately 6 μm from the end of the well into the well. Also,
This phosphorus ion implantation layer has a depth of about 1 micron steps when measured after the final thermal step.

By implanting phosphorus ions between the wells in a self-aligned manner as described above, conduction between the wells (P type) can be prevented.
22 S AP (Self Ali-gned P
chaunel field lon 1nsprau
It is called tatlon)j-.

As mentioned above, the p-well diffusion region is 81. Formed by heat treatment in an oxidizing atmosphere using an N4 film as a mask,
By adopting a method of implanting N-type impurities into the surface of the N2U substrate between the wells, using a thick oxide film formed on the well surface as a mask, and forming an SAP layer for preventing channel generation between the wells, the mask is Ion implantation between wells can be performed without increasing the number of layers, and the well diffusion region and the ion implantation layer between wells can be formed in a self-aligned manner. This technique will hereinafter be referred to as the SAP method.

After this, a Si layer is formed on the surface of the Si substrate.

Remove all A11 (12, 13 and 14.15.16). In this state, p-type well regions (1o, 11) and n-type (having an impurity concentration higher than the substrate n-type impurity concentration) regions (20, 21, 22) are formed on the surface of the substrate 81.
) is formed, and furthermore, at the boundary between the two, approximately 0.4
Irregularities 17 (steps) of ~0.5 μm are formed. Using this step, mask alignment for the next photoetching process can be performed.

Next, the so-called LOCO8 (Local 0xi-
A process called oxidation is carried out.

(G) First, as mentioned above, 810. After removing all the film, about 50 nm of Sl is applied to the entire surface of the substrate.
A pattern film 4 is formed by a thermal oxidation method. Continued CVD
According to the law, this S10. 8 of 100-140 nm on the film
1. Form an N4 film.

Next, by photoetching, a photoresist film is left only in predetermined areas such as areas where active elements will be formed (35.36, 37° 3B, 39.4 in Figure 11 ■).
0). In other words, in this state, the photoresist film is removed from the surface of the portion where it is necessary to form a thick oxide film for isolation between elements, etc., and 81. N, membrane is exposed. In this state, plasma etching is performed and the exposed 8
isN+# removed and the approximately 50 nm previously formed on the surface
Sin.

The membrane (24) was exposed. After that, using the above resist film as a mask, boron (B) ions are introduced into the Si substrate in the part where there is no resist film through the S50HM (24) exposed on the surface at an energy of 75 KeV, )-1 pv dose. 2 x 10" 3-1 Te implant, p-type semiconductor layer 4
1. Form 42, 43, 44, 45°46. At this time, the photomask is designed so that the end of the KsiaNa film is located in the SAP implant layer at the end of the well where it is necessary to form the high breakdown voltage DMO8. In this way, the first
As shown in FIG. 1, an active region is formed spanning the trap, the 8AP layer (21), and the well. This boron ion implantation is described below as a field implantation method (
It is called F implant.

[F] Thereafter, after removing the resist film, field oxidation is performed in wet (moist) oxygen (0,). By performing this oxidation treatment at 1000° C. for about 4 hours, about 0.95 μm of SIO is formed on the surface of the 8i substrate where the Si and N4 films have been removed.

A membrane (60) is formed. In this state, approximately 0 between the wells
, the part where a 95 μm thick field oxide film is formed, for example, the St coating surface shown in FIG.
Moreover, in the amount of tones, phosphorus is I
-”, the bow is 2X10”cm-Yuki and Ho.

However, during field oxidation, the amount of boron that segregates into KSiO is larger than that of boron.In other words, the boron in 81 is depleted at the interface with SIO. However, since phosphorus in Si piles up (accumulates) at the interface with 5iO1 (see Figures 28 and 29), the surface between the wells has a high concentration of phosphorus, and the channel It fulfills its role as a stopper.In this way, by sharing the above-mentioned SAP method and LOCOS process and making good use of the difference in behavior of phosphorus and boron at the StO interface as described above, it is possible to eliminate the need for a masking process. Inject phosphorus at the lowest possible concentration (
This is due to high voltage depletion, which will be discussed later.
Items required for use as the drain of SFETDMOS) and boron implantation that requires a higher dose (items required to maintain the threshold voltage of parasitic MO8 (field MO8) to a certain degree) ) can coexist and ultimately increase the phosphorus concentration.

Thus, a p-type semiconductor region 51 is formed under the thick oxide film on the substrate surface corresponding to the p-type ion implantation layers 41 to 46 in FIG.
~56 are formed.

Immediately after performing this field oxidation, as shown in FIG.
nm S10. 5 of about 100-140 nm on the film 24.
1aNa film (25-30), and about 20n on the surface
An oxide film of about 0.95 μm is formed in the field region. A membrane (60) is formed.

0 In this state, perform sioting and etching on the entire surface, approximately 5
After removing 0 nm of StO, the field region has approximately 0.9 μm of 810. Film 60 remains, with 50 nm of StO in the active region, film 24 and 100-1
A 40nm St, N4 film 25-30 remains, and this Sl
, the N4 film is exposed. Continuing with this, this Si
, the N4 films 25 to 30 are heated with hot phosphoric acid (HsPOa), for example.
) Remove using liquid etc.

In this way, the active region is covered with the previously formed 810. The membrane 24 remains, and this 8
Although it is possible to use the 401 film 24 as the active MIaFET gate oxide film, the gate breakdown voltage may be poor due to the abnormal region (generally thought to be 5tsNt PA) that occurs at the end of LOCO8. As shown in FIG. 110, this thin oxide film 24 and the Sl, N, and films on it are removed once, and then, for example, after repeating the formation and removal of 45 nm of StO, As shown in FIG. 0, a sto, M (62 to 67) of about 75 nm, which is actually used as a gate insulating film, is formed, for example, at 1,000 DEG C. for 110 minutes.

0, furthermore, among the transistors (MOS), EMOS
(Enhaucement mode MOS: L
In order to set the threshold voltage of the thin gate insulator [62 to 67, boron ions are implanted into the entire surface with an energy of 40 KeV) - Taldose 2X10. ”/
Drive with α weight (Fig. 11 071-76).

Naturally, this boron is not implanted in the field regions which have a thick oxide, and the 810.degree. S below the part where the membrane is present
5. Implanted onto the surface of the substrate through an SmuO1 film.

(I) Next, since the EAROM described in this example uses an E/D converter as a peripheral circuit to increase the speed,
KDMO8 (De-pleti) other than EMO8 mentioned above
It is necessary to form an on mode MOS (one in which the L threshold voltage is low and current flows at the gate voltage Ov). In order to form this DMO8 in a predetermined portion, S10.
After a photoresist film is deposited on the films 60, 62 to 67, the photoresist film on the area where the DMO 8 needs to be formed is removed by a photoetching process as shown in FIG. 11(I), and the other parts are left. Using the photoresist film 80 as a mask, phosphorus ions are implanted only in predetermined portions (81), and the threshold voltage of the DMO 8 is set. Here, for example, the energy is 100 KeV.

It was implanted at a dose of 1.2 x 10'"7cm". This also applies to the region of the high voltage DMO8 (11th
Figure (I) 81). In this way, by forming a deprisin MO8FET on the boundary surface around the well made by the self-aligned isolation method (SAP) between fers, it is possible to form a photomask on the same chip as will be seen from the following explanation. Non-volatile memory element MNO8 and high breakdown voltage D without increasing
It becomes possible to coexist with MO3.

(J) Next, after removing the photoresist film 80, polycrystalline silicon (
A poly 81 ) layer is formed at about 580° C. for about 35 μms. Regarding the poly 81 formation method, a normal pressure method and a low pressure method were also compared, and apart from the fact that the latter method was superior in film thickness uniformity, there were no particularly large differences in characteristics. Subsequently, polySi was doped with phosphorus by a diffusion method. The conditions in this case are, for example, 10
00℃, 20 min POCz, P from the source poly8
1 surface, and was further stretched for 5 minutes, so that the resistance of polySi was about 15Ω/hole.

After that, the phosphorus glass formed on the surface of polys1 is removed by etching with a solution containing HF, etc.
By photo-etching, the photoresist is left only in a predetermined area, and by plasma etching, polysl is removed from areas other than the areas where the photoresist remains.
n, a gate electrode and wiring were formed using a first layer of polySt on the film (FIG. 11 (J) 83.84).

Next, using the first pO-Si layer (83, 84) as a mask, the gate oxide film 62 is selectively etched to partially expose the substrate surface as shown in the eleventh point.

■ After this, oxidation was performed at 850°C for 20 minutes in a wet atmosphere, and about 40 nm of S was applied to the exposed St substrate surface.
In, the film (11th figure 87) was deposited on the polyS1 surface with approximately 200 nm of 810. A film (85, 86) is formed. After this, the entire surface was subjected to S tO and film etching for about 60 minutes.
By removing nm sto, m, poly
The S1 upper pressure is approximately 140 nm S10. is left behind. In this way, a thick oxide film is formed on poly 81, and St
In order to form a sufficiently thin oxide film on the substrate surface, p
It is important to contain at least 10 cm of phosphorus in the olySi and to perform the oxidation in a wet atmosphere at a temperature in the range of 600 to 1000°C.

■ Next, the S io film 85 left on the polysl
86 as a mask (in other words, 5iO1 in this case prevents etching of the highly doped first layer polysilicon), the exposed St substrate surface was etched with NH, -H.
, O, and HCL-H, O, after being lightly etched with an etching solution containing H, O, a thin oxide of about 2 nm! (11th
Figure ■88) is N! Formed by oxidation at 850°C for 120 minutes in diluted O1, followed by CVD method to form approximately 50%
81.nm. N, form a film (90). Here, we compared the formation methods of the formed Si and N4 films using various methods as mentioned earlier, but in the end, we found that the high temperature H and annealing described later resulted in no problem in any case. I was able to get

After this, this 81. N, polySi on the membrane 90
After depositing a layer (second layer) of about 0.3 μm, it is processed by photoetching to form a second layer (second layer) of polySi.
A gate (091 in FIG. 11) is formed. Subsequently, using the first skin polyS1 (91) as a mask, [,1X10
1.tar'' @ 90 KaV ``11'' 17 ions are implanted into the silicon substrate to form N-type semiconductor regions (92 to 100) such as sources and drains, and at the same time, the second
The layer potY st 91 was also doped with phosphorus. At this time, since the first layer of polySL (83, 84) has already been doped with phosphorus and the crystal grains have increased, phosphorus is implanted into the surface of the St substrate under the 11f4 polySL by implanting phosphorus ions. However, as mentioned above, about 140n on the first skin polyS1
810 of m. Film 85.86 and 50 nm of Sl,N.

Due to the formation of membrane 90, this risk is eliminated.

- Next, using the Si, N, film (90) formed under the second layer poly Si 91 as a mask, [second skin pol
After selectively oxidizing yS1 (91,84) in a wet atmosphere at 850°C for 10 minutes, this oxide film (102
) was used as a mask to selectively remove the 8i, N, film.

In other words, the highly doped first skin polyS1 is protected from Sl, N, and etching solution by the upper oxide film.

In this state, the breakdown voltage between the first polySi gate and the source or drain (gate breakdown voltage) is poor, so after this,
Oxidation treatment was performed at 850°C for 30 minutes in a wet atmosphere to improve the gate breakdown voltage of the second layer polyS1 gate, and to modify the shape of the end of the first layer polyS1 (83, 84) gate to improve the breakdown voltage. ing. In this state, as shown in Figure 11, the first skin pol
On the yS1 layer 83.84, there is a Sin of about 0.3/Jffl.
, films 85 and 86 are coated with approximately 0.2 μm of 5iO on the first polyS1 layer 91 and the source and drain n+ diffusion layers.
One film (102, 104 to 112) is formed.

As mentioned above, the gate electrode is made of a material that can withstand high temperatures, such as polysilicon, and MO8 is used as shown in FIG.
After forming the device, an oxide film is formed on this gate electrode using a low-temperature oxidation method, and a thin SIO film is formed on the Sl substrate (well).
, the film is removed, and the film is placed on the substrate again at 810. A film is formed, a &C8l*Na film is formed thereon, and a gate electrode of polySt is partially formed thereon, and the process described in 31. Oxidize the polySt gate surface using N4M as a mask to form an oxide film,
Using this oxide film as a mask, 8% of the N4 film was removed and the first
By adopting the method of forming the MN08X element as particularly shown in FIG. 1, the MNO8 element is formed after the MOS, so that the deterioration of the characteristics of the MNO8 element is reduced. Furthermore, since the selective oxidation method is applied to cover the gate of the MOS or MNOS with an oxide film, a device with favorable characteristics such as interlayer breakdown voltage or interlayer capacitance can be obtained.

In this way, the MNO8 element is formed, and when the MNO8 element forming part and the MO8 element forming part are drawn using enlarged cross-sectional views in FIG. 11 and in particular, FIGS.
It will look like the figure. That is, as shown in FIG.
A very thin layer 310 of Si, N, and a polysilicon layer 91 partially deposited on the film 90.
is formed, impurities for source/drain formation are introduced into the substrate surface using this polysilicon layer as a mask, and then, as shown in FIG. 31, the surface of this polysilicon layer 91 is oxidized using 818N411JI as a mask. A relatively thick oxide film (Sin) 102 is formed. Furthermore, as shown in FIG. 32, the formed oxide film 10
2 as a mask, the Sl and N4 films 90 are partially etched away. At this time, thin StO.

1[88 is also removed from the substrate surface, but as shown in FIG.
Form 05. Depending on the combination of the gate electrode material, 81, N, and film etching solution (or gas), there is a risk that the gate electrode will also be etched, but after patterning the gate electrode as described above, the Si, N, and film are masked. [The gate electrode is oxidized and covered with an oxide film. This oxide film is used as a mask to etch the Sl, N, and film, so even if the gate electrode material is etched with Si3N4 etching solution, this method protects the fine gate electrode. can do. Further, as shown in FIG. 33, slo on the polysilicon layer 91, S10. 81. with membranes 104 and 105. N, membrane 9
0 is completely covered, so by performing sufficient oxidation treatment in this way, [, so-called protected game] (p
Since a protected gate structure can be formed in a self-aligned manner, the gate breakdown voltage of the MNO8 element can be improved and the parasitic capacitance can be reduced.

Furthermore, as can be understood from FIGS. 30 to 33, by forming pixel elements of 8 MNO elements and 8 MO elements on the same semiconductor substrate, and leaving the Sl and N4 films 90 only under the gates of the 3 MNO elements, As shown in FIG. 33, in the oxidation treatment performed to improve the gate breakdown voltage of the MO8 element, the end of the gate electrode of the MO8 element is also oxidized, creating an inverted canopy structure, which increases the gate breakdown voltage of the MO8 element. As a result, the gate breakdown voltage of both types of devices can be improved.

4. Next, after completing the steps shown in Figure 11-1, it is necessary to use the photoetching method to make electrical connections with the N+ layer or polysL layer below with each of the above oxide films, as shown in Figure 11 (2). If there is, for example (106, 112) and a predetermined part that needs to make contact with the p-type reel, for example 810. of (110° 111). Remove the film by etching. In this case, about 0.3 μm of 810. Because film etching is performed, the oxide film in the part that makes contact with the p-type well is only partially etched, and the thickness of the oxide film is approximately 0.3
A µm Sin film remains.

0 After that, after removing the photoresist film used in the above step, P10m! Phosphosilicate glass (hereinafter referred to as phosphorus glass) 2 of approximately 1 mole per degree
After that, heat treatment was performed at 900°C for 20 minutes in H2 atmosphere to densify the phosphorus glass and MNO
Improved the characteristics of 8 elements.

Thereafter, the areas where electrical connections need to be made with the N+ layer, polysilicon layer, p-type well layer, etc. described above are removed by a phosphorus photoetching method. At this time, holes in the oxide film (114 to 11B) were opened to the light.
The holes in the phosphor glass share at least a part of the area, and the St substrate surface or po
Expose the lysi surface. In this state, the parts (116, 117, 60) that make contact with the p-type well have
Although the film thickness slightly decreases due to over-etching during photo-etching, there is still a StO film of approximately 0.62 μm remaining, so the photo-etching method is used to fill 11 of the previously drilled holes in the phosphor glass. The remaining STO film of about 0.2 μm is removed by etching so that the hole in the photoresist is aligned.

When making contact holes in a two-layer film of phosphor glass and SIO*Jll[, the etching speed of phosphor glass is fast.
Due to the slow etching speed of StO, there are processing problems such as the size of the hole becoming large or the adhesion between the photoresist and the phosphor glass worsening if the two-layer film is drilled at once. As can be seen from the explanation of Figure 1100 and the partially enlarged diagrams of Figures 34 to 36, first, a hole (119) is formed in the Sio film (105) on the surface of the substrate by etching using a contact mask. )
After that, phosphor glass (120) is deposited, and then a hole is drilled in the phosphor glass 1120 so as to share at least a part of the contact hole 119, and a hole 125 is formed.
By setting K so as to provide , the drilling can be performed with higher precision than the design value. In addition, the 36th
In the figure, the hole 125 of the phosphor glass is S io, and the hole 1 of the membrane
19 is shown, but in order to prevent metal wiring such as aluminum from breaking, it is necessary to expose all the holes 119 of the film, and preferably even the end surface of the 5101 film. It is preferable to form a hole 125 made of phosphor glass.

[F] Next, after removing the photoresist used above, a KAA vapor-deposited film is formed on the entire surface at about 300°C. The film thickness is approximately 0.8 μm.

Next, a wiring pattern is formed on the At film by photoetching as shown in FIG.
After removing the photoresist,
In order to ensure contact with poly Si or p-type well and to reduce the surface state, H2
Heat treatment is performed at about 450° C. for 60 minutes in an atmosphere.

By completing the steps (6) to [F] described in detail above, as shown in FIG. Together with the depletion type MO8 element having the above structure, an NPN bipolar transistor consisting of the semiconductor region 97.11.1 can be formed in and on one semiconductor substrate 1 without increasing the number of special photomasks. In addition, 121 in the same figure is E
122 is the emitter electrode of the bipolar transistor, 123 is the base electrode of the transistor and the electric mark of the p-type reel region 11, and 124 is the electrode of the region 22 and the substrate. .

FIG. 15 shows a plan view of the memory array before forming the phosphor glass layer, and FIG. 16 shows a plan view of the memory array after forming the aluminum wiring. Also the first
7, FIG. 18, and FIG. 19 respectively show a section taken along line AA, section taken along line BB, and section taken along line CC of the plane shown in FIG. 16.

The memory array consists of P
It is formed on the mold twill region 10a.

In the gls diagram, the source region, drain region, and channel region of the MNOS of the memory cell and the switch MISFET are shown separated by dotted @ lines. Areas CHI and CH2 surrounded by the dashed line above
A thick silicon oxide film 60 is formed on the other surfaces of the P-type well region 10a.

On the surface of the Pm well region 10a, a plurality of polycrystalline crystals are formed on the surface of the Pm well region 10a in a direction crossing the areas CHI and CH2 through a silicon oxide film, and are used as gate electrodes of MISFETs for switching memory cells and as first word lines. Silicon layer Wl
1, W21, WB2°W41 are arranged.

Similarly, a plurality of polycrystalline silicon layers Wl 2 serve as gate electrodes of MNOS of memory cells and serve as second word lines.
, W22, W32, and W42 are arranged.

Area CHI not covered by each of the above polycrystalline silicon layers
, nm impurities are introduced into the surface of the pi mirael region 10a in CH2 by the manufacturing method explained above with reference to FIG.
n'JM regions are formed to serve as source and drain regions.

At the internal pressure of area CHI, the n+ type region 92a, the polycrystalline silicon layers Wll, W12, and the n+ type region 92a constitute the first memory cell. In other words, the n+ type region 92a
, constitutes the drain region of the switching MISFET,
Polycrystalline silicon layer W11 constitutes the gate electrode.

Further, the polycrystalline silicon layer W12 constitutes a gate electrode of the MNOS, and the n-type region 94a constitutes its source region.

Within the area CHI, the n+ type region 92b polycrystalline silicon layer W21. is adjacent to the first memory cell. W
22 and n+ type region 94b constitute a second memory cell. That is, 92b above.

W21. W22 and 94b are MI8 for switch respectively.
It forms the drain region of the FET, the gate electrode thereof, the gate electrode of the MNOS, and the source region thereof.

Similarly, within the area CH1, 94c.

W32. WB2,92c constitutes a third memory cell,
92d, W41, W42, and 94d form a fourth memory cell.

First to fourth memory cells are also formed in the area adjacent to the area CHI, although no symbols are attached thereto.

Each memory cell formed within the area CHI constitutes a first memory cell column, and similarly each memory cell formed within the area CH2 constitutes a second memory cell column.

The polycrystalline silicon layer Wll as the first word line
As shown in FIG. 5, an extended portion Wl extends across the bottom of the polycrystalline silicon layer W12 on the thick silicon oxide film 60.
I have either LA or Wllc.

Since the polycrystalline silicon layer W12 constitutes the second word line as described above, the voltage of +25V is applied when writing the storage information.
will be exposed to high voltages such as Therefore, a parasitic channel may be induced in the surface of the P-type well region 10a under the polycrystalline silicon layer W12. The polycrystalline silicon layer W11 constitutes a first word line and receives a low voltage signal such as +5V mentioned above. Therefore, the parasitic channels induced on the surface of the Pm well region 10a under the polycrystalline silicon layer W12 are blocked under the extensions W11m to W11c of the polycrystalline silicon layer Wll, respectively.

As a result, the memory cells in the areas CH1 and CH2 are electrically coupled to each other by the parasitic channels, and as a result, it is possible to prevent an undesirable operation such as not writing information to the selected memory cell. .

A phosphorus glass layer 120 is formed on the surface of the memory array shown in FIG. 15 by the manufacturing method described in FIG. Open hole CNTl exposing the area
to C5 (see FIG. 6) are provided.

Next, aluminum is deposited and selectively etched to form an aluminum wiring layer EDI as shown in FIG.
, ED2, DI and D2 are formed.

The wiring layer EDI has the openings CNT1 and CN, respectively.
In T3 and CNT5, the n++ region 94 serves as the source region of the MNOS in the first to fourth memory cells.
a, 94b, 94c and 94d (see FIG. 15) K contact. Therefore, this wiring layer EDI constitutes a reference potential line of the memory array.

The wiring layer D1 has the above-mentioned open holes CNT2 and CNT4, respectively.
In this step, the n+ type regions 92m92b, 92c, and 92d, which serve as drain regions of switch MISFETs in the first to fourth memory cells, are contacted. Therefore,
This wiring D1 constitutes a digit line of the memory array.

Similarly, wiring layers ED2 and ED02 constitute other reference potential lines and digit lines, respectively.

As shown in FIG. 15, the above memory array has an MNOS and a switching M
The arrangement with the ISFET is alternately reversed. Therefore,
For example 92a and 92b.

As in 94b and 94c, the n+ type regions of adjacent memory cells can be shared, and the dimension in the column direction can be made smaller than when the n+ type regions for each memory cell are formed independently. I can do it.

Also, as shown in FIG. 16, an area C where memory cells are formed
Aluminum wiring layers EDI, ED2 . DI, D2 to the above areas CHI, CH
2 is inclined with respect to the extending direction, the dimension in the row direction, that is, in the lateral direction of the paper surface, can be made smaller than in the case where the wiring area is set independently of the above-mentioned area.

In addition, since an aluminum wiring layer is used as the reference potential line and the digit line as shown in the figure instead of using a semiconductor such as an n++ semiconductor wiring area, the resistance thereof can be made sufficiently small. The reduction in interconnect resistance allows the memory array described above to operate at high speeds.

Fig. 20 shows the pattern of the unit X decoder before forming the phosphor glass layer, and Fig. 21 shows the pattern after forming the aluminum wiring layer in the portion corresponding to Fig. 20 above. .

Since each of the unit X decoders is provided corresponding to a memory cell row of the memory array, each of the unit X decoders is taken into account so as not to increase the pitch of the memory cell rows. Therefore, although not particularly limited, as described below, in FIGS. 20 and 21, the combination of two unit X decoders is substantially one unit.

In FIG. 20, the X decoder consists of an n-type silicon substrate l
It is formed on the P-type well region 11 formed above. The area for forming each MI8FET is surrounded by a dashed line in the figure. A thick silicon oxide film 60 is formed on the surface of the P-type well region 11 other than the above-mentioned region, as described above.

On the silicon oxide film 60 and the gate oxide film on the region surrounded by the dotted chain line, a first polycrystalline silicon layer Wl having a pattern as shown by the combination of dots and solid lines is formed.
1, W21, aO, aO'a1. at' is formed. Of the region surrounded by the above-mentioned dashed-dotted line, an n+ type region is formed by the manufacturing method shown in FIG. 11 above except under the above-mentioned polycrystalline silicon layer.

In FIG. 20, the enhancement type MI8F
This means that the channel region of the ET is formed, and the channel region of the deep-plunge MISFET is formed under the polycrystalline silicon layer in the area where the two diagonal lines on the lower left and lower right sides are combined. This means that it is formed.

In the upper half of the paper in FIG. 20, the n+ type region VC
Ca, polycrystalline silicon layer Wll, and n+ type region Wllb constitute a deep-plunge type MISFETQ3, and n+ type region Wllc, polycrystalline silicon layer aO' and n
Enhancement WMIS by + type area GNDa
FETQ4 is configured, and enhancement type MISFETQ5 is configured by n+ type region W11c, polycrystalline silicon layer al', and n+ type region GNDb.

Similar MISF in the lower half of the paper in Figure 20
ETQ3', Q4' and Q5' are constructed.

As shown in FIG. 21, a phosphor glass layer 120 is formed on the surface of the decoder shown in FIG. 20, and then holes are formed in the phosphor glass layer and the oxide film thereunder by selective etching.

By aluminum evaporation and selective etching, the 21st
Various aluminum wiring layers are formed as shown in the figure. In FIG. 2, the openings provided in the phosphor glass layer and the insulating film such as the oxide film are indicated by X marks. Therefore, each of the aluminum wiring layers contacts the polycrystalline silicon layer or semiconductor region below at the X-marked portions.

In FIG. 21, a wiring layer Wlla is a wiring layer for short circuiting, and includes a polycrystalline silicon layer Wll as a gate electrode of MISFETQ3 (see FIG. 20), its source region, and the MISFETQ4. The CI region wixb as a common drain region of Q5 is short-circuited. Wiring layer V
CC is the wiring H for the power supply, and is the common drain region of MI8FETQ3 and Q3' (see Figure 20).
+It is in contact with the star region VCCa. The wiring layer GND is a wiring layer for grounding, and is in contact with the n+ type region GNDa as a common source region of MI 5FETQ4 and Q4'. In addition, as shown in FIG. 20, MI 5FETQ5. Q
The n+fJ region GNDb serving as the common source region 5' is continuous with the n+ type region GNDaK.

Wiring) 4tA aO and aO are a pair of wiring layers that receive address signals of mutually opposite phases, and the selected one of them, that is, aO in the illustrated case, is connected to the polycrystalline silicon layer aO.
' and aO''.

Similarly, the wires f@a 1 and al are a pair of wires fRN that receive other address signals having mutually opposite phases. In the case shown,
The wiring layer a1 is in contact with the polycrystalline silicon layer al', and the wiring layer a1 is in contact with the polycrystalline silicon layer 81''.

As described above, a unit decoder such as the X decoder XDI in the m1 diagram is configured in the upper half of FIG. 12, and other unit decoders such as XD2 are configured in the lower half.

The unit X decoder has a pair Fl for each memory cell row.

It can be arranged as follows. Therefore, the wiring layer VCC, GND.

aO, ao, al, al, etc. are common to a plurality of unit X decoders.

FIG. 22 and FIG. 22B show the pattern of the unit write circuit before forming the phosphor glass layer, and the second
Figure 3 Person and Figure 23 B are the above Figure 22 Person and Figure 2, respectively.
2 shows a pattern after forming an aluminum wiring layer in a portion corresponding to FIG. 2B. The right end of the pattern of the person in Figure 22 is connected to the left end of Figure 22B, and similarly the right end of the person in Figure 23 is connected to the left end of Figure 23B.

The patterns in FIGS. 22A and B and FIGS. 23A and B are shown using the same notation as in FIGS. 20 and 21.

For the same reason as the X decoder, the two unit write circuits are essentially one unit.

A polycrystalline silicon layer W serving as a first word line is extended over a P-type well region 10b indicated by a two-dot chain line for configuring a memory array through a thick silicon oxide film 60.
ll and W21 are aluminum wiring layers WIIC, respectively.
, W2IC formed in the P-type well region 11
Drain region W of ISFETQl 5, Ql 5'
ild, contacts W21d.

As shown in the figure, an aluminum wiring layer e to which a signal from an erase circuit (see FIG. 1) is applied is in contact with the P-type well region 10b.

A signal from a control line We (see FIG. 1) is applied to the polycrystalline silicon layer We serving as the gates of the MISFETs QI 5 and Ql 6.

Polycrystalline silicon layer W12°W22 as second word line
are aluminum wiring layers W12a, respectively.

MI 5FET QI 6 and Ql 7 formed in the P-type well region 11 shown by the two-dot chain line through W22a
The common drain region W12b of the MISFETs Q16' and Q17' is in contact with the common drain region W22b of the MISFETs Q16' and Q17'.
K is in contact.

The above MISFETQ16, Ql7, Q16'Q17
'The polycrystalline silicon layer VCC as a common gate has +
A power supply voltage of 5V is applied.

Common drain region G of MI8FETQ18 and Q18'
NDa has an aluminum wiring layer GN that is set to the ground potential.
D is in contact.

The polycrystalline silicon layer W12c is an independent P-type well region 1.
It is used as the gate electrode of MISFET Ql 9 formed in MISFET Ql 1r, and is in contact with the source region W12e of MISFET Ql 9 and the P-type well region 11r through the aluminum wiring layer Wl 2d.

Similarly, the polycrystalline silicon layer W22c connects the MI 5FET QI 9 formed in another independent P-type well region 11m.
' is used as the gate electrode of the aluminum plate W2.
2d6'C is in contact with the source region W22e of the MISFET Q19' and the P-type well region 11a.

The MISFETs QI9 and Q19' have the structure as explained in FIG. 9 or FIG. 11 above. n
The above MI 5FETQ extended on the type silicon substrate l
The common drain region VPPa of I 9 and Ql 9' is in contact with an aluminum wiring layer VPP to which a high voltage for writing and erasing is applied.

For example, the circuit WAI in FIG. 1 is configured by the MI 5FETQI 5 to Ql9,
Another circuit WA2 is configured by l9'.

The unit write circuits shown in FIGS. 22A and 22B and FIGS. 23A and 23B are arranged in correspondence with memory cell rows, similar to the X decoder described above.

FIG. 24 shows the pattern of the Y gate before forming the phosphor glass layer, and FIG. 25 shows the pattern of the portion corresponding to FIG. 24 after forming the aluminum wiring layer.

In the polycrystalline silicon layer CD as a common digit line,
Aluminum wiring layer C for connecting unit gates in parallel
Da is in contact.

The above aluminum wiring layer CDa is MISFETQII
and Ql3 are in contact with the common drain region CDb. The polycrystalline silicon layer Yla serves as the gate electrode of the MI8FETQ11 and Ql3.

Y2aK are Y decoders MDI and YD2 (first
(See figure) Aluminum wiring layers Yl and Y2 that receive the output
are in contact.

The source region of MI 5FET QI 1 and the drain region of Ql2 are made into a common n+ type region Dlb, and similarly MI8
The source region of FET Q13 and the drain region of FET Q14 are co-progressive n+ type regions.

A +5V power supply voltage is supplied to the polycrystalline silicon layer vCC serving as the gate electrode of the MISFETs QI2 and Ql4.

The source region Dla of MI8FETQ12 is in contact with an aluminum wiring layer D1 as a digit a, and similarly, the source region D2a of MISFETQ14 is in contact with an aluminum wiring layer D1 as a digit line in degrees Celsius.

FIG. 26 and FIG. 26B show the pattern of the write inhibit circuit before forming the phosphor glass layer, and FIG.
Figure 26 and Figure 27B show the patterns of the portions corresponding to Figure 26 and Figure 26B, respectively, after the aluminum wiring layer has been formed. As a pattern, the lower end of the person in Figure 26 is connected to the upper end of Figure 26B, and similarly the lower end of the person in Figure 27 is connected to the upper end of Figure 27B.

As shown in FIG. 6, since the wiring region WIR is arranged between the memory array and the write inhibit circuit, the aluminum wiring layer ED1 as the reference potential line explained in FIGS. 15 and 16 is not particularly limited. , ED2 is each MISFE
Polycrystalline silicon/#ED1a formed simultaneously with the polycrystalline silicon layer of T.

ED2a K are contacted respectively. Above wiring area W
In TR, the polycrystalline silicon layers EDla, B
Various aluminum wiring layers are formed on Dia via an oxide film and a phosphorous glass layer.

Note that the figures A and B in Figure 26 and people and B in Figure 27 are shown using the same notation as in each of the figures above. Therefore, the second
A description of the structure of the write inhibit circuit in FIGS. 6A and 6B and FIGS. 27A and 27B will be omitted.

According to this invention, as shown in FIG. 6, since the decoder and the write circuit are placed across the memory array, the operation speed, particularly the read operation speed, can be increased. On the other hand, if the decoder and write circuit are placed on one side of the memory array, the wiring from the decoder to the memory cell becomes long, and multiple circuits are placed on one side of the memory array, so it is difficult to The number of well-known cross-wiring locations will increase. As a result, the signal transmission characteristics of the wiring paths that supply signals to the memory array deteriorate, and the operating speed is limited.

As mentioned above, when placing the decoder and write circuit across the memory array, the pitch between the unit decoder and write circuit can be made relatively small, so the size of the memory array does not have to be limited by these circuits. Become good.

Furthermore, since the gate or decoder and write inhibit circuit are arranged across the memory array, high-speed operation can be achieved for the same reason as above.

As mentioned above, the configuration in which a decoder and a write circuit are placed across a memory array, or the configuration in which a gate or a decoder and a write circuit are placed across a memory array, uses a write circuit or a write inhibit circuit. It can be applied to the following types of storage devices.

According to the invention, using the well region as described above,
This well region can be effectively used for high voltage circuits.

In the voltage divider circuit in which the enhancement WMISFETs Q37 to Q39 of FIG. 1 are connected in series, MI
Since the highest voltage is applied to the drain of SFETQ37, if this MI5FETQ37 is destroyed by high voltage, "CQ" is applied through this destroyed MISFETQ37.
A high voltage will be applied to 3B. As a result, the MI 5FETs connected in series are destroyed one after another. However, if MI5FETQ37, to which the highest voltage is applied, is made to have a structure that utilizes the shell region as described above to achieve a high withstand voltage, other MISFETQ3B to Q39
Even if it has a normal structure, the above type of destruction can be prevented. The voltage divider circuit as described above can be used in circuit devices other than the memory circuit device of the embodiment.

Similarly, circuits such as the erase circuit and write inhibit voltage generation circuit shown in FIG. 1 can be used for other purposes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory circuit, FIGS. 2, 3, and 4 are operation timing charts of the circuit in FIG.
5 is a block diagram of a semiconductor memory circuit, FIG. 6 is a plan view of a semiconductor memory circuit device, FIG. 7 is a plan view of a semiconductor substrate forming the semiconductor memory circuit device of FIG. 6, and FIG. 8 is a plan view of a semiconductor memory circuit device. Figure 7 is a cross-sectional view of the person-A1 portion, Figure 9 is a MISFET
10 is a sectional view of a semiconductor substrate on which a bipolar transistor is formed, FIG. 11 rA) or 0) is a sectional view of a semiconductor substrate in each manufacturing process of a semiconductor memory circuit device, Figure 12 shows the MN OS
(IF) M plane view, Figure 13 tlE12 MNOS characteristic curve diagram, Figure 14 is the equivalent circuit diagram of the memory cell, Figure 1
5 is a plan view of the memory array before forming the phosphor glass layer, FIG. 16 is a plan view of the memory array after forming the aluminum wiring layer, and FIGS. 17, 18, and 19 are 816 Figure 17) A-A' section, B-B' section, and c-c' s cross-sectional view, Figure 20 is a plan view of the X decoder before forming the phosphor glass layer, and Figure 21 is the aluminum wiring. A plan view of the X-decoder after forming the layers, FIG. 22 and FIG. 22B are plan views of the write circuit before forming the glass layer, FIG. 23 and FIG. 23B are forming the aluminum wiring no. 24 is a plan view of the Y gate before forming the phosphor glass layer, FIG. 25 is a plan view of the Y gate after forming the aluminum wiring layer, and FIG. 26 is a plan view of the write circuit after forming the write circuit. Figures 26 and 26B are plan views of the write-protection circuit before forming ring glass snow, Figures 27 and 27B are plan views of the write-protection circuit after shaping the aluminum wiring layer, Figures 28 and 29 show 5t-sto, phosphorus at the interface, respectively.
The state diagrams illustrating the concentration distribution of boron impurities, FIGS. 30 to 33, and 34 to 36 are cross-sectional views of the main parts of the semiconductor device at each manufacturing process. MA...Memory array, XDI, XD2...X decoder, YGO...Y gate, YDI, YD2...
X decoder, WAI, WA2...Writing circuit, IH
Al...Write inhibit circuit, IHA2...Write inhibit voltage generation circuit, ER8...Erase circuit, CRL...
・Control circuit, IO8...Sense circuit, IOR...Output buffer circuit, IOW...Data input circuit, BO~
BIO...Input buffer circuit. Fig. 2 Fig. 3 τ/l ・ζ1 Seated figure Fig. Fig. Fig. Fig. Fig. 22 B Fig. 23 Fig. 8 Fig. 26 A Basket 27 Fig. A もZ ゛8 fig. 29 fig. fig.? 3.3.

Claims (1)

[Claims] 1. A method for manufacturing a semiconductor device including an MNOS element, which includes the steps of: forming a lower layer film of oxide and an upper layer film of silicon nitride covering the main surface of a semiconductor substrate; forming a semiconductor layer for a gate electrode on the film; and forming regions to become a source and a drain on the main surface of the semiconductor substrate by introducing impurities into the main surface of the semiconductor substrate using the semiconductor layer for gate electrode as a mask; and then forming an oxide film by oxidizing the surface of the gate electrode semiconductor layer using the silicon nitride film as an oxidation-resistant mask, and forming an oxide film on the surface of the gate electrode semiconductor layer. a step of removing the silicon nitride film exposed from the gate electrode semiconductor layer using the oxidized oxide film as an etching mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of removing the silicon nitride film, the surfaces of the source and drain regions are oxidized.