JP2004342720A - Semiconductor device including nonvolatile memory - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device including a plurality of nonvolatile memories in which the operating speed can be enhanced while reducing the area of the peripheral circuit. <P>SOLUTION: The semiconductor device comprises a plurality of nonvolatile memories 100 arranged in the row direction and the column direction intersecting the row direction. The nonvolatile memory 100 comprises a gate insulation layer 22 provided on the channel region of a semiconductor layer 10, a gate conductive layer 14 provided on the gate insulation layer 22, first conductivity type first and second impurity regions 34 and 24, and a bit conductive layer 80. The bit conductive layer 80 connects the second impurity regions 24 of the memory cell 100 arranged in i row [j+1] column electrically with the first impurity regions 34 of the memory cell 100 arranged in [i+1] row [j+1] column. A charge storage region is provided in the vicinity of one end part of the gate conductive layer 14 in a charge capturing layer 22b and not provided in the vicinity of the other end part thereof. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

[0001]
TECHNICAL FIELD OF THE INVENTION
The present invention relates to a semiconductor device including a nonvolatile memory device that stores data by capturing charges (carriers) in a gate insulating layer including an electron capturing layer.
[0002]
[Background Art]
As one type of the nonvolatile memory device, for example, a gate insulating layer including a silicon oxide layer, a silicon nitride layer, and a silicon oxide layer is formed between a channel region and a gate conductive layer, and the silicon nitride layer transfers electric charges. There is a type called a MONOS (Metal Oxide Nitride Semiconductor) type or a SONOS (Silicon Oxide Nitride Oxide Silicon) type (for example, see Patent Document 1).
[0003]
In such a nonvolatile memory device memory cell, when control of the memory cell is complicated, a peripheral circuit for controlling the memory cell is complicated. As a result, the area of the peripheral circuit increases, which may hinder miniaturization. Further, the complexity of the memory cell control contributes to a decrease in the operation speed of the memory cell.
[0004]
[Patent Document 1]
JP 2001-118943 A
[0005]
[Problems to be solved by the invention]
An object of the present invention is to provide a semiconductor device including a plurality of nonvolatile memory devices, which can achieve an improvement in operation speed and a reduction in peripheral circuit area.
[0006]
[Means for Solving the Problems]
(1) The semiconductor device of the present invention comprises:
Including a plurality of nonvolatile storage devices arranged in a row direction and a column direction intersecting the row direction,
The nonvolatile storage device,
A gate insulating layer provided on the channel region of the semiconductor layer, the gate insulating layer including a first insulating layer, a charge trapping layer, and a second insulating layer;
A gate conductive layer provided on the gate insulating layer,
First and second impurity regions of a first conductivity type provided in the semiconductor layer so as to sandwich the gate conductive layer;
The second impurity region of the nonvolatile memory device arranged in the i-th row and [j + 1] column and the first impurity region of the nonvolatile memory device arranged in the [i + 1] -row and [j + 1] column are electrically connected. A bit conductive layer to be connected (i and j are integers of 1 or more);
Including
The charge trapping layer has a charge storage region near one end of the gate conductive layer, and has no charge storage region near the other end.
[0007]
According to the semiconductor device, the bit conductive layer has the second impurity region of the nonvolatile memory device arranged in the i-th row [j + 1] column and the non-volatile memory region arranged in the [i + 1] -row [j + 1] column. By electrically connecting the first impurity region of the storage device, bit lines and word lines to which a voltage is applied during writing and erasing are limited. Thereby, even if the non-volatile memory devices adjacent in the column direction share a word line and the non-volatile memory devices adjacent in the row direction share a bit line, other than the selected non-volatile memory device Erroneous writing and erasing of cells can be effectively prevented. As described above, the nonvolatile memory device having excellent reliability can be obtained.
[0008]
Further, a peripheral circuit for controlling the nonvolatile memory device can be further simplified. As a result, the area of the peripheral circuit can be reduced, and the operation speed of the nonvolatile memory device can be improved. Details will be described in the section of the present embodiment.
[0009]
(2) In the semiconductor device, the first impurity region includes a first-conductivity-type high-concentration impurity region provided in the semiconductor layer near one end of the gate conductive layer; The region may have a higher concentration of the first conductivity type impurity than near the other end of the gate conductive layer in the semiconductor layer.
[0010]
In this case, the second impurity region includes a first conductivity type low concentration impurity region provided near the other end of the gate conductive layer in the semiconductor layer, and the second impurity region includes the high concentration impurity region and the low concentration impurity region. The impurity region is disposed so as to sandwich the gate conductive layer, and the low-concentration impurity region can have a higher concentration of the first conductivity type impurity than the high-concentration impurity region.
[0011]
In this case, the semiconductor device may further include a third impurity region of the second conductivity type adjacent to the high-concentration impurity region on a side closer to the channel region.
[0012]
(3) In the above-described semiconductor device, two non-volatile memory devices adjacent to each other in a row direction may have a common first impurity region or second impurity region.
[0013]
In this case, the semiconductor device may further include a first contact portion provided on the common first impurity region and a second contact portion provided on the common second impurity region.
[0014]
Further, in this case, the first contact portion is formed on a common first impurity region between the nonvolatile memory device arranged in the i-th row and the j-th column and the nonvolatile memory device arranged in the i-th row and the [j + 1] column. And the second contact portion is common to the nonvolatile memory device arranged in [i + 1] row [j + 1] column and the nonvolatile memory device arranged in [i + 1] row [j + 2] column. Being provided on a second impurity region, the bit conductive layer electrically connects the common first impurity region and the common second impurity region via the first and second contact portions. Can be.
[0015]
(4) In the semiconductor device, the gate conductive layer may extend in a column direction.
[0016]
(5) In the semiconductor device, the two nonvolatile memory devices adjacent to each other in the column direction may be electrically separated by an element isolation region.
[0017]
In this case, the element isolation region may have a polygonal line shape. In this case, a plurality of the element isolation regions are included, and the distance between two adjacent element isolation regions can be equalized.
[0018]
The semiconductor device, wherein the bit conductive layer has a portion extending in a direction crossing a row direction and a column direction.
[0019]
(6) In the above semiconductor device, the bit conductive layer may have a polygonal planar shape.
[0020]
(7) In the above-described semiconductor device, a plurality of the bit conductive layers are included, and a distance between two adjacent bit conductive layers can be equalized.
[0021]
(8) In the semiconductor device, a buried insulating layer may be formed above the nonvolatile memory device, and the bit conductive layer may be provided above the buried insulating layer.
[0022]
(9) In the semiconductor device, the first and second insulating layers may be made of silicon oxide, and the charge trapping layer may be made of silicon nitride.
[0023]
(10) The semiconductor device further includes a control circuit of the nonvolatile storage device,
The control circuit includes:
At the time of writing, a high-level voltage is applied to the gate conductive layer, a low-level voltage is applied to the second impurity region, and a high-level voltage is applied to the first impurity region. Injecting a first conductivity type hot carrier into the charge trapping layer,
At the time of reading, carriers of the first conductivity type can flow through the channel region in a direction opposite to that at the time of writing.
[0024]
In this case, at the time of writing, the control circuit applies a voltage to the gate conductive layer and the bit conductive layer that are electrically connected to the selected non-volatile memory device, and applies the voltage to the non-selected non-volatile memory device. No voltage can be applied to the gate conductive layer and the bit conductive layer that are connected to each other.
[0025]
BEST MODE FOR CARRYING OUT THE INVENTION
Next, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view schematically showing a semiconductor device according to one embodiment of the present invention. FIG. 2 is a diagram schematically showing a cross section taken along line AA of FIG.
[0026]
As shown in FIG. 1, the semiconductor device of the present embodiment includes a memory cell array including a plurality of nonvolatile memory devices (memory cells) 100. FIG. 2 shows a cross section of the memory cell 100 shown in FIG.
[0027]
[Plane structure]
First, the planar structure of the semiconductor device of the present embodiment will be described mainly with reference to FIGS.
[0028]
FIG. 3 is a schematic circuit diagram of the semiconductor device shown in FIG. As shown in FIG. 3, a plurality of word lines WL (WL _j , WL _{j + 1} , WL _{j + 2} , WL _{j + 3} ..) And a plurality of bit lines BL (BL _i , BL _{i + 1} , BL _{i + 2} , BL _{i + 3} , BL _{i + 4} ..) Are arranged above the semiconductor layer 10 so as to cross each other. Note that the bit line BL shown in FIG. 1 corresponds to the bit conductive layer 80, and the word line WL is connected to the word conductive layer 14 shown in FIG.
[0029]
These bit lines BL are connected to a bit line driver BD and selectively receive a driving voltage. These word lines WL are connected to a word line driver WD and selectively receive a scanning voltage. A control circuit of the memory cell 100 such as the bit line driver BD and the word line driver WD can be formed in the same semiconductor layer 10 as the memory cell array shown in FIG.
[0030]
As shown in FIG. 1, each word line WL extends in the column direction. Further, the first impurity regions 34 and the second impurity regions 24 are alternately arranged between two adjacent word lines WL. For example, WL _j And WL _{j + 1} And a second impurity region 24 is disposed between _{j + 1} And WL _{j + 2} Between the first impurity region 34 and the WL _{j + 2} And WL _{j + 3} The second impurity region 24 is disposed between the first and second regions.
[0031]
As shown in FIG. 3, a memory cell 100 is connected to each intersection of a word line WL and a bit line BL. In the memory cell array shown in FIG. 1, a plurality of memory cells 100 are arranged in a row direction and a column direction intersecting the row direction. This embodiment shows a case where the row direction and the column direction are orthogonal to each other.
[0032]
In FIGS. 1 and 3, the memory cell 100 arranged at the i-th row and the j-th column is referred to as “T _ij (I and j are integers of 1 or more). Here, “memory cell (T _ij ) "Means the i-th bit line BL _i And the [i + 1] th bit line BL _{i + 1} And its gate conductive layer is connected to the j-th word line WL. _j (See FIG. 3).
[0033]
Also, as shown in FIG. 1, two memory cells 100 adjacent in the row direction have a common first impurity region 34 or a common second impurity region 24. Specifically, for example, as shown in FIG. _{i + 1, j + 1} And T _{i + 1, j + 2} Have a common first impurity region 34. Further, memory cells T adjacent in the row direction _{i, j} And T _{i, j + 1} Have a common second impurity region 24.
[0034]
Further, as shown in FIG. 1, the first and second impurity regions 34 and 24 are respectively arranged in the column direction. The common first and second impurity regions 34 and 24 adjacent in the column direction are electrically isolated by the element isolation region 12. The element isolation region 12 is made of, for example, STI (shallow trench isolation). On the other hand, the first and second impurity regions 34 and 24 adjacent in the row direction are arranged so as to sandwich the word line WL (gate conductive layer 14) (see FIG. 3).
[0035]
That is, as shown in FIG. 1, the memory cells 100 adjacent in the column direction are electrically isolated by the element isolation region 12. FIG. 1 shows a case where the plurality of element isolation regions 12 extend linearly in the row direction. Further, the distance between two adjacent element isolation regions 12 is substantially equal.
[0036]
The first contact portions C11, C21, C31, C13, C23, and C33 are provided on the common second impurity region 24. The second contact portions C02, C12, and C22 are provided on the common first impurity region 34.
[0037]
Next, the connection structure of the bit line BL (bit conductive layer 80) will be described with reference to FIG. _{i, j + 1} And T _{i + 1, j + 1} Will be described as an example.
[0038]
Bit line BL _{i + 1} (Bit conductive layer 80) _{i, j + 1} (The memory cell 100 arranged in the i-th row [j + 1] column) of the second impurity region 24 and T _{i + 1, j + 1} The first impurity region 34 of (the memory cell 100 arranged in [i + 1] row [j + 1] column) is electrically connected.
[0039]
Specifically, the memory cell T _{i, j + 1} Of the second impurity region 24 and the memory cell T _{i + 1, j + 1} Of the bit line BL via the first contact portion C11 and the second contact portion C12. _{i + 1} (Bit conductive layer 80).
[0040]
The first contact portion C11 is connected to the memory cell T _{i, j + 1} And memory cell T _{i + 1, j + 1} And the second contact portion C12 is provided on the second impurity region 24 common to the memory cell T. _{i + 1, j + 1} And memory cell T _{i + 1, j + 2} Are provided on the common first impurity region 34. Therefore, the bit line BL _{i + 1} The (bit conductive layer 80) electrically connects the common second impurity region 24 and the common first impurity region 34 via the first contact portion C11 and the second contact portion C12.
[0041]
Further, the bit line BL _{i + 1} The (bit conductive layer 80) electrically connects the common first impurity region 34 and the common second impurity region 24 via the second contact portion C12 and the first contact portion C13. The first contact portion C13 is connected to the memory cell T _{i, j + 2} And memory cell T _{i, j + 3} Are provided on the common first impurity region 24.
[0042]
Therefore, the bit line BL (bit conductive layer 80) alternately electrically connects the common first impurity region 34 and the common second impurity region 24 via the first contact portion and the second contact portion. ing.
[0043]
For example, the bit line BL _{i + 1} (Bit conductive layer 80) electrically connects alternately the second impurity region 24 of the memory cell 100 arranged in the i-th row and the first impurity region 34 of the memory cell 100 arranged in the [i + 1] -th row. Connected. Specifically, the bit line BL _{i + 1} Is connected to the memory cell T via the first contact portion 11. _{i, j} And T _{i, j + 1} Of the memory cell T via the common second impurity region 24 and the second contact portion 12. _{i + 1, j + 1} And T _{i + 1, j + 2} Of the memory cell T via the common first impurity region 34 and the first contact portion 13. _{i, j + 2} And T _{i, j + 3} Are electrically connected to the common second impurity region 24.
[0044]
In the memory cell array shown in FIG. 1, specifically, bit conductive layer 80 (bit line BL) has a portion extending in a direction intersecting the row direction and the column direction. Specifically, the bit conductive layer 80 has a polygonal planar shape. Further, as shown in FIG. 1, the distance between two adjacent bit conductive layers 80 is substantially equal.
[0045]
[Cross section structure]
Next, a cross-sectional structure of the memory cell 100 shown in FIG. 1 will be described mainly with reference to FIG.
[0046]
As shown in FIG. 2, the memory cell 100 includes one gate conductive layer 14 (word line WL). _{j + 1} ), The gate insulating layer 22, and the first and second impurity regions 34 and 24. The gate conductive layer 14 is formed on the semiconductor layer 10 with a gate insulating layer 22 interposed. Gate conductive layer 14 is made of, for example, doped polysilicon. Further, sidewall insulating layers 15 can be provided on both side walls of the gate conductive layer 14 (see FIG. 2). The sidewall insulating layer 15 is made of, for example, silicon oxide or silicon nitride.
[0047]
The gate insulating layer 22 is formed by sequentially depositing a first insulating layer 22a, a charge trapping layer 22b, and a second insulating layer 22c. The first insulating layer 22a forms a potential barrier between the channel region and the charge storage region. The charge trapping layer 22b includes a charge storage region for trapping carriers (for example, electrons). The second insulating layer 22c forms a potential barrier between the gate conductive layer 14 and the charge storage region.
[0048]
In the memory cell 100 of the present embodiment, one bit is stored per cell. Specifically, as shown in FIGS. 1 and 2, the charge trapping layer 22b has a charge storage region X. The charge storage region X is formed near one end of the gate conductive layer 14 in the charge trapping layer 22b. On the other hand, no charge accumulation region is formed near the other end of the gate conductive layer 14 in the charge trapping layer 22b (the low concentration impurity region 28 in the charge trapping layer 22b).
[0049]
Charge trapping layer 22b may be, for example, made of silicon nitride, a layer obtained by dispersing metal such as tungsten in the insulating layer such as silicon oxide or silicon nitride or silicon oxide islands of polysilicon is embedded, layer.
[0050]
The gate insulating layer 22 can be made of, for example, an ONO (Oxide-Nitride-Oxide) film. That is, the first and second insulating layers 22a and 22c are made of silicon oxide, and the charge trapping layer 22b is made of silicon nitride.
[0051]
As shown in FIG. 2, the first and second impurity regions 34 and 24 are arranged so as to sandwich the gate conductive layer 14 in the semiconductor layer 10. A channel region is formed in the semiconductor layer 10 in a region between the first and second impurity regions 34 and 24 and below the gate conductive layer 14.
[0052]
Impurities of the same conductivity type (first conductivity type) are introduced into the first and second impurity regions 34 and 24. In this embodiment, a case will be described in which the first conductivity type is N-type and the second conductivity type is P-type. However, these conductivity types may be reversed.
[0053]
The first impurity region 34 has a high concentration impurity region 38 and an impurity region 36. The impurity region 36 is adjacent to the high-concentration impurity region 38. The impurity region 36 is provided at a position farther from the gate conductive layer 14 than the high-concentration impurity region 38 in one memory cell 100.
[0054]
The second impurity region 24 has a low concentration impurity region 28 and an impurity region 26. The impurity region 26 is adjacent to the low concentration impurity region 28. The impurity region 26 is provided at a position farther from the gate conductive layer 14 than the low concentration impurity region 28 in one memory cell 100. This second impurity region 24 has an LDD (Lightly Doped Drain) structure. Specifically, the low-concentration impurity region 28 has a lower N-type impurity concentration than the impurity region 26.
[0055]
As shown in FIG. 1, the high-concentration impurity region 38 is provided near one end of the gate conductive layer 14 in the semiconductor layer 10. The low concentration impurity region 28 is provided near the other end of the gate conductive layer 14 in the semiconductor layer 10. The high-concentration impurity regions 38 and the low-concentration impurity regions 28 are arranged so as to sandwich the gate conductive layer 14, as shown in FIG.
[0056]
Both the high-concentration impurity region 38 and the low-concentration impurity region 28 have the same conductivity type (first conductivity type) impurity introduced therein. In this embodiment, a case will be described in which the first conductivity type is N-type and the second conductivity type is P-type. However, these conductivity types may be reversed.
[0057]
The concentration of the N-type impurity in the high-concentration impurity region 38 is higher than the concentration of the N-type impurity in the low-concentration impurity region 28. That is, since the low-concentration impurity region 28 having a lower N-type impurity concentration than the high-concentration impurity region 38 is provided near the other end of the gate conductive layer 14 in the semiconductor layer 10, the high-concentration impurity region 38 Has a higher N-type impurity concentration than the vicinity of the other end of the gate conductive layer 14 in the semiconductor layer 10.
[0058]
Specifically, the high-concentration impurity region 38 preferably has an N-type impurity concentration at least several times (for example, 3 to 4 times) or more than the low-concentration impurity region 28, and preferably has an N-type impurity concentration 10 times or more. It is more desirable to have
[0059]
Further, as shown in FIG. 2, the third impurity region 32 is formed in a region adjacent to the high-concentration impurity region 38 on the side closer to the channel region in the semiconductor layer 10 made of a P-type semiconductor substrate. Into the third impurity region 32, an impurity of a conductivity type (second conductivity type; P-type) different from that of the high-concentration impurity region 38 is introduced. Here, as shown in FIG. 2, it is desirable that the third impurity region 32 be disposed to a position closer to the center of the channel region than the high-concentration impurity region 38. Even if the third impurity region 32 is not provided, if the N-type impurity concentration of the high-concentration impurity region 38 is sufficiently high and the concentration gradient between the high-concentration impurity region 38 and the channel region is sufficiently large, the memory cell 100 When writing, hot carriers can be injected into the charge storage region X.
[0060]
Further, as shown in FIG. 2, a silicide layer 92 containing a metal such as titanium or cobalt can be formed on the first and second impurity regions 34 and 24 and the gate conductive layer 14. By forming these silicide layers 92, the access speed of the memory cell 100 can be improved.
[0061]
Further, a buried insulating layer 72 is formed on the memory cell 100. A bit conductive layer 80 (bit line BL in FIG. 2) is formed on the buried insulating layer 72. _{i + 1} , BL _{i + 2} ) Is provided. In the cross section shown in FIG. 2, the first contact portion C21 provided on the second impurity region 24 and the bit conductive layer 80 (bit line BL) provided on the first contact portion C21 are provided. _{i + 2} ), A second contact portion C12 provided on the first impurity region 34, and a bit conductive layer 80 (bit line BL) provided on the second contact portion C12. _{i + 1} ). The first and second contact portions are formed of an opening 84 provided in the buried insulating layer 72 and a conductive layer 82 buried in the opening 84.
[0062]
[motion]
As described above, the memory cell 100 stores one bit per cell. Specifically, the charge is stored in the charge trapping region X in the charge storage layer 22b.
[0063]
As described above, in the memory cell 100 of the present embodiment, the high-concentration impurity region 38 of the first impurity region 34 has a higher N-type impurity concentration than the low-concentration impurity region 28 of the second impurity region 24. The high concentration impurity region 38 is formed near one end of the gate conductive layer 14a, and the low concentration impurity region 28 is formed near the other end. Therefore, when charge is introduced into the charge trapping layer 22b, the charge is trapped in the charge trapping region X near the end of the charge trapping layer 22b closer to the high-concentration impurity region 38. On the other hand, in the vicinity of the end of the charge trapping layer 22b closer to the low concentration impurity region 28, the charge is not trapped.
[0064]
Hereinafter, an example of the operation of the memory cell 100 will be described with reference to FIG. Here, the memory cell T shown in FIG. _{i + 1, j + 1} The case in which is selected to perform writing will be described.
[0065]
(1) Write
At the time of data writing, the second impurity region 34 is grounded (V ₂ = Ground potential) by setting the first impurity region 24 and the gate conductive layer 14 to a positive potential (V _GT , V ₁ = Positive potential), hot electrons (N-type hot carriers) are accumulated in the charge trapping region X in the charge trapping layer 22b near the high concentration impurity region 38.
[0066]
The memory cell T of FIG. _{i + 1, j + 1} Write to the charge storage region X of the word line WL _{j + 1} To a positive potential (for example, 7 V) and the word line WL _{j + 1} Other word lines to ground potential. Then, in FIG. _{i + 1} To a positive potential (for example, 5 V) and the bit line BL _{i + 1} Other bit lines are set to the ground potential. Thereby, hot electrons are injected into the charge storage region X.
[0067]
In this case, the memory cell T selected for writing is _{i + 1, j + 1} And memory cells T adjacent in the column direction _{i, j + 1} , The memory cell T for which writing is selected _{i + 1, j + 1} Similarly, the gate conductive layer 14 and the second impurity region 24 have a positive potential, and the first impurity region 34 has a ground potential.
[0068]
However, in the memory cell 100, the low-concentration impurity region 28 of the second impurity region 24 has a considerably lower N-type impurity concentration than the high-concentration impurity region 38 of the first impurity region 34, so that the charge accumulation is performed. No charge is injected into the vicinity of the low-concentration impurity region 28 (the region Y in FIG. 1) in the layer 22b. Therefore, the memory cell T _{i, j + 1} Is not written.
[0069]
(2) Read
At the time of data reading, N-type carriers are caused to flow in the channel region in a direction opposite to that at the time of writing. When a current flows from the first impurity region 24 to the second impurity region 34, the charge in the charge trapping region X has a great influence on the formation of the channel current. Specifically, at the time of data reading, the first impurity region 24 is grounded (V ₁ = Ground potential), the second impurity region 34 and the gate conductive layer 14 are set to a positive potential (V _GT , V ₂ = Positive potential).
[0070]
(3) Erasure
At the time of data erasing, charges of the conductivity type opposite to the charges in the charge trapping region are injected. When erasing the charge accumulated in the charge trapping region X, the gate conductive layer 14 (V _GT ) Is set to a low level or a negative potential (for example, −3 V), and the second impurity region 34 (V ₂ ) Is applied with a high level voltage (for example, 6 V). Thus, hot holes (P-type hot carriers) are injected into the charge trapping region X.
[0071]
[Characteristic]
(A) Features of memory cell array
First, according to the memory cell array of the present embodiment, the bit conductive layer 80 (bit line BL _{i + 1} ) Is the memory cell T _{i, j + 1} Of the second impurity region 24 and the memory cell T _{i + 1, j + 1} Is electrically connected to the first impurity region 34. As described above, the memory cell T _{i + 1, j + 1} Write to the charge storage region X of the word line WL _{j + 1} To a positive potential and the word line WL _{j + 1} Other word lines are set to the ground potential and the bit lines BL _{i + 1} To a positive potential and the bit line BL _{i + 1} Other bit lines are set to the ground potential. As described above, according to the memory cell 100 of the present embodiment, the bit lines and word lines to which a voltage is applied during writing and erasing are limited. Thus, even if the memory cells 100 adjacent in the column direction share the word line WL and the memory cells 100 adjacent in the row direction share the bit line BL, the selected memory cell 100 (in this case, the memory cell T _{i, j} ) Can be effectively prevented from being erroneously written and erased to cells other than the cells. As described above, a memory cell 100 having excellent reliability can be obtained.
[0072]
In this case, the selected word line and bit line (in this case, word line WL _{j + 1} And bit line BL _{i + 1} ), There is no need to apply voltages to word lines and bit lines. Thus, peripheral circuits for controlling the operation of the memory cell 100 can be simplified. As a result, the area of the peripheral circuit can be reduced, and the operation speed of the memory cell 100 can be improved.
[0073]
(B) Features of memory cells
First, in the memory cell 100 of the present embodiment, since one memory cell has one programming site, it is easier to control the operation of the memory cell. Thereby, a peripheral circuit for controlling the operation of the memory cell can be further simplified. As a result, the area of the peripheral circuit can be reduced, so that the overall size of the semiconductor device can be reduced.
[0074]
Second, the high-concentration impurity region 38 has a higher N-type impurity concentration than the vicinity of the other end of the gate conductive layer 14 in the semiconductor layer 10. According to this configuration, hot carriers can be introduced only in the region near the high-concentration impurity region 38 in the charge trapping layer 22b. That is, the impurity region (the high-concentration impurity region 38) of the semiconductor layer 10 provided in the vicinity of one end of the gate conductive layer 14 can be mainly involved in the writing of the memory cell 100.
[0075]
Specifically, memory cell 100 of the present embodiment includes high-concentration impurity regions 38 and low-concentration impurity regions 28 arranged so as to sandwich gate conductive layer 14, and high-concentration impurity regions 38 The impurity concentration is higher than 28. Thus, the concentration gradient between the high concentration impurity region 38 and the semiconductor layer 10 is larger than the concentration gradient between the low concentration impurity region 28 and the semiconductor layer 10. As a result, even when the same level of bias is applied to the high-concentration impurity region 38 and the low-concentration impurity region 28, generation of hot carriers is suppressed in the low-concentration impurity region 28, so that the high-concentration impurity Only in the region near the impurity region 38 (charge trapping region X), injection of hot carriers is introduced, and cell writing is performed.
[0076]
On the other hand, the low-concentration impurity region 28 is set to have a lower N-type impurity concentration than the high-concentration impurity region 38, so that the generation of hot carriers is suppressed in the low-concentration impurity region 28. That is, even if a bias is applied to the low-concentration impurity region 28, hot carriers are not injected into a region of the charge trapping layer 22b near the low-concentration impurity region 28. Thereby, there is an advantage that disturb hardly occurs and the degree of freedom of the configuration of the memory cell array is increased.
[0077]
Further, generation of hot carriers is suppressed in the low-concentration impurity region 28 of the memory cell 100, so that electric field concentration in the vicinity of the low-concentration impurity region 28 in the gate conductive layer 14 can be reduced. That is, when a high voltage is applied to the low-concentration impurity region 28, occurrence of erroneous writing and change in characteristics can be suppressed, and durability against stress at the time of reading can be increased.
[0078]
In addition, while the charge storage region X is formed near the high concentration impurity region 38 in the charge trapping layer 22b, the vicinity of the low concentration impurity region 28 in the charge trapping layer 22b does not function as a charge storage region. This makes it difficult for the short channel effect to occur, so that the gate length can be further reduced. As a result, the size of the memory cell can be reduced.
[0079]
Thirdly, the third impurity region 32 includes a third impurity region 32 adjacent to the high-concentration impurity region 38 on a side closer to the channel region. Has been introduced. Since the third impurity region 32 is adjacent to the high-concentration impurity region 38 on the side closer to the channel region, the concentration gradient between the high-concentration impurity region 38 and the third impurity region 32 can be further increased. . Thereby, injection of hot carriers into the charge trapping region X can be further promoted.
[0080]
For example, even when the concentration of the P-type impurity in the semiconductor layer 10 is low, since the third impurity region 32 is arranged adjacent to the high-concentration impurity region 38, the high-concentration impurity region 38 and the third impurity region 32 Can be increased, so that the injection of hot carriers into the region of the charge trapping layer 22b near the high concentration impurity region 38 can be further promoted.
[0081]
[Modification]
FIG. 5 shows a modification of the semiconductor device (memory cell array) of the present embodiment. The memory cell array of the present modification also has the same function and effect as the memory cell array of FIG.
[0082]
In the memory cell array shown in FIG. 5, except that the planar shape of the element isolation region 12 is a polygonal line and that the first and second contact portions are arranged in a staggered lattice, the memory cell array shown in FIG. It has the same configuration as the cell array. The cross section taken along the line AA in FIG. 5 has the same configuration as the cross section shown in FIG.
[0083]
The basic configuration and operation of the memory cell of FIG. 5 are the same as those of the memory cell of FIG. Therefore, in the memory cell array shown in FIG. 5, detailed description is omitted for portions having the same configuration as the memory cell array shown in FIG. In FIG. 5, the memory cell T _{i + 1, j + 1} Only the range is indicated by a dotted line.
[0084]
In the memory cell array shown in FIG. 5, the first contact portions and the second contact portions are arranged in a staggered pattern. That is, the plurality of first and second contact portions are respectively arranged in the column direction, and one second contact portion (or first contact portion) is formed from four adjacent first contact portions (or second contact portions). They are located at equal positions.
[0085]
In the memory cell array shown in FIG. 5, the distance between bit conductive layers 80 adjacent in the column direction can be larger than in the memory cell array shown in FIG. Thereby, the margin when forming the bit conductive layer 80 by patterning can be increased.
[0086]
As mentioned above, although one Embodiment of this invention was described, this invention is not limited to this and can take various aspects within the range of the gist of this invention. For example, in the above embodiment, a bulk semiconductor substrate is used as the semiconductor layer 10, but a semiconductor layer of an SOI substrate may be used.
[Brief description of the drawings]
FIG. 1 is a plan view schematically showing a semiconductor device including a nonvolatile memory device according to an embodiment of the present invention.
FIG. 2 is a cross-sectional view schematically showing the nonvolatile memory device shown in FIG.
FIG. 3 is a diagram showing an equivalent circuit of the semiconductor device shown in FIG.
FIG. 4 is a diagram illustrating an operation of the nonvolatile memory device shown in FIG.
FIG. 5 is a plan view schematically showing a modification of the semiconductor device shown in FIG.
[Explanation of symbols]
Reference Signs List 10 semiconductor layer, 12 element isolation region, 14 gate conductive layer, 15 sidewall insulating layer, 22 gate insulating layer, 22a first insulating layer, 22b charge trapping layer, 22c second insulating layer, 24 second impurity region, 26, 36 impurity region, 28 low concentration impurity region, 32 third impurity region, 34 first impurity region, 38 high concentration impurity region, 72 buried insulating layer, 80 wiring layer, 82 conductive layer, 84 opening, 92 silicide layer, 100 memory cells (non-volatile storage device), BD bit line driver, BL _i ~ BL _{i + 4} Bit line, C02, C11-C13, C21-C23, C31-C33 contact, WD word line driver, WL _j ~ WL _{j + 3} Word line

Claims (18)

Including a plurality of nonvolatile storage devices arranged in a row direction and a column direction intersecting the row direction,
The nonvolatile storage device,
A gate insulating layer provided on the channel region of the semiconductor layer, the gate insulating layer including a first insulating layer, a charge trapping layer, and a second insulating layer;
A gate conductive layer provided on the gate insulating layer,
First and second impurity regions of a first conductivity type provided in the semiconductor layer so as to sandwich the gate conductive layer;
The second impurity region of the nonvolatile memory device arranged in the i-th row and [j + 1] column and the first impurity region of the nonvolatile memory device arranged in the [i + 1] -row and [j + 1] column are electrically connected. A bit conductive layer to be connected (i and j are integers of 1 or more);
Including
A semiconductor device having a charge storage region near one end of the gate conductive layer in the charge trapping layer and no charge storage region near the other end. In claim 1,
The first impurity region includes a first conductivity type high-concentration impurity region provided in the semiconductor layer near one end of the gate conductive layer,
The semiconductor device, wherein the high concentration impurity region has a higher concentration of the first conductivity type impurity than near the other end of the gate conductive layer in the semiconductor layer. In claim 2,
The second impurity region includes a first-conductivity-type low-concentration impurity region provided near the other end of the gate conductive layer in the semiconductor layer;
The high-concentration impurity region and the low-concentration impurity region are arranged to sandwich the gate conductive layer,
The semiconductor device, wherein the low-concentration impurity region has a higher first-conductivity-type impurity concentration than the high-concentration impurity region. In claim 2 or 3,
And a third impurity region of a second conductivity type adjacent to the high-concentration impurity region on a side closer to the channel region. In any one of claims 1 to 4,
A semiconductor device, wherein two non-volatile memory devices adjacent in the row direction have a common first impurity region or second impurity region. In claim 5,
A first contact portion provided on the common first impurity region;
A second contact portion provided on the common second impurity region. In claim 6,
The first contact portion is provided on a common first impurity region of the nonvolatile memory device arranged at the i row and the j column and the nonvolatile memory device arranged at the i row and the [j + 1] column.
The second contact portion is a common second impurity region between the nonvolatile memory device arranged in [i + 1] row and [j + 1] column and the nonvolatile memory device arranged in [i + 1] row and [j + 2] column. Provided above,
The semiconductor device, wherein the bit conductive layer electrically connects the common first impurity region and the common second impurity region via the first and second contact portions. In any one of claims 1 to 7,
The semiconductor device, wherein the gate conductive layer extends in a column direction. In any one of claims 1 to 8,
A semiconductor device, wherein two non-volatile memory devices adjacent in the column direction are electrically separated by an element isolation region. In claim 9,
The semiconductor device, wherein the element isolation region has a polygonal line shape. In claim 9 or 10,
Including a plurality of the element isolation regions,
A semiconductor device, wherein the distance between two adjacent element isolation regions is equal. In any one of claims 1 to 11,
The semiconductor device, wherein the bit conductive layer has a portion extending in a direction crossing a row direction and a column direction. In claim 12,
The semiconductor device, wherein the bit conductive layer has a polygonal planar shape. In any one of claims 1 to 13,
Including a plurality of the bit conductive layer,
A semiconductor device, wherein the distance between two adjacent bit conductive layers is equal. In any one of claims 1 to 14,
A buried insulating layer is formed above the nonvolatile memory device,
The semiconductor device, wherein the bit conductive layer is provided above the buried insulating layer. In any one of claims 1 to 15,
The first and second insulating layers are made of silicon oxide,
The semiconductor device, wherein the charge trapping layer is made of silicon nitride. In any one of claims 1 to 16,
Further, a control circuit of the nonvolatile memory device is included,
The control circuit includes:
At the time of writing, a high-level voltage is applied to the gate conductive layer, a low-level voltage is applied to the second impurity region, and a high-level voltage is applied to the first impurity region. Injecting a first conductivity type hot carrier into the charge trapping layer,
A semiconductor device in which, at the time of reading, carriers of the first conductivity type flow in the channel region in a direction opposite to that of writing. In claim 17,
The control circuit applies a voltage to a gate conductive layer and a bit conductive layer electrically connected to the selected nonvolatile memory device during writing, and electrically connects to the non-selected nonvolatile memory device. A voltage is not applied to the gate conductive layer and the bit conductive layer.

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