JP4507023B2 - Semiconductor device including nonvolatile memory device - Google Patents

Description

  The present invention relates to a semiconductor device including a nonvolatile memory device that captures charges (carriers) in a gate insulating layer including an electron trapping layer and stores data.

  As one type of nonvolatile memory device, for example, a gate insulating layer composed of a silicon oxide layer-a silicon nitride layer-a silicon oxide layer is formed between a channel region and a gate conductive layer, and the silicon nitride layer is charged with electric charge. There is a type called MONOS (Metal Oxide Nitride Oxide Semiconductor) type or SONOS (Silicon Oxide Nitride Oxide Silicon) type to be captured (see, for example, Patent Document 1).

  In such a nonvolatile memory device memory cell, when the control of the memory cell becomes complicated, the peripheral circuit for controlling the memory cell becomes complicated. As a result, the area of the peripheral circuit increases, which may hinder downsizing. Further, complication of memory cell control contributes to lowering the operation speed of the memory cell.

JP 2001-118943 A

  An object of the present invention is to provide a semiconductor device including a plurality of nonvolatile memory devices that can achieve improvement in operating speed and reduction in peripheral circuit area.

(1) The semiconductor device of the present invention
A plurality of nonvolatile memory devices arranged in a row direction and a column direction intersecting the row direction;
The nonvolatile memory device is
A gate insulating layer provided on the channel region of the semiconductor layer and including a first insulating layer, a charge trapping layer, and a second insulating layer;
A gate conductive layer provided on the gate insulating layer;
First and second impurity regions of a first conductivity type provided in the semiconductor layer so as to sandwich the gate conductive layer;
A second impurity region of the nonvolatile memory device arranged in i row [j + 1] column and a first impurity region of the nonvolatile memory device arranged in [i + 1] row [j + 1] column are electrically connected Bit conductive layers to be connected (i and j are integers of 1 or more);
Including
The charge trapping layer has a charge accumulation region near one end of the gate conductive layer and does not have a charge accumulation region near the other end.

  According to the semiconductor device, the bit conductive layer includes the second impurity region of the nonvolatile memory device arranged in i row [j + 1] column, and the nonvolatile material arranged in [i + 1] row [j + 1] column. By electrically connecting the first impurity region of the memory device, bit lines and word lines to which a voltage is applied during writing and erasing are limited. Thereby, even if the non-volatile memory devices adjacent in the column direction share a word line and the non-volatile memory devices adjacent in the row direction share a bit line, other than the selected non-volatile memory device It is possible to effectively prevent erroneous writing and erroneous erasing into the cell. As described above, the nonvolatile memory device having excellent reliability can be obtained.

  In addition, the peripheral circuit for controlling the nonvolatile memory device can be further simplified. As a result, the area of the peripheral circuit can be reduced, and the operation speed of the nonvolatile memory device can be improved. Details will be described in the section of this embodiment.

  (2) In the semiconductor device, the first impurity region includes a high-concentration impurity region of a first conductivity type provided in the vicinity of one end of the gate conductive layer in the semiconductor layer, and the high-concentration impurity In the region, the concentration of the first conductivity type impurity can be higher than that in the vicinity of the other end of the gate conductive layer in the semiconductor layer.

  In this case, the second impurity region includes a low-concentration impurity region of a first conductivity type provided in the vicinity of the other end of the gate conductive layer in the semiconductor layer, and the high-concentration impurity region and the low-concentration impurity region The impurity region is disposed so as to sandwich the gate conductive layer, and the concentration of the first conductivity type impurity can be higher in the low concentration impurity region than in the high concentration impurity region.

  Further, in this case, a third impurity region of a second conductivity type adjacent to the high concentration impurity region on a side closer to the channel region can be included.

  (3) In the semiconductor device, the two nonvolatile memory devices adjacent in the row direction may have the common first impurity region or second impurity region.

  In this case, it may further include a first contact portion provided on the common first impurity region and a second contact portion provided on the common second impurity region.

  Further, in this case, the first contact portion is on a common first impurity region between the nonvolatile memory device arranged in i row and j column and the nonvolatile memory device arranged in i row [j + 1] column. And the second contact portion is common to the nonvolatile memory device arranged in the [i + 1] row [j + 1] column and the nonvolatile memory device arranged in the [i + 1] row [j + 2] column. The bit conductive layer is provided on a second impurity region, and the bit conductive layer electrically connects the common first impurity region and the common second impurity region via the first and second contact portions. Can do.

  (4) In the semiconductor device, the gate conductive layer may extend in the column direction.

  (5) In the semiconductor device described above, the two nonvolatile memory devices adjacent in the column direction can be electrically isolated by an element isolation region.

  In this case, the element isolation region may have a polygonal line shape. In this case, a plurality of the element isolation regions can be included, and the distance between two adjacent element isolation regions can be made equal.

  The bit conductive layer has a portion extending in a direction intersecting a row direction and a column direction.

  (6) In the semiconductor device, the bit conductive layer may have a polygonal planar shape.

  (7) In the semiconductor device, a plurality of the bit conductive layers may be included, and the distance between two adjacent bit conductive layers may be equalized.

  (8) In the semiconductor device, a buried insulating layer may be formed above the nonvolatile memory device, and the bit conductive layer may be provided above the buried insulating layer.

  (9) In the semiconductor device, the first and second insulating layers may be made of silicon oxide, and the charge trapping layer may be made of silicon nitride.

(10) The semiconductor device further includes a control circuit for the nonvolatile memory device,
The control circuit includes:
At the time of writing, a high level voltage is applied to the gate conductive layer, a low level voltage is applied to the second impurity region, and a high level voltage is applied to the first impurity region. Injecting hot carriers of the first conductivity type into the charge trapping layer,
At the time of reading, carriers of the first conductivity type can be passed through the channel region in the direction opposite to that at the time of writing.

  In this case, at the time of writing, the control circuit applies a voltage to the gate conductive layer and the bit conductive layer that are electrically connected to the selected nonvolatile memory device, so that the non-selected nonvolatile memory device is electrically connected. No voltage can be applied to the electrically connected gate conductive layer and bit conductive layer.

1 is a plan view schematically showing a semiconductor device including a nonvolatile memory device according to an embodiment of the present invention. It is sectional drawing which shows typically the non-volatile memory device shown in FIG. It is a figure which shows the equivalent circuit of the semiconductor device shown in FIG. It is a figure explaining operation | movement of the non-volatile memory device shown in FIG. FIG. 10 is a plan view schematically showing a modification of the semiconductor device shown in FIG. 1.

  Next, a semiconductor device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a plan view schematically showing a semiconductor device according to an embodiment of the present invention. FIG. 2 is a diagram schematically showing a cross section taken along the line AA of FIG.

  As shown in FIG. 1, the semiconductor device of the present embodiment includes a memory cell array including a plurality of nonvolatile memory devices (memory cells) 100. FIG. 2 shows a cross section of the memory cell 100 shown in FIG.

[Plane structure]
First, the planar structure of the semiconductor device of this embodiment will be described mainly with reference to FIGS.

FIG. 3 is a schematic circuit diagram of the semiconductor device shown in FIG. As shown in FIG. 3, a plurality of word lines WL (WL _j , WL _{j + 1} , WL _{j + 2} , WL _{j + 3} ...) And a plurality of bit lines BL (BL _i , BL _{i + 1} , BL _{i + 2} , BL _{i + 3} , BL _{i + 4} ...) Are arranged above the semiconductor layer 10 so as to cross each other. 1 corresponds to the bit conductive layer 80, and the word line WL is connected to the word conductive layer 14 shown in FIG.

  These bit lines BL are connected to a bit line driver BD and selectively receive a driving voltage. These word lines WL are connected to a word line driver WD and selectively receive a scanning voltage. Control circuits of the memory cell 100 such as the bit line driver BD and the word line driver WD can be formed in the same semiconductor layer 10 as the memory cell array shown in FIG.

As shown in FIG. 1, each word line WL extends in the column direction. In addition, the first impurity regions 34 and the second impurity regions 24 are alternately arranged between two adjacent word lines WL. For example, a second impurity region 24 is disposed between WL _j and WL _{j + 1} , a first impurity region 34 is disposed between WL _{j + 1} and WL _{j + 2,} and between WL _{j + 2} and WL _{j + 3.} A second impurity region 24 is disposed.

  As shown in FIG. 3, a memory cell 100 is connected to each intersection of the word line WL and the bit line BL. In the memory cell array shown in FIG. 1, a plurality of memory cells 100 are arranged in a row direction and a column direction intersecting the row direction. In this embodiment, the case where the row direction and the column direction are orthogonal to each other is shown.

1 and 3, the memory cell 100 arranged in i row and j column is denoted as “T _ij ” (i and j are integers of 1 or more). Here, the “memory cell (T _ij ) arranged in i row and j column” is connected between the i th bit line BL _i and the [i + 1] th bit line BL _{i + 1,} and its gate conductive layer Is a memory cell connected to the j-th word line WL _j (see FIG. 3).

As shown in FIG. 1, two memory cells 100 adjacent in the row direction have a common first impurity region 34 or a common second impurity region 24. Specifically, for example, as shown in FIG. 1, memory cells T _{i + 1, j + 1} and T _{i + 1, j + 2} adjacent in the row direction have a common first impurity region 34. The memory cells T _{i, j} and T _{i, j + 1} adjacent in the row direction have a common second impurity region 24.

  Further, as shown in FIG. 1, the first and second impurity regions 34 and 24 are arranged in the column direction, respectively. The common first and second impurity regions 34 and 24 adjacent in the column direction are electrically isolated by the element isolation region 12. The element isolation region 12 is made of, for example, STI shallow trench isolation. On the other hand, the first and second impurity regions 34 and 24 adjacent in the row direction are arranged so as to sandwich the word line WL (gate conductive layer 14) (see FIG. 3).

  That is, as shown in FIG. 1, the memory cells 100 adjacent in the column direction are electrically isolated by the element isolation region 12. FIG. 1 shows a case where a plurality of element isolation regions 12 extend linearly in the row direction. Further, the distance between two adjacent element isolation regions 12 is formed to be approximately equal.

  In addition, on the common second impurity region 24, first contact portions C11, C21, C31, C13, C23, and C33 are provided. On the common first impurity region 34, second contact portions C02, C12, and C22 are provided.

Next, the connection structure of the bit line BL (bit conductive layer 80) will be described with reference to FIG. 1, taking memory cells T _{i, j + 1} and T _{i + 1, j + 1} adjacent in the column direction as an example.

Bit line _{BL i + 1} (bit conductive layer _{80), T i, j +} 1 and the second impurity region 24 (i row [j + 1] memory cells 100 arranged in _{columns), T i + 1, j} + 1 ([i + 1] row [j + 1 The first impurity regions 34 of the memory cells 100) arranged in the column are electrically connected.

Specifically, memory cell _{T i,} a second impurity region 24 of the _{j + 1,} the memory cell _{T i + 1,} the first impurity region 34 of the _{j + 1,} through the first contact portion C11 and the second contact portion C12, the bit They are electrically connected by a line BL _{i + 1} (bit conductive layer 80).

The first contact portion C11, the memory cell _{T i,} provided on the common second impurity region 24 of the _{j + 1} and the memory cell _{T i + 1, j + 1,} the second contact portion C12, the memory cell _{T i + 1, j + 1} and memory cell The first impurity region 34 is provided in common with T _{i + 1 and j + 2} . Therefore, the bit line BL _{i + 1} (bit conductive layer 80) electrically connects the common second impurity region 24 and the common first impurity region 34 via the first contact portion C11 and the second contact portion C12. is doing.

Further, the bit line BL _{i + 1} (bit conductive layer 80) electrically connects the common first impurity region 34 and the common second impurity region 24 via the second contact portion C12 and the first contact portion C13. is doing. The first contact portion C13 is provided on the first impurity region 24 common to the memory cell T _{i, j + 2} and the memory cell T _{i, j + 3} .

  Therefore, the bit line BL (bit conductive layer 80) electrically connects the common first impurity region 34 and the common second impurity region 24 alternately via the first contact portion and the second contact portion. ing.

For example, the bit line BL _{i + 1} (bit conductive layer 80) includes the second impurity region 24 of the memory cell 100 arranged in the i row and the first impurity region 34 of the memory cell 100 arranged in the [i + 1] row. , Alternately connected electrically. Specifically, the bit line BL _{i + 1} is connected to the second impurity region 24 common to the memory cells T _{i, j} and T _{i, j + 1} via the first contact portion 11 and the memory cell via the second contact portion 12. A first impurity region 34 common to T _{i + 1, j + 1} and T _{i + 1, j + 2,} a second impurity region 24 common to the memory cells T _{i, j + 2} and T _{i, j + 3} via the first contact portion 13 _,. Electrically connected.

  In the memory cell array shown in FIG. 1, specifically, bit conductive layer 80 (bit line BL) has a portion extending in the direction intersecting the row direction and the column direction. Specifically, the bit conductive layer 80 has a polygonal plane shape. Also, as shown in FIG. 1, the distance between two adjacent bit conductive layers 80 is formed to be approximately equal.

[Cross-section structure]
Next, a cross-sectional structure of the memory cell 100 shown in FIG. 1 will be described with reference mainly to FIG.

As shown in FIG. 2, the memory cell 100 includes one gate conductive layer 14 (word line WL _{j + 1} ), a gate insulating layer 22, and first and second impurity regions 34 and 24. The gate conductive layer 14 is formed on the semiconductor layer 10 via the gate insulating layer 22. The gate conductive layer 14 is made of, for example, doped polysilicon. In addition, sidewall insulating layers 15 can be provided on both side walls of the gate conductive layer 14 (see FIG. 2). The sidewall insulating layer 15 is made of, for example, silicon oxide or silicon nitride.

  The gate insulating layer 22 is formed by sequentially depositing a first insulating layer 22a, a charge trapping layer 22b, and a second insulating layer 22c. The first insulating layer 22a forms a potential barrier between the channel region and the charge storage region. The charge trapping layer 22b includes a charge storage region that traps carriers (for example, electrons). The second insulating layer 22c forms a potential barrier between the gate conductive layer 14 and the charge storage region.

  In memory cell 100 of the present embodiment, 1 bit is stored per cell. Specifically, as shown in FIGS. 1 and 2, the charge trapping layer 22b has a charge accumulation region X. The charge storage region X is formed in the vicinity of one end of the gate conductive layer 14 in the charge trapping layer 22b. On the other hand, no charge storage region is formed in the vicinity of the other end of the gate conductive layer 14 in the charge trapping layer 22b (the low concentration impurity region 28 in the charge trapping layer 22b).

  The charge trapping layer 22b can be made of, for example, a layer in which a metal such as tungsten is dispersed in an insulating layer such as silicon nitride, silicon oxide, or silicon nitride, or a silicon oxide layer in which polysilicon islands are embedded.

  The gate insulating layer 22 can be made of, for example, an ONO (Oxide-Nitride-Oxide) film. That is, the first and second insulating layers 22a and 22c are made of silicon oxide, and the charge trapping layer 22b is made of silicon nitride.

  As shown in FIG. 2, the first and second impurity regions 34 and 24 are disposed so as to sandwich the gate conductive layer 14 in the semiconductor layer 10. A channel region is formed in the semiconductor layer 10 between the first and second impurity regions 34 and 24 and under the gate conductive layer 14.

  Impurities of the same conductivity type (first conductivity type) are introduced into the first and second impurity regions 34 and 24. In the present embodiment, the case where the first conductivity type is N-type and the second conductivity type is P-type is described, but these conductivity types can be reversed.

  The first impurity region 34 has a high concentration impurity region 38 and an impurity region 36. The impurity region 36 is adjacent to the high concentration impurity region 38. The impurity region 36 is provided at a position farther from the gate conductive layer 14 than the high-concentration impurity region 38 in one memory cell 100.

  The second impurity region 24 has a low concentration impurity region 28 and an impurity region 26. The impurity region 26 is adjacent to the low concentration impurity region 28. The impurity region 26 is provided at a position farther from the gate conductive layer 14 than the low-concentration impurity region 28 in one memory cell 100. The second impurity region 24 has an LDD Lightly doped drain structure. Specifically, the low-concentration impurity region 28 has an N-type impurity concentration lower than that of the impurity region 26.

  As shown in FIG. 1, the high concentration impurity region 38 is provided in the vicinity of one end portion of the gate conductive layer 14 in the semiconductor layer 10. The low concentration impurity region 28 is provided in the vicinity of the other end of the gate conductive layer 14 in the semiconductor layer 10. The high-concentration impurity region 38 and the low-concentration impurity region 28 are disposed so as to sandwich the gate conductive layer 14 as shown in FIG.

  In both the high-concentration impurity region 38 and the low-concentration impurity region 28, impurities of the same conductivity type (first conductivity type) are introduced. In the present embodiment, the case where the first conductivity type is N-type and the second conductivity type is P-type is described, but these conductivity types can be reversed.

  The N-type impurity concentration in the high-concentration impurity region 38 is higher than the N-type impurity concentration in the low-concentration impurity region 28. That is, the low-concentration impurity region 28 whose N-type impurity concentration is lower than that of the high-concentration impurity region 38 is provided in the vicinity of the other end of the gate conductive layer 14 in the semiconductor layer 10. The concentration of the N-type impurity is higher than that of the semiconductor layer 10 near the other end of the gate conductive layer 14.

  Specifically, the high-concentration impurity region 38 preferably has an N-type impurity concentration that is at least several times (eg, 3 to 4 times) or more that of the low-concentration impurity region 28, and is preferably 10 times or more. It is more desirable to have

  As shown in FIG. 2, in the semiconductor layer 10 made of a P-type semiconductor substrate, a third impurity region 32 is formed in a region adjacent to the high concentration impurity region 38 on the side closer to the channel region. The third impurity region 32 is doped with an impurity of a conductivity type (second conductivity type; P type) different from that of the high concentration impurity region 38. Here, as shown in FIG. 2, it is desirable that the third impurity region 32 is disposed up to a position closer to the central portion of the channel region than to the high concentration impurity region 38. Even if the third impurity region 32 is not provided, if the N-type impurity concentration of the high-concentration impurity region 38 is sufficiently high and the concentration gradient between the high-concentration impurity region 38 and the channel region is sufficiently large, the memory cell 100 can be obtained. During the writing, hot carriers can be injected into the charge storage region X.

  Furthermore, as shown in FIG. 2, a silicide layer 92 containing a metal such as titanium or cobalt can be formed on the first and second impurity regions 34 and 24 and the gate conductive layer 14. By forming these silicide layers 92, the access speed of the memory cell 100 can be improved.

A buried insulating layer 72 is formed on the memory cell 100. Further, a bit conductive layer 80 (bit lines BL _{i + 1} and BL _{i + 2 in} FIG. ₂ ) is provided on the buried insulating layer 72. In the cross section shown in FIG. 2, the first contact portion C21 provided on the second impurity region 24, the bit conductive layer 80 (bit line BL _{i + 2} ) provided on the first contact portion C21, and the first impurity region A second contact portion C12 provided on the bit line 34 and a bit conductive layer 80 (bit line BL _{i + 1} ) provided on the second contact portion C12 are shown. The first and second contact portions include an opening 84 provided in the buried insulating layer 72 and a conductive layer 82 buried in the opening 84.

[Operation]
As described above, the memory cell 100 stores 1 bit per cell. Specifically, charges are accumulated in the charge trapping region X in the charge accumulation layer 22b.

  As described above, in the memory cell 100 of the present embodiment, the high concentration impurity region 38 in the first impurity region 34 has a higher concentration of N-type impurities than the low concentration impurity region 28 in the second impurity region 24. The high concentration impurity region 38 is formed in the vicinity of one end of the gate conductive layer 14a, and the low concentration impurity region 28 is formed in the vicinity of the other end. For this reason, when charge is introduced into the charge trapping layer 22b, the charge is trapped in the charge trapping region X near the end closer to the high concentration impurity region 38 in the charge trapping layer 22b. On the other hand, in the vicinity of the end portion closer to the low concentration impurity region 28 in the charge trapping layer 22b, the charge is not trapped.

Hereinafter, an example of the operation of the memory cell 100 will be described with reference to FIG. Here, a case will be described in which the memory cell T _{i + 1, j + 1} shown in FIG. 1 is selected for writing.

(1) Write At the time of data write, the second impurity region 34 is grounded (V ₂ = ground potential), and the first impurity region 24 and the gate conductive layer 14 are set to a positive potential (V _GT , V ₁ = positive). Potential), hot electrons (N-type hot carriers) are accumulated in the charge trapping region X in the charge trapping layer 22b in the vicinity of the high concentration impurity region.

When writing to the charge storage region X of the memory cells T _{i + 1, j + 1} in FIG. 1, the word line WL _{j + 1 is set} to a positive potential (for example, 7 V), and the word lines other than the word line WL _{j + 1} are set to the ground potential. In FIG. 1, the bit line BL _{i + 1 is set} to a positive potential (for example, 5 V), and the bit lines other than the bit line BL _{i + 1} are set to the ground potential. As a result, hot electrons are injected into the charge storage region X.

In this case, in the memory cell T _{i, j + 1} adjacent to the memory cell T _{i + 1, j + 1} selected for writing in the column direction, similarly to the memory cell T _{i + 1, j + 1} selected for writing, The two impurity regions 24 have a positive potential, and the first impurity region 34 has a ground potential.

However, in the memory cell 100, the low concentration impurity region 28 of the second impurity region 24 is set to have a much lower N-type impurity concentration than the high concentration impurity region 38 of the first impurity region 34. No charge is injected into the layer 22b in the vicinity of the low-concentration impurity region 28 (region Y in FIG. 1). Therefore, no writing is performed on the memory cell T _{i, j + 1} .

(2) Reading At the time of data reading, N-type carriers are passed through the channel region in the direction opposite to that at the time of writing. When a current is passed from the first impurity region 24 to the second impurity region 34, the charge in the charge trapping region X has a great influence on the formation of the channel current. Specifically, at the time of data reading, the first impurity region 24 is grounded (V ₁ = ground potential), and the second impurity region 34 and the gate conductive layer 14 are set to a positive potential (V _GT , V ₂ = positive potential). .

(3) Erase At the time of data erasure, a charge having a conductivity type opposite to that in the charge trapping region is injected. When erasing the charge accumulated in the charge trapping region X, the gate conductive layer 14 (V _GT ) is set to a low level or a negative potential (for example, −3 V), and a high level voltage is applied to the second impurity region 34 (V ₂ ). For example, 6V) is applied. Thereby, hot holes (P-type hot carriers) are injected into the charge trapping region X.

[Characteristic]
(A) Features of Memory Cell Array First, according to the memory cell array of the present embodiment, the bit conductive layer 80 (bit line BL _{i + 1} ) includes the second impurity region 24 of the memory cell T _{i, j + 1} and the memory cell. The first impurity region 34 of T _{i + 1, j + 1} is electrically connected. As described above, when writing to the charge storage region X of the memory cell T _{i + 1, j + 1} , the word line WL _{j + 1 is set} to the positive potential, the word lines other than the word line WL _{j + 1} are set to the ground potential, and the bit line BL _{i + 1 is set.} Is set to a positive potential, and bit lines other than the bit line BL _{i + 1} are set to the ground potential. Thus, according to the memory cell 100 of the present embodiment, the bit line and the word line to which a voltage is applied during writing and erasing are limited. Thus, even if the memory cells 100 adjacent in the column direction share the word line WL and the memory cells 100 adjacent in the row direction share the bit line BL, the selected memory cell 100 (in this case, the memory cell T It is possible to effectively prevent erroneous writing and erroneous erasing to cells other than _{i, j} ). As described above, the memory cell 100 having excellent reliability can be obtained.

In this case, it is not necessary to apply a voltage to word lines and bit lines other than the selected word line and bit line (in this case, word line WL _{j + 1} and bit line BL _{i + 1} ). Thereby, the peripheral circuit for controlling the operation of the memory cell 100 can be simplified. As a result, the peripheral circuit area can be reduced, and the operation speed of the memory cell 100 can be improved.

(B) Characteristics of Memory Cell First, the memory cell 100 of the present embodiment has one programming site in one memory cell, so that it is easier to control the operation of the memory cell. Thereby, the peripheral circuit for controlling the operation of the memory cell can be further simplified. As a result, the area of the peripheral circuit can be reduced, so that the size of the entire semiconductor device can be reduced.

  Second, the high-concentration impurity region 38 has a higher concentration of N-type impurities than the vicinity of the other end portion of the gate conductive layer 14 in the semiconductor layer 10. According to this configuration, hot carriers can be introduced only in the region near the high concentration impurity region 38 in the charge trapping layer 22b. That is, the impurity region (high-concentration impurity region 38) provided in the vicinity of one end of the gate conductive layer 14 in the semiconductor layer 10 can be mainly involved in the writing of the memory cell 100.

  Specifically, the memory cell 100 of the present embodiment includes a high concentration impurity region 38 and a low concentration impurity region 28 arranged so as to sandwich the gate conductive layer 14, and the high concentration impurity region 38 is a low concentration impurity region. Impurity concentration is higher than 28. As a result, the concentration gradient between the high concentration impurity region 38 and the semiconductor layer 10 is larger than the concentration gradient between the low concentration impurity region 28 and the semiconductor layer 10. As a result, even when the high-concentration impurity region 38 and the low-concentration impurity region 28 are biased to the same extent, the generation of hot carriers is suppressed in the low-concentration impurity region 28, so that the high concentration of the charge trapping layer 22 b Only in the region (charge trapping region X) in the vicinity of the impurity region 38, hot carrier injection is introduced and the cell is written.

  On the other hand, since the N-type impurity concentration of the low concentration impurity region 28 is set lower than that of the high concentration impurity region 38, the generation of hot carriers is suppressed in the low concentration impurity region 28. That is, even if the low concentration impurity region 28 is biased, hot carriers are not injected into the region near the low concentration impurity region 28 in the charge trapping layer 22b. As a result, disturbance is less likely to occur, and there is an advantage that the degree of freedom in the configuration of the memory cell array is increased.

  Further, by suppressing the generation of hot carriers in the low concentration impurity region 28 of the memory cell 100, electric field concentration in the vicinity of the low concentration impurity region 28 in the gate conductive layer 14 can be reduced. That is, when a high voltage is applied to the low-concentration impurity region 28, it is possible to suppress the occurrence of erroneous writing and change in characteristics, and to improve the durability against stress during reading.

  In addition, the charge storage region X is formed in the charge trapping layer 22b in the vicinity of the high concentration impurity region 38, whereas the charge trapping layer 22b in the vicinity of the low concentration impurity region 28 does not function as a charge storage region. Thereby, since the short channel effect hardly occurs, the gate length can be further reduced. As a result, the memory cell can be reduced in size.

  Third, it includes a third impurity region 32 that is adjacent to the high concentration impurity region 38 on the side closer to the channel region, and this third impurity region 32 has impurities of a conductivity type (P type) different from that of the high concentration impurity region 38. Has been introduced. Since the third impurity region 32 is adjacent to the high concentration impurity region 38 on the side closer to the channel region, the concentration gradient between the high concentration impurity region 38 and the third impurity region 32 can be further increased. . Thereby, injection of hot carriers into the charge trapping region X can be further promoted.

  For example, even when the concentration of the P-type impurity in the semiconductor layer 10 is low, the third impurity region 32 is disposed adjacent to the high concentration impurity region 38, so that the high concentration impurity region 38 and the third impurity region 32 are arranged. Therefore, the hot carrier injection into the region near the high concentration impurity region 38 in the charge trapping layer 22b can be further promoted.

[Modification]
FIG. 5 shows a modification of the semiconductor device (memory cell array) of this embodiment. The memory cell array of this modification also has the same operation and effect as the memory cell array of FIG.

  In the memory cell array shown in FIG. 5, the memory shown in FIG. 1 except that the planar shape of the element isolation region 12 is a polygonal line and that the first and second contact portions are arranged in a staggered pattern. It has the same configuration as the cell array. 5 has the same configuration as the cross section shown in FIG.

The basic configuration and operation of the memory cell of FIG. 5 are the same as those of the memory cell of FIG. Therefore, in the memory cell array shown in FIG. 5, detailed description of portions having the same configuration as that of the memory cell array shown in FIG. 1 is omitted. In FIG. 5, only the memory cell T _{i + 1, j + 1} has a range indicated by a dotted line.

  In the memory cell array shown in FIG. 5, the first contact portions and the second contact portions are arranged in a staggered pattern. That is, a plurality of first and second contact portions are arranged in the column direction, and one second contact portion (or first contact portion) is formed from four adjacent first contact portions (or second contact portions). It is placed at the same position.

  In the memory cell array shown in FIG. 5, the distance between the bit conductive layers 80 adjacent in the column direction can be made larger than in the memory cell array shown in FIG. Thereby, a margin when forming the bit conductive layer 80 by patterning can be increased.

  As mentioned above, although one embodiment of the present invention was described, the present invention is not limited to this, and can take various forms within the scope of the gist of the present invention. For example, in the above embodiment, a bulk semiconductor substrate is used as the semiconductor layer 10, but a semiconductor layer of an SOI substrate may be used.

10 semiconductor layer, 12 element isolation region, 14 gate conductive layer, 15 sidewall insulating layer, 22 gate insulating layer, 22a first insulating layer, 22b charge trapping layer, 22c second insulating layer, 24 second impurity region, 26, 36 impurity regions, 28 low-concentration impurity regions, 32 third impurity regions, 34 first impurity regions, 38 high-concentration impurity regions, 72 buried insulating layers, 80 wiring layers, 82 conductive layers, 84 openings, 92 silicide layers, 100 memory cells (nonvolatile memory device), BD bit line driver, BL _{i to} BL _{i + 4} bit line, C02, C11 to C13, C21 to C23, C31 to C33 contact, WD word line driver, WL _{j to} WL _{j + 3} word line

Claims (6)

A plurality of nonvolatile memory devices arranged in a row direction and a column direction intersecting the row direction;
Each of the plurality of nonvolatile storage devices includes:
A gate insulating layer provided on the channel region of the second conductivity type of the semiconductor layer and comprising a first insulating layer, a charge trapping layer, and a second insulating layer;
A gate conductive layer provided on the gate insulating layer;
A first impurity region and a second impurity region of a first conductivity type provided in the semiconductor layer so as to sandwich the gate conductive layer;
A second impurity region of the nonvolatile memory device arranged in i row [j + 1] column and a first impurity region of the nonvolatile memory device arranged in [i + 1] row [j + 1] column are electrically connected Bit conductive layers to be connected (i and j are integers of 1 or more);
Including
The first impurity region includes a high-concentration impurity region of a first conductivity type provided in the vicinity of one end of the gate conductive layer in the semiconductor layer,
The second impurity region is adjacent to the low-concentration impurity region of the first conductivity type provided near the other end of the gate conductive layer in the semiconductor layer, and the low-concentration impurity. An impurity region provided at a position farther from the gate conductive layer than the region,
The high concentration impurity region and the low concentration impurity region are disposed so as to sandwich the gate conductive layer,
The high concentration impurity region is provided under one end of the gate conductive layer and has an impurity concentration higher than that of the impurity region,
The low concentration impurity region is provided below the other end portion of the gate conductive layer, and to have a lower impurity concentration than the impurity regions, the semiconductor device. In claim 1,
Furthermore, the have if adjacent to the high impurity concentration region in the near side by a channel region, a third impurity region, the second conductivity type high concentration than said channel region, the semiconductor device. In claim 2,
  The concentration gradient between the high concentration impurity region and the channel region is larger than the concentration gradient between the low concentration impurity region and the channel region,
  A semiconductor device, wherein a concentration gradient between the high concentration impurity region and the third impurity region is larger than a concentration gradient between the high concentration impurity region and the channel region. In any of claims 1 to 3 ,
Two of the non-volatile memory device adjacent in the row direction, have a common said first impurity region or the second impurity region,
A first contact portion provided on the common first impurity region;
A second contact portion provided on said common second impurity regions on, only including,
The first contact portion is provided on a first impurity region common to the nonvolatile memory device arranged in i rows and j columns and the nonvolatile memory device arranged in i rows [j + 1] columns,
The second contact portion is a second impurity region common to the nonvolatile memory device arranged in the [i + 1] row and [j + 1] column and the nonvolatile memory device arranged in the [i + 1] row and [j + 2] column Provided on the
The bit conductive layer electrically connects the common first impurity region and the common second impurity region via the first and second contact portions. A plurality of nonvolatile storage devices arranged in a row direction and a column direction intersecting the row direction;
  Each of the plurality of nonvolatile storage devices includes:
  A gate insulating layer provided on the channel region of the second conductivity type of the semiconductor layer and comprising a first silicon oxide layer, a silicon nitride layer, and a second silicon oxide layer;
  A gate conductive layer provided on the gate insulating layer;
  A first impurity region and a second impurity region of a first conductivity type provided in the semiconductor layer so as to sandwich the gate conductive layer;
  A second impurity region of the nonvolatile memory device arranged in i row [j + 1] column and a first impurity region of the nonvolatile memory device arranged in [i + 1] row [j + 1] column are electrically connected Bit conductive layers to be connected (i and j are integers of 1 or more);
  Including
  The first impurity region includes a high-concentration impurity region of a first conductivity type provided in the vicinity of one end of the gate conductive layer in the semiconductor layer,
  The second impurity region is adjacent to the low-concentration impurity region of the first conductivity type provided near the other end of the gate conductive layer in the semiconductor layer, and the low-concentration impurity. An impurity region provided at a position farther from the gate conductive layer than the region,
  The high concentration impurity region and the low concentration impurity region are disposed so as to sandwich the gate conductive layer,
  The high concentration impurity region is provided under one end of the gate conductive layer and has an impurity concentration higher than that of the impurity region,
  The low-concentration impurity region is provided under the other end of the gate conductive layer, and has a lower impurity concentration than the impurity region. In any of claims 1 to 5 ,
And a control circuit for the nonvolatile memory device,
The control circuit includes:
At the time of writing, a high level voltage is applied to the gate conductive layer, a low level voltage is applied to the second impurity region, and a high level voltage is applied to the first impurity region. Injecting hot carriers of the first conductivity type into the charge trapping layer,
At the time of reading, the time of writing in the reverse direction, and the flow of the first conductivity type carriers in the channel region,
At the time of writing, a voltage is applied to the gate conductive layer and the bit conductive layer electrically connected to the selected nonvolatile memory device, and the gate conductive layer electrically connected to the non-selected nonvolatile memory device And a semiconductor device in which no voltage is applied to the bit conductive layer.

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