JP2009141134A - Semiconductor memory device and manufacturing method thereof, and operating method of semiconductor memory device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor memory device capable of compatibly improving a write speed and suppressing readout disturbance. <P>SOLUTION: A charge accumulation film and a gate electrode 105 are formed on a semiconductor layer, and two first conductivity diffusion regions A and B are formed in semiconductor layers on both sides of a channel region formed below the gate electrode 105. The channel region is so formed that the channel width Wb on the side where the diffusion region B comes into contact with the channel region is not larger than the channel width Wa on the side where the diffusion region A comes into contact with the channel region. Upon storing operation, a higher voltage is applied to the diffusion region A than to the diffusion region B, and upon readout operation, a higher voltage is applied to the diffusion region B than to the diffusion region A. <P>COPYRIGHT: (C)2009,JPO&INPIT

Description

  The present invention relates to a semiconductor memory device, and more particularly to a nonvolatile semiconductor memory device that performs writing using hot carriers, a method for manufacturing the same, and a method for operating the semiconductor memory device.

  A conventional nonvolatile memory device using a floating gate has, for example, the configuration shown in FIG. The semiconductor memory device shown in FIG. 16 shows a case where the semiconductor memory device is manufactured by the same method as that for manufacturing the NMOSFET. This nonvolatile memory device includes a first insulating film 902, a floating gate 903 made of a conductor, a second insulating film 904, a gate electrode on a p-type semiconductor substrate 901 provided with an element isolation region 900 made of an insulating film. 905. Generally, the semiconductor substrate 901 is a silicon substrate, the first insulating film 902 is a silicon oxide film, the second insulating film 904 is a silicon oxide film, or silicon oxide film / silicon nitride film / silicon oxide film 3. A layer structure is often used. A polysilicon film is often used as the floating gate 903 and the gate electrode 905.

  These are known methods, that is, the first insulating film 902 is thermally oxidized on the surface of the semiconductor substrate 901, and the floating gate 903, the second insulating film 904, and the gate electrode 905 are formed by chemical vapor deposition (CVD). Is formed into a predetermined shape, and further processed into a predetermined shape by lithography and dry etching. On both sides of the gate electrode, a source 906 and a drain 907, which are n-type diffusion regions formed by ion implantation and activation annealing, are partially overlapped with the gate electrode. Note that contact plugs, metal wirings, etc. are not shown.

  When writing to this memory device, as shown in FIG. 17, a ground potential is applied to the source 906, a positive write voltage is applied to the drain 907, and a positive write voltage is applied to the gate electrode 905. At this time, an electron flow 909 flows from the source 906 to the drain 907 in the channel 908 under the gate electrode. This electron flow 909 is accelerated by a high electric field by the drain 907 in the vicinity of the end of the drain 907 and hot holes due to impact ionization.・ Generate hot electron pairs. Among these, a part of hot electrons is attracted to the positive bias of the gate electrode 905 and jumps to the floating gate 903 beyond the potential energy of the first insulating film 902 to become the accumulated charge 910. A state where the accumulated charge 910 exists is a write state.

  When reading data from the memory device, a ground potential is applied to the source 906, a positive read voltage lower than the write voltage is applied to the drain 907, and a positive read voltage lower than the write voltage is applied to the gate electrode 905. At this time, since an electron flow flows from the source 906 to the drain 907 via the channel 908 under the gate electrode, the amount of the electron flow is monitored as a read current. That is, in the writing state in which the accumulated charge 910 exists, the threshold voltage rises because the electric field exerted on the channel 908 by the gate electrode 905 is shielded by the accumulated charge 910, compared to the case where the accumulated charge 910 does not exist. The read current is lowered. Therefore, the amount of read current reflects the presence or absence of accumulated charge 910, so that the information written in this storage device can be read.

Here, for example, Patent Literature 1 proposes a method for improving the write characteristics of the nonvolatile memory device. This semiconductor memory device has a cross-sectional structure conforming to the above technique, but has a planar structure, which is shown in FIG. FIG. 18 is a plan view of the source 906, the drain 907, and the channel region 908. This semiconductor memory device is characterized in that the channel width 912 near the drain 907 is narrower than the channel width 911 near the source 906.
With this structure, it is possible to improve the writing speed while reducing the decrease in the on-current as compared with the case where the channel width is simply reduced over the entire channel region.
JP 63-37669 A

Improving the write efficiency not only has the advantage that high-speed writing can be performed, but also writing occurs at a lower voltage. In the technique of Patent Document 1, a semiconductor memory device is built in a fixed structure that narrows the channel width on the drain side, thereby relatively increasing the channel resistance in the vicinity of the drain, and The horizontal electric field is more effectively concentrated near the drain to increase the writing efficiency.
However, this also increases the electric field concentration in the vicinity of the drain during the read operation, and has the side effect of increasing read disturb (erroneous write). Read disturb is a phenomenon in which the threshold value gradually rises even to cells that are not originally written by repeated reading. Read disturb operates at a voltage lower than that at the time of writing at the time of reading.However, since electrons flow from the source to the drain also at the time of reading, hot carriers are generated in the vicinity of the drain. By accumulating.

In the technique of Patent Document 1, a structure for increasing the electric field in the vicinity of the drain is adopted in order to improve the writing efficiency. However, as a side effect, hot carrier generation is promoted even during reading, and reading disturb is likely to occur. There is.
The present invention solves the above-described problems, and provides a semiconductor memory device capable of achieving both improvement in write speed and suppression of read disturb. The present invention also provides a method for manufacturing the semiconductor memory device. Furthermore, the present invention provides a method for operating this semiconductor memory device.

  In order to solve the above problems, a semiconductor memory device according to a first aspect of the present invention includes a semiconductor layer, a charge storage film having a charge storage function formed on the semiconductor layer, and a gate formed on the charge storage film. An electrode, a channel region formed in the semiconductor layer below the gate electrode, and two first conductivity type diffusion regions (A) and (B) formed in the semiconductor layer on both sides of the channel region; A control circuit for applying a predetermined voltage to each of the gate electrode and the two diffusion regions (A) and (B), and the channel region has a channel width on the side where the one diffusion region (A) is in contact The channel width Wb on the side where the other diffusion region (B) contacts is larger than Wa, and the control circuit transfers the other diffusion region (B) to the one diffusion region (A) during the storage operation. Higher voltage Applied to, at the time of reading is to apply a voltage higher than the one of the diffusion regions to the other diffusion region (B) (A).

According to the above-described invention, since the write voltage is applied with the diffusion region (A) having a narrow channel width and high channel resistance as the drain region during writing, the lateral electric field at the drain region end can be effectively increased. As a result, the writing efficiency can be improved, so that the writing speed can be increased or the writing voltage can be lowered.
On the other hand, at the time of reading, since the reading voltage is applied using the diffusion region (B) side having a wide channel width and low channel resistance as the drain region, the lateral electric field at the end of the drain region is alleviated. (Incorrect writing) is less likely to occur. That is, a high performance and high reliability semiconductor memory device having both high write efficiency and high read disturb tolerance can be obtained.

In the semiconductor memory device of one embodiment of the present invention, the charge storage film has at least a part of the first insulating film, a conductor film made of the same material as the gate electrode, and a first electrode in order from the semiconductor layer side. 2 insulating films.
This configuration has an advantage that a memory cell having a floating gate type structure and a normal transistor for a circuit can be easily formed at the same time.

The semiconductor memory device according to one embodiment of the present invention is characterized in that the charge storage film is an insulating film.
As a result, the accumulated charge is localized in the charge accumulation film near one diffusion region (A) having a narrow channel width, and the channel width is wide on the other diffusion region (B) side that becomes the drain region at the time of reading. Because of its low resistance, the effect of accumulated charge is sensitively reflected in the amount of read current, and a highly reliable semiconductor memory device with a large read current difference (window) between the write state and erase state can be obtained. It is done.
In addition, it is possible to effectively localize the position where charge is injected at the time of writing, and to match the position of charge injection at the time of writing and erasing, so that the charge remains without being neutralized at the time of rewriting. As much as possible, it is possible to prevent rewriting deterioration caused by the remaining charge.

In the semiconductor memory device according to an embodiment of the present invention, the charge storage film includes at least a part of the first insulating film, an insulator having a charge storage function, and a second insulation in order from the semiconductor layer side. It has the structure which consists of a film | membrane.
With this structure, the accumulated charge is prevented from flowing out to the outside by the first insulating film and the second insulating film, which is suitable for long-term holding. In addition, since charges are held in the insulator, even if a part of the first insulating film or the second insulating film is damaged, the accumulated charge does not flow out from the damaged portion at once. High reliability.

The semiconductor memory device according to an embodiment of the present invention is characterized in that the semiconductor layer includes a well region of a second conductivity type different from the diffusion region. Thereby, by providing the well region, the resistance of the semiconductor layer is lowered, and the potential controllability of the semiconductor layer is increased, so that variation between devices is suppressed.
The semiconductor memory device of one embodiment of the present invention is characterized in that a ratio of the channel width Wa to the channel width Wb is 20% to 80%. With this ratio, a read-on current that does not impair the reliability of the memory device can be obtained while obtaining the above-described effect, and the advantages of the present invention can be exhibited most effectively. When the ratio of the channel width Wa to the channel width Wb is 40% to 70%, the above effect can be obtained more remarkably.

In the semiconductor memory device according to an embodiment of the present invention, the first diffusion region having a lower impurity concentration than the other diffusion region (B) is formed in the semiconductor layer below the gate electrode at the end of the other diffusion region (B). A conductive type region is provided.
As a result, a highly reliable semiconductor memory device can be obtained in which the lateral electric field at the end of the other diffusion region (B), which becomes the drain region at the time of reading, is further relaxed and the read disturb resistance is high.

In one embodiment of the present invention, in the semiconductor memory device, the channel region extends from the other diffusion region (B) toward the one diffusion region (A), (1) a region having the channel width Wb, (2 And (3) a region that decreases from the channel width Wb to the channel width Wa, and (3) a region that has the channel width Wa.
Accordingly, the channel shape is prevented from becoming an acute angle or a right angle, and the gate electric field is concentrated on the corner portion to prevent the insulating film from being broken, so that a highly reliable memory device can be obtained.

The semiconductor memory device according to one embodiment of the present invention is characterized in that an intrinsic semiconductor region or a second conductivity type semiconductor region is provided in at least a portion of the one diffusion region (A) adjacent to the gate electrode direction.
That is, the channel width Wa on the side of at least one diffusion region (A) is not defined by element isolation, but is defined by the width of the region where the first conductivity type impurity is implanted. It is not defined by element isolation or the like, but is automatically defined by the channel widths Wb and Wa in the vicinity of the other diffusion region (B) and one diffusion region (A) and the electric field during operation. Therefore, the structure is not easily affected by a photoalignment deviation or the like at the time of element formation, and the element characteristic variation is effectively prevented.

A semiconductor memory device according to an embodiment of the present invention has a plurality of memory cells at least in the word line direction, and adjacent memory cells, the one diffusion region (A) and the other diffusion region (B) are staggered. It is arranged so that In particular, when a plurality of memory cells are two-dimensionally arranged, the bit lines are zigzag-shaped so as to connect the one diffusion region (A) and the other diffusion region (B). It is provided.
By adopting such a structure, a dense arrangement is possible while ensuring the element isolation width and the bit line interval, and the chip area can be reduced.

A semiconductor memory device according to an embodiment of the present invention has a plurality of memory cells at least in the word line direction, and the other diffusion region (B) is shared by adjacent memory cells.
In this configuration, it is not necessary to separate the other diffusion region (B) adjacent in the word line direction, so that the chip area can be reduced. In addition, since the number of bit lines can be reduced because the bit line connected to the other diffusion region (B) can be shared, the circuit can be simplified and the chip area can be reduced.

The semiconductor memory device according to one embodiment of the present invention is characterized in that the semiconductor layer is formed on an insulating substrate.
As described above, according to the present invention, forming on an inexpensive glass substrate or the like without using an expensive semiconductor substrate can suppress the manufacturing cost and has an important industrial significance. In addition, this embodiment has the following effects. In general, when forming a memory on an insulating substrate, the crystallinity of the semiconductor layer and the interface state between the semiconductor layer and the insulating film are not as good as when using a semiconductor substrate. Due to the influence of carrier scattering and the like, the range in which charges are injected into the charge holding film tends to be wide. This can cause rewrite degradation due to charge neutralization failure during rewrite. In this embodiment, the charge injection position can be effectively localized, and the charge injection position at the time of writing and at the time of erasing can be matched, so that rewriting deterioration can be prevented. This realizes an inexpensive and rewritable memory.

The semiconductor memory device of one embodiment of the present invention includes a body contact region having a second conductivity type impurity concentration higher than the well concentration on the same side as the one diffusion region (A) with respect to the gate electrode. It is characterized by having.
As described above, when the semiconductor memory device is provided over the insulating substrate, the body contact is provided and the potential of the semiconductor layer is controlled, so that variation between elements can be suppressed and stable writing operation can be performed. In particular, in this configuration, by providing the body contact on the side of one diffusion region (A) that functions as a drain region at the time of writing, the position where the carrier is generated at the time of writing is close to the body contact, and the carrier can be efficiently discharged. . For this reason, it is highly effective to perform stable writing by suppressing fluctuations in body potential and preventing abnormal operations such as a decrease in writing speed. At the same time, when the body contact is provided, it is mounted using the extra space next to one diffusion region (A) with a narrow channel width, so the high density that efficiently utilizes the space on the chip A simple layout.

A semiconductor memory device according to an embodiment of the present invention is characterized in that a region having a low impurity concentration is provided between a body contact region and the one diffusion region (A).
Thereby, the reverse breakdown voltage between one diffusion region (A) and the body contact region is increased, and the leakage current between them is suppressed, so that a semiconductor memory device with low power consumption is provided.
The semiconductor memory device according to an embodiment of the present invention is characterized in that a part of the body contact region is close to or overlaps with the semiconductor layer region immediately below the gate electrode. As a result, when performing an erase operation, carriers flow from the body contact region to the semiconductor layer under the gate electrode to form a storage layer, and a low-resistance current from the position where carriers are generated during erase to the body contact region Since a route is formed, stable and high-speed erasure is possible.

  The semiconductor memory device of the second invention is a semiconductor layer, two diffusion regions (A) and (B) of the first conductivity type formed in the semiconductor layer, and the two diffusion regions (A) and (B ) Between the channel region formed in the semiconductor layer, a gate electrode formed on the channel region so as to be offset with respect to at least one diffusion region (A) via a gate insulating film, and the gate electrode A memory cell comprising: a gate sidewall insulating film formed on at least one of the sidewalls on the diffusion region (A) side; an insulator having a charge trap level disposed in the gate sidewall insulating film; and the semiconductor A control circuit that applies a predetermined voltage to each of the layer, the gate electrode, and the two diffusion regions (A) and (B), and the channel region has a channel width on the side where the one diffusion region (A) contacts The channel width Wb on the side where the other diffusion region (B) contacts is larger than a, and the control circuit transfers the other diffusion region (B) to the one diffusion region (A) during the memory operation. A voltage higher than that of the one diffusion region (A) is applied to the other diffusion region (B) at the time of reading.

According to the above invention, since the memory portion is provided not in the gate electrode but in the side wall shape, the distance between the gate electrode and the channel is short, and at least one diffusion region (A) and the gate electrode are offset. . Therefore, there is a strong merit for the short channel effect. In addition to this, there are advantages similar to those of the first invention. That is, at the time of writing, a writing voltage is applied using one diffusion region (A) having a narrow channel width and high channel resistance as a drain region, so that the lateral electric field at the end of the drain region can be effectively increased. For this reason, since the writing efficiency can be improved, the writing speed can be increased or the writing voltage can be lowered. On the other hand, since a read voltage is applied with the other diffusion region (B) having a wide channel width and low channel resistance as a drain region at the time of reading, the lateral electric field at the end of the drain region is alleviated, and reading is performed even when repeated reading is performed. It has the merit that disturb (erroneous writing) hardly occurs.
That is, a high performance and high reliability semiconductor memory device having both high write efficiency and high read disturb tolerance can be obtained. In particular, as described above, when one diffusion region (A) side (drain region side) on which writing is performed has an offset structure, electric field concentration is unlikely to occur at the drain region end during writing, and writing efficiency tends to be low. is there. Also from this point, the second invention has an important effect of realizing high write efficiency while having the sidewall-shaped storage section. Further, since the other diffusion region (B) side, which becomes the drain region at the time of reading, has a wide channel width and low resistance, the influence of the accumulated charge is sensitively reflected on the amount of reading current. Therefore, there is a merit that the read current difference (window) between the write state and the erase state is large and the reliability is high.

The semiconductor memory device according to an embodiment of the present invention is characterized in that the semiconductor layer includes a well region of a second conductivity type different from the diffusion region. Thereby, by providing the well region, the resistance of the semiconductor layer is lowered, and the potential controllability of the semiconductor layer is increased, so that variation between devices is suppressed.
The semiconductor memory device of one embodiment of the present invention is characterized in that a ratio of the channel width Wa to the channel width Wb is 20% to 80%.
With this ratio, a read-on current that does not impair the reliability of the memory device can be obtained while obtaining the above-described effect, and the advantages of the present invention can be exhibited most effectively. When the ratio of the channel width Wa to the channel width Wb is 40% to 70%, the above effect can be obtained more remarkably.

In the semiconductor memory device according to an embodiment of the present invention, the first diffusion layer having a lower impurity concentration than the other diffusion region (B) is formed in the semiconductor layer below the gate electrode at the end of the other diffusion region (B). A conductive type region is provided.
As a result, a highly reliable semiconductor memory device can be obtained in which the lateral electric field at the end of the other diffusion region (B), which becomes the drain region at the time of reading, is further relaxed and the read disturb resistance is high.
In one embodiment of the present invention, in the semiconductor memory device, the channel region extends from the other diffusion region (B) toward the one diffusion region (A), (1) a region having the channel width Wb, (2 And (3) a region that decreases from the channel width Wb to the channel width Wa, and (3) a region that has the channel width Wa.
Accordingly, the channel shape is prevented from becoming an acute angle or a right angle, and the gate electric field is concentrated on the corner portion to prevent the insulating film from being broken, so that a highly reliable memory device can be obtained.

The semiconductor memory device according to one embodiment of the present invention is characterized in that an intrinsic semiconductor region or a second conductivity type semiconductor region is provided in at least a portion of the one diffusion region (A) adjacent to the gate electrode direction.
That is, the channel width Wa on the side of at least one diffusion region (A) is not defined by element isolation, but is defined by the width of the region where the first conductivity type impurity is implanted. Therefore, the current path during operation is not defined by element isolation or the like, and is automatically determined by the channel widths Wb and Wa near the other diffusion region (B) and one diffusion region (A) and the electric field during operation. Stipulated in That is, it is a structure that is not easily affected by a photoalignment shift or the like during element formation, and effectively prevents element characteristic variations.

A semiconductor memory device according to an embodiment of the present invention has a plurality of memory cells at least in the word line direction, and adjacent memory cells, the one diffusion region (A) and the other diffusion region (B) are staggered. It is arranged so that In particular, when a plurality of memory cells are two-dimensionally arranged, the bit lines are zigzag-shaped so as to connect the one diffusion region (A) and the other diffusion region (B). It is provided.
By adopting such a structure, a dense arrangement is possible while ensuring the element isolation width and the bit line interval, and the chip area can be reduced.

A semiconductor memory device according to an embodiment of the present invention has a plurality of memory cells at least in the word line direction, and the other diffusion region (B) is shared by adjacent memory cells.
In this configuration, it is not necessary to separate the other diffusion region (B) adjacent in the word line direction, so that the chip area can be reduced. In addition, since the number of bit lines can be reduced because the bit line connected to the other diffusion region (B) can be shared, the circuit can be simplified and the chip area can be reduced.
The semiconductor memory device according to one embodiment of the present invention is characterized in that the semiconductor layer is formed on an insulating substrate.
As a result, the manufacturing cost can be reduced by forming on an inexpensive glass substrate or the like without using an expensive semiconductor substrate.
As described above, according to the present invention, forming on an inexpensive glass substrate or the like without using an expensive semiconductor substrate can suppress the manufacturing cost and has an important industrial significance. In addition, this embodiment has the following effects. In general, when forming a memory on an insulating substrate, the crystallinity of the semiconductor layer and the interface state between the semiconductor layer and the insulating film are not as good as when using a semiconductor substrate. Due to the influence of carrier scattering and the like, the range in which charges are injected into the charge holding film tends to be wide. This can cause rewrite degradation due to charge neutralization failure during rewrite. In this embodiment, the charge injection position can be effectively localized, and the charge injection position at the time of writing and at the time of erasing can be matched, so that rewriting deterioration can be prevented. This realizes an inexpensive and rewritable memory.

The semiconductor memory device of one embodiment of the present invention includes a body contact region having a second conductivity type impurity concentration higher than the well concentration on the same side as the one diffusion region (A) with respect to the gate electrode. It is characterized by having.
According to the present invention, when a semiconductor memory device is provided on an insulating substrate, a body contact is provided and the potential of the semiconductor layer is controlled, so that variation between elements can be suppressed and stable writing operation can be performed. And by providing the body contact on the side of one diffusion region (A) that functions as a drain region particularly at the time of writing, the position where the carrier is generated at the time of writing is close to the body contact, so that carriers can be efficiently discharged. The effect of stable writing is suppressed by suppressing fluctuations in body potential and preventing abnormal operations such as a decrease in writing speed. At the same time, when the body contact is provided, it is mounted using the extra space next to one diffusion region (A) with a narrow channel width, so the high density that efficiently utilizes the space on the chip A simple layout.

A semiconductor memory device according to an embodiment of the present invention is characterized in that a region having a low impurity concentration is provided between a body contact region and the diffusion region (A).
Thereby, the reverse breakdown voltage between one diffusion region (A) and the body contact region is increased, and the leakage current between them is suppressed, so that a semiconductor memory device with low power consumption is provided.

The semiconductor memory device according to an embodiment of the present invention is characterized in that a part of the body contact region is close to or overlaps with the semiconductor layer region immediately below the gate electrode.
As a result, when performing an erase operation, carriers flow from the body contact region to the semiconductor layer under the gate electrode to form a storage layer, and a low-resistance current from the position where carriers are generated during erase to the body contact region Since a route is formed, stable and high-speed erasure is possible.

In one embodiment of the method for manufacturing a semiconductor memory device of the present invention, the impurity concentration of the semiconductor layer under the gate electrode is higher than that of the other diffusion region (B) at the end of the other diffusion region (B). A method of manufacturing a semiconductor memory device comprising a thin first conductivity type region, wherein the introduction of impurities in the first conductivity type region having a low impurity concentration is performed after the gate electrode forming step. The first conductivity type impurity implantation is performed at an angle of 15 ° or more with respect to the vertical.
By this method, the first conductivity type region having a low impurity concentration can be easily introduced without using a special process or manufacturing apparatus.

In one embodiment of the method for manufacturing a semiconductor memory device of the present invention, an intrinsic semiconductor region or a second conductivity type semiconductor region is provided at least in a portion adjacent to the diffusion region (A) in the gate electrode direction. A method of manufacturing a semiconductor memory device, the step of forming a gate electrode, the step of providing an implantation mask, and the first conductivity of the one diffusion region (A) and the other diffusion region (B) by ion implantation. A step of implanting a type impurity, and the opening width in the gate electrode direction of the implantation mask is narrower in the one diffusion region (A) portion than in the other diffusion region (B) portion. To do.
With this method, the semiconductor memory device can be easily manufactured without using a special process or manufacturing apparatus, and the effect of misalignment during photo on the device characteristics of the memory cell is small. Semiconductor memory devices with small variations are manufactured.

The operating method of the semiconductor memory device according to the present invention is the operating method of the semiconductor memory device according to any one of the first to second inventions, wherein the other diffusion region (A) is transferred to the one diffusion region (A) during the storage operation. A voltage higher than that of B) is applied, and a voltage higher than that of the one diffusion region (A) is applied to the other diffusion region (B) at the time of reading.
As a result, high writing efficiency is exhibited during writing, so that high-speed writing or low-voltage writing is possible, and erroneous writing due to read disturb can be prevented during reading.

The operation method of the semiconductor memory device according to one embodiment is characterized in that biases opposite to each other are applied to the one diffusion region (A) and the gate electrode with reference to the potential of the semiconductor layer during the memory operation.
With this operation method, for example, by performing an erasing operation which is one of the storage operations, a current caused by a band-to-band tunnel flows between one diffusion region (A) and the semiconductor layer, and hot carriers are secondarily generated. Since the generated charges are erased by the generated hot carriers, the erase can be performed at a high speed with a relatively low voltage. In particular, in erasing a semiconductor memory device including an insulating film having a charge storage function, charge exchange can be performed only in the vicinity of one diffusion region (A) during writing and erasing. Match the parts to be written and erased, effectively neutralize the accumulated charge by writing, and suppress the injection of extra carriers to other parts as much as possible, so even if you repeatedly write and erase, High holding ability can be realized.

  As described above in detail, according to the present invention, there is provided a semiconductor memory device that has high write efficiency and is less susceptible to read disturb than a conventional semiconductor memory device. In particular, when an insulating film having a charge storage function is provided and information is stored by storing charges in the insulating film, the structure is sensitive to charges and has the effect of widening the window. And a highly reliable semiconductor memory device suitable for the above can be obtained. The semiconductor memory device of the present invention can be manufactured at low cost by being formed over an insulator substrate. Further, by adopting the above-described embodiment, memory cells can be efficiently arranged with high density, and an increase in chip area can be suppressed.

  Hereinafter, the present invention will be described in detail with reference to the drawings. Hereinafter, in the first to seventh embodiments, an n-type device will be mainly described. However, it may be implemented as a p-type device. In that case, in the following description, the conductivity type of the impurity is set to the reverse conductivity type. The applied voltage may be a reverse bias. In the case of an n-type device, a state in which electrons are accumulated in the charge storage film, and in a p-type device, a state in which holes are accumulated is defined as a write state. The erased state refers to a state in which almost no electrons or holes are accumulated, or a state in which electrons and holes are accumulated to the same extent and charges are neutralized. Since the eighth embodiment using an insulating substrate such as a glass substrate is particularly preferably formed as a p-type device, the p-type device is described.

(First embodiment)
The configuration of the semiconductor memory device according to the first embodiment will be described with reference to FIGS. FIG. 1 is a schematic cross-sectional view of a memory cell portion in this embodiment, and FIG. 2 is a schematic plan view thereof.
As shown in the cross-sectional view of FIG. 1, on a p-type semiconductor substrate 101 provided with an element isolation region 100 made of an insulating film such as a silicon oxide film, a first insulating film 102, a floating gate 103 made of a conductor, A second insulating film 104 and a gate electrode 105 are formed.
In general, the semiconductor substrate 101 is a silicon substrate, the first insulating film 102 is a silicon oxide film, the second insulating film 104 is a silicon oxide film, or silicon oxide film / silicon nitride film / silicon oxide film 3. A layer structure can be used. For example, a polysilicon film is used as the floating gate 103 and the gate electrode 105, but a metal such as tungsten may be used.

These are known methods, that is, the first insulating film 102 is formed by thermal oxidation of the surface of the semiconductor substrate 101. The floating gate 103, the second insulating film 104, and the gate electrode 105 are formed by chemical vapor deposition (CVD), and further processed by lithography and dry etching. The floating gate 103 and the gate electrode 105 may be formed of the same material or different conductors.
In particular, if the same material is used for the floating gate 103 and the gate electrode 105, there is an advantage that it is easy to mix with the non-memory element for a circuit. That is, after the second insulating film 104 is deposited, the memory element forming portion is covered with a photoresist or the like, the second insulating film 104 in the circuit forming portion is removed by etching, the photoresist is removed, and the gate electrode 105 and the subsequent layers are deposited. When the process is performed, the memory cell portion has a floating gate type structure, and at the same time, the circuit formation portion has a normal transistor structure having no floating gate (the floating gate 103 and the gate electrode 105 are integrated in direct contact). Thereby, a memory element and a non-memory element can be formed simultaneously without going through a complicated process.

Here, the film thicknesses of the first insulating film 102 and the second insulating film 104 may be appropriately determined according to the use and specification of the semiconductor memory device. In general, as these films are thinner, the short channel effect is suppressed and suitable for miniaturization. However, if the film is too thin, there is a possibility that the charge holding ability may be lowered. In addition, since hot carriers are injected into the floating gate 103 through the first insulating film 102 at the time of writing, the writing efficiency is improved when the first insulating film 102 is thinner.
In view of the above points and the miniaturization level, voltage specification, write speed specification, retention specification, etc. of the semiconductor device to be manufactured, an engineer may select an appropriate film thickness of these films. In general, the thickness of the first insulating film 102 is preferably about 3 nm to 20 nm, and the thickness of the second insulating film 104 is preferably set to be thicker than the first insulating film in the range of about 5 nm to 50 nm. . In this embodiment, the first insulating film thickness is 6 nm and the second insulating film thickness is 15 nm.

On the semiconductor substrate on both sides of the gate electrode, a diffusion region (B) 106, which is an n-type diffusion region formed by ion implantation and activation annealing, and a diffusion region ( A) 107 is included. Note that contact plugs, metal wirings, etc. are not shown. Further, an insulating film side wall may be formed on the side wall of the gate electrode 105 as necessary. Also, if necessary, a low resistance film such as a metal silicide film may be formed on the surface of the diffusion regions 106 and 107 and the gate electrode 105 in order to reduce the sheet resistance. By forming it, a simple silicide film can be formed by the salicide technique.
In particular, when the semiconductor memory device is arranged in a cell array, and when the gate electrode 105 is used as a word line across a plurality of cells as it is, the floating gate 103 is formed before the deposition of the gate electrode 105 material. It is preferable to divide each element in the direction perpendicular to the paper surface.

  Next, as shown in the plan view of FIG. 2, the diffusion region (A) 107 on the right side of the drawing sheet has a channel width Wb (111 in the drawing) where the diffusion region (B) 106 on the left side of the drawing sheet faces the gate electrode 105. The channel width Wa (112 in the figure) of the portion facing the gate electrode 105 is formed to be small. At the same time, an electron flow is made to flow from the diffusion region (B) 106 to the diffusion region (A) 107 (arrow 113 in the figure) during the write operation to the memory cell, and conversely during the read operation to the memory cell, the electron flow It is characterized by flowing a flow from the diffusion region (A) 107 to the diffusion region (B) 106 (indicated by an arrow 114 in the figure).

Specifically, the shape of the diffusion region (B) 106 on the left side of the drawing is set so as to have the channel width Wb (111 in the figure) by the element isolation region 100, and the channel width Wa (112 in the figure) is set. The shape of the diffusion region (A) 107 on the right side of the page is set. Similarly, the shape of the channel 108 is set by the element isolation region 100.
At the time of writing in this semiconductor memory device, the semiconductor substrate 101 and the diffusion region (B) 106 are grounded, the gate electrode 105 has a write gate voltage (for example, a voltage of about 5 V), and the diffusion region (A) has a write drain voltage (for example, about 5 V). Voltage). That is, the diffusion region (B) is operated as a source region and the diffusion region (A) is operated as a drain region.
At this time, the electron flow 113 flows from the left to the right in the drawing on the channel 108, but the channel width Wa (112) on the diffusion region (A) 107 side is narrower than the channel width Wb (111). The channel resistance in the vicinity is high, and a lateral electric field from the diffusion region (B) 106 to the diffusion region (A) 107 is effectively applied to this vicinity. Therefore, the hot carrier generation efficiency is increased, and high-speed writing is possible. Therefore, there is an advantage that a high-performance semiconductor memory device can be provided. In addition, the fact that the carrier generation efficiency can be increased means that the write voltage can be lowered while maintaining the write speed, so that advantages such as simplification of the peripheral circuit and longer life can be obtained. Is possible.

Next, at the time of reading, in this case, for example, this time, the semiconductor substrate 101 and the diffusion region (A) 107 are grounded, and the gate electrode 105 has a read gate voltage lower than the write gate voltage (for example, a voltage of about 3 V). Then, a read drain voltage (for example, a voltage of about 1.5 V) lower than the write drain voltage and lower than the read gate voltage is applied to the diffusion region (B). That is, this time, the diffusion region (A) on the side having the narrow channel width Wa (112) is the source region, and the diffusion region (B) on the side having the wide channel width Wb (111) is the drain region. It is operating as.
At this time, an electron flow 114 flows from the right to the left in the drawing on the channel 108. In general, the channel width Wb (111) is the channel width Wa at the drain region end (diffusion region (B) end) where a drain electric field is likely to be applied. Since it is wider than (112), the resistance is low, and the lateral electric field at this portion is relaxed. Therefore, the hot carrier generation at the end of the drain region is weakened at the time of the read operation, and the read disturb is less likely to occur. Therefore, a highly reliable semiconductor memory device that is less likely to malfunction even during repeated reading. Is provided.

As for the ratio of the channel width Wa (112) to the channel width Wb (111), the smaller the channel width Wa (112), the easier the above effect is obtained. In general, the Wa / Wb ratio is preferably set to about 20% to 80%. Furthermore, if it is made 40% to 70%, the above effect can be obtained more remarkably. In this example, the ratio was 50%.
The present invention applies a voltage higher than that of the diffusion region (B) to the diffusion region (A) during a write operation and a circuit for performing the above operation in addition to the memory cell having the above-described configuration. B) includes a series of circuits having a function of applying a voltage higher than that of the diffusion region (A). As an example of the circuit configuration, a schematic diagram of the main part of the semiconductor memory device of this embodiment is shown in FIG.

  In general, a semiconductor memory device often has a cell array configuration in which a plurality of memory cells are two-dimensionally arranged, but only one memory cell is displayed here for easy understanding. Bit lines 116 and 117 are connected to the diffusion region (B) 106 on the side having a wide channel width Wb and the diffusion region (A) 107 on the side having a narrow channel width with respect to the memory cell 115, respectively. Further, it is connected to a read drain voltage control circuit 1001 and a write drain voltage control circuit 1002 via selection transistors 118 and 119, respectively. The bit lines 116 and 117 are also connected to a ground power supply via selection transistors 120 and 121, respectively. The gate electrode of the memory cell 115 is connected to the word line control circuit 1003 through the word line 122. In addition to these configurations, a read circuit such as a sense amplifier is appropriately installed (for example, connected between the read drain voltage control circuit 1001 and the select transistor 118 via a cut transistor). Was omitted.

  The operations of the selection transistors 118, 119, 120, and 121 are controlled by the selection circuit 1004. In this embodiment, the simplest configuration is illustrated in which these are controlled by two control lines. In other words, the selection transistor 119 that connects the diffusion region (A) 107 and the write drain voltage control circuit 1002 and the selection transistor 120 that connects the diffusion region (B) 106 and the GND power supply both through the selection transistor control line 123. Controlled by. On the other hand, the selection transistor 118 that connects the diffusion region (B) 106 and the read drain voltage control circuit 1001 and the selection transistor 121 that connects the diffusion region (A) 107 and the GND power supply both through the selection transistor control line 124. Controlled.

At the time of writing, a writing drain voltage is supplied from the writing drain voltage control circuit 1002, a writing gate voltage is applied from the word line control circuit 1003, an ON signal is input to the control line 123 by the selection circuit 1004, and an OFF signal is input to the control line 124. , The selection transistors 119 and 120 are turned on, the selection transistors 118 and 121 are turned off, the diffusion region (B) 106 becomes the source region, and the diffusion region (A) 107 becomes the drain region. Is done.
At the time of reading, a read drain voltage is supplied from the read drain voltage control circuit 1001, a read gate voltage is applied from the word line control circuit 1003, an off signal is input to the control line 123 by the selection circuit 1004, and an on signal is supplied to the control line 124. , The selection transistors 118 and 121 are turned on, the selection transistors 119 and 120 are turned off, the diffusion region (A) 107 becomes the source region, and the diffusion region (B) 106 becomes the drain region. Is done.
With the above configuration, a semiconductor memory device having high write efficiency and high read disturb tolerance can be obtained.

FIG. 3 is merely an example, and it is not always necessary to follow the circuit configuration as shown in FIG. 3 in applying the present invention. In short, the memory cells have different channel widths at the ends of the diffusion regions on both sides of the gate, and the diffusion region with the narrower channel width is used as the drain region during writing, and the diffusion region with the wider channel width is used as the drain during reading. Setting the area is an important point of the present invention, and it is sufficient if the structure satisfies this.
For example, the selection transistors 118, 121, 119, and 120 need not be controlled by the same control line, and different control lines may be provided. Further, as described above, FIG. 3 shows a circuit configuration for a single memory cell. However, in order to realize a semiconductor memory device for storing a plurality of bits, two word lines, two bit lines, or both directions can be realized. A memory cell array can be configured by dimensionally arranging a plurality of memory cells and arranging a plurality of word lines / bit lines accordingly.
When multiple cells are arranged in the direction along the word line, that is, in the horizontal direction of the paper, the bit line can be shared by installing the adjacent cells in the left-right direction. Since the area can be reduced, the manufacturing cost can be reduced. The design of the selection transistor and the control line for controlling the selection transistor may be appropriately performed according to the cell array configuration.

Moreover, the arrangement of such a configuration can be freely designed by appropriately applying a technique used for a conventional nonvolatile semiconductor memory device, selecting an appropriate circuit configuration.
Finally, regarding the erasing operation of the semiconductor device, it may be performed by extracting stored electrons by FN tunneling, or by hot carrier generation by band-to-band tunneling. In the case of performing FN tunneling, for example, the diffusion region and the substrate are set to the ground potential, and a high negative voltage (for example, about −15 V) is applied to the gate electrode, whereby the stored electrons are tunneled from the floating gate to the substrate and erased.
3, the voltage output from the read drain voltage control circuit 1001 and the write drain voltage control circuit 1002 is stopped, and an ON signal is input to the control lines 123 and 124 by the selection circuit 1004. Erasing is performed by setting the diffusion regions 106 and 107 to the ground potential through 121 and applying a negative erasing voltage from the word line control circuit 1003 to the gate electrode.

On the other hand, when erasing is performed by hot carrier generation by band-to-band tunneling, the substrate is grounded, a positive erasing voltage (for example, 5V) is applied to one or both of the diffusion regions, and a negative erasing voltage (for example, -8V is applied to the gate electrode). ) Is applied. At this time, a steep junction is formed between the storage layer generated under the gate electrode and the diffusion region, and an electron flow from the diffusion region to the storage layer, a so-called interband tunneling phenomenon occurs. The tunnel electrons are accelerated by the electric field to generate hot carriers. Among the hot carriers, holes are attracted by the gate electric field and jump into the floating gate, so that the accumulated charges are erased.
In the case of the configuration of FIG. 3, for example, the read drain voltage control circuit 1001 is provided with an erasing voltage generation function, and the selection circuit 1004 inputs an off signal to the control line 123 and an on signal to the control line 124. An erase voltage is applied to the region (B) 106. At the same time, an erase operation is performed by applying a negative erase gate voltage from the word line control circuit 1003 to the gate electrode.
Here, erasing is possible even if the erasing voltage is applied to the diffusion region (A) side at the time of erasing, but it is better to generate an interband tunnel on the diffusion region (B) 106 side. More efficient erasure is possible. If an erasing voltage is applied to both diffusion regions 106 and 107, more efficient erasing is possible, but this method can also be realized by a simple circuit change.

  The semiconductor memory device described above can be manufactured using a conventional manufacturing method without requiring a special manufacturing apparatus or the like. In addition, various application developments are possible by making full use of conventional circuit technology within a range not impairing the basic technical idea of the present invention. In the above embodiment, the source potential and the drain potential at the time of reading are controlled and the reading current flowing between them is monitored, but other than this method, for example, the source region side is put in a floating state and reading is performed. It is also possible to take a method of monitoring the potential increase on the source region side.

(Second Embodiment)
FIG. 4 is a schematic cross-sectional view of a memory cell portion in the semiconductor memory device of the second embodiment. Although the configuration is almost similar to that of the first embodiment described above, the difference from the first embodiment is that the stored charge is stored in the charge storage insulating film 225 instead of the floating gate. As the material, any insulating film having a charge storage function may be used, and silicon nitride films, various high dielectric material films such as aluminum oxide and hafnium oxide, or laminated films thereof can be used. It is also possible to use an insulating film (such as a silicon oxide film) that contains dots capable of accumulating charges. In particular, the use of a silicon nitride film has the merit that it can be most easily handled in a general production line and can be manufactured at low cost.

  That is, in the semiconductor memory device of the second embodiment, the first insulating film 102, the charge storage insulating film 225, the p-type semiconductor substrate 101 provided with the element isolation region 100 made of an insulating film such as a silicon oxide film, A second insulating film 104 and a gate electrode 105 are provided. In general, a silicon substrate can be used as the semiconductor substrate 101, and a silicon oxide film can be used as the first insulating film 102 and the second insulating film 104. For example, a polysilicon film is used as the gate electrode 105, but a metal such as tungsten may be used.

  The first insulating film 102 may be obtained by oxidizing the surface of the semiconductor substrate 101, or a silicon oxide film or the like may be deposited by a technique such as CVD. As the second insulating film 104, a silicon oxide film by CVD or the like can be used. Similarly to the first embodiment, the film thickness may be determined appropriately according to the specifications of the semiconductor memory device. Generally speaking, the film thickness of the first insulating film 102 is about 3 nm to 20 nm, and the charge storage film insulating film 225 is. The film thickness of 5 nm to 50 nm, the film thickness of the second insulating film 104 is set in the range of about 5 nm to 50 nm, and the second insulating film is set to be thicker than the first insulating film. It is preferable from the aspect of efficiency. In this embodiment, the first insulating film thickness is 5 nm, the second insulating film thickness is 10 nm, a silicon nitride film is used as the charge storage insulating film 225, and the film thickness is 10 nm. With this stacked structure, the charge accumulated in the charge storage insulating film 225 is prevented from leaking to the outside as much as possible, and can be held for a long time.

  On the semiconductor substrate on both sides of the gate electrode, a diffusion region (B) 106, which is an n-type diffusion region formed by ion implantation and activation annealing, and a diffusion region ( A) 107 is included. Note that contact plugs, metal wirings, etc. are not shown. Further, an insulating film side wall may be formed on the side wall of the gate electrode 105 as necessary. Also, if necessary, a low resistance film such as a metal silicide film may be formed on the surface of the diffusion regions 106 and 107 and the gate electrode 105 in order to reduce the sheet resistance. By forming it, a simple silicide film can be formed by the salicide technique.

  In order to form the memory cell of the second embodiment, even when a plurality of memory cells are arranged in the direction perpendicular to the paper surface, it is not necessary to divide the charge storage film 225 for each cell for the reason described later. Therefore, after the first insulating film 102, the charge storage film 225, the second insulating film 104, and the gate electrode 105 material film are all deposited, they are easily processed by lithography and etching techniques.

  Also in the second embodiment, as shown in FIG. 2, the channel width Wb (111) at the end of one diffusion region (B) 106 is changed to the channel width Wa (112) at the end of the other diffusion region (A) 107. The diffusion region (A) is operated as a drain region during writing, and the diffusion region (B) is operated as a drain region during reading. As a result, as in the first embodiment, there is an advantage that the writing efficiency is high and read disturb hardly occurs. In addition, there are the following advantages.

In the second embodiment, since charge accumulation is performed by an insulating film, the accumulated charge hardly moves in the film after writing, and the accumulated charge 226 is a drain region at the time of writing as shown in FIG. Localized in the charge storage film 225 in the vicinity of the diffusion region (B) 107. Therefore, in the semiconductor memory device of the second embodiment, electrons injected from the vicinity of the step between the channel width Wb (111) and the channel width Wa (112) are accumulated in the charge storage film 225 on the drain side.
Here, for convenience, the channel region 108 is roughly divided into a region 227 in which charges are stored in the upper charge storage film 225 and a region 228 in which charges are not stored in the upper charge storage film 225.
These regions 227 and 228 function as resistances at the time of reading, but the channel resistance mainly changes depending on the presence or absence of the accumulated charge 226 in the region 227 where charges are accumulated. Therefore, if the resistance of the region 228 where charge is not accumulated is originally higher than the region 227 where charge is accumulated, the influence of the presence or absence of the accumulated charge 226 on the amount of read current is relatively small. Conversely, if the resistance of the region 228 where charge is not accumulated is small, the proportion of the resistance of the region 227 where charge is accumulated out of the total channel resistance. That is, when the resistance of the region 227 in which charges are accumulated changes depending on the presence / absence of the accumulated charge 226, the total channel resistance also changes accordingly. Therefore, the presence / absence of the accumulated charge 226 ultimately determines the amount of read current. The impact on the is relatively large. Here, in this embodiment, since the channel width on the diffusion region (B) 106 side is large, the resistance of the region 228 in which charge is not accumulated is kept low. For this reason, the influence of the stored charge 226 on the amount of read current can be increased, and the current difference (window) between the written state and the erased state can be increased. There is an advantage that a semiconductor memory device can be obtained.

In addition, when a conductive floating gate is used, if the first insulating film 102 or a part of the second insulating film 104 is damaged, all accumulated charges may leak from the damaged portion. However, in this embodiment, since charges are accumulated in the insulating film in which the charge transfer in the film is unlikely to occur, the first insulating film 102 and a part of the second insulating film 104 are damaged. However, it is highly reliable from this point of view because all the accumulated charges do not leak at once, only the charges in the vicinity leak.
In addition, since charges are localized in the film, a memory cell can be formed without dividing the charge storage film 225 in the word line direction, and simple manufacturing is possible as described above. It is.

  In the present embodiment, the accumulated charge 226 after writing is localized in the vicinity of the end of the diffusion region (A) 107. Therefore, when erasing, the substrate 101 is set to the ground potential and the diffusion region (A) 107 is obtained. It is preferable to apply a positive erase voltage (for example, 5V) to the gate electrode 105 and a negative erase voltage (for example, −8V) to the gate electrode 105 and use an erase method using a band-to-band tunnel. As a result, a hot hole is generated at the end of the diffusion region (A) 107 and injected into the charge storage film 225, whereby the stored charge 226 is erased. Since it is limited to the region 227, the charge in the charge storage film 225 after erasure can be eliminated as much as possible, which is suitable for repeated writing and erasing. By this method, erasing can be performed at a relatively low voltage in a short time.

In particular, when the charge storage film is an insulator as in the present embodiment, it is important to improve the rewriting resistance to match the injection region at the time of writing with the injection region at the time of erasing. Since carriers injected during writing / erasing cannot move freely in the charge storage film, which is an insulator, charge neutralization is insufficient if the injection region during writing does not match the injection region during erasing As a result, the charge remaining in the film is generated. This remnant of charge is gradually accumulated by repeated rewriting, leading to deterioration of memory characteristics such as a decrease in read current. Here, in the above erasing method using the band-to-band tunnel, erasing is injected into a relatively limited range at the end of the diffusion region, whereas in the above writing method in which hot carriers are generated using the channel current, In the channel region other than the end of the diffusion region (drain region), hot carriers are partially generated, and this becomes a charge residue at the time of rewriting, which can cause deterioration of characteristics. Here, in the present embodiment, since the channel width near the drain region end at the time of writing is reduced and the resistance is increased, the lateral electric field at the time of writing can be concentrated at the end of the drain region.
As described above, it is important to match the implantation region at the time of writing with the implantation region at the time of erasing. However, according to the present invention, by designing the shape of the channel region, The time injection area can be matched.
This makes it possible to effectively localize the hot carrier generation position at the end of the drain region while suppressing the generation of hot carriers other than at the end of the drain region. This has the effect of preventing residual charge and preventing deterioration of the rewrite characteristics.

Even during the read operation, channel hot carriers are generated over the entire channel area by reducing the channel width near the edge of the source region where the influence of the drain electric field is the smallest and relatively reducing the resistance of other regions of the channel. The structure is difficult to read and prevents read disturb. If hot carrier injection occurs in the center of the channel, the injected carriers cannot be erased by erasing at the end of the diffusion region, and charges continue to remain.For example, even if a refresh operation by rewriting is performed, disturb deterioration is caused. You will not be able to recover. The present embodiment is a highly reliable semiconductor memory device that is resistant to repeated reading by suppressing such disturbance.
As described above, this embodiment reduces the channel width at the end of the drain region at the time of writing and the channel width at the end of the drain region at the time of reading, for a semiconductor memory device that stores information by accumulating charges in the insulating film. By having the function of increasing the size, the following effects can be achieved: (1) faster writing, (2) increased read window, (3) suppression of rewrite degradation, and (4) prevention of read disturb. A highly reliable semiconductor memory device is provided.

(Third embodiment)
The third embodiment is characterized in that the storage unit is provided not on the gate electrode but on the side of the gate electrode. That is, as shown in FIG. 6, a gate insulating film 327 and a gate electrode 105 are provided on a p-type semiconductor substrate 101 provided with an element isolation region 100 made of an insulating film such as a silicon oxide film. A sidewall-shaped memory portion including a first insulating film 328, a charge storage insulating film 325, and a second insulating film 329 is provided on the side wall portion. The semiconductor substrate on both sides of the gate electrode has a diffusion region (B) 106 and a diffusion region (A) 107 which are n-type diffusion regions formed by ion implantation and activation annealing.
Also in the third embodiment, as shown in FIG. 2, the channel width Wb (111) at the end of one diffusion region (B) 106 is changed to the channel width Wa (112) at the end of the other diffusion region (A) 107. The diffusion region (A) is operated as a drain region during writing, and the diffusion region (B) is operated as a drain region during reading. In particular, it is preferable to dispose the step portion where the channel width changes from Wb to Wa under the sidewall-shaped storage portion on the diffusion region (A) 107 side.
In the embodiment of FIG. 6, the side wall-shaped memory portion including the first insulating film 328, the charge storage insulating film 325, and the second insulating film 329 is formed on the side walls on both sides of the gate electrode 105. It does not need to be formed on both sides, and may be formed at least on the diffusion region (A) 107 side where charge injection is performed at the time of writing or erasing.

Further, as shown in FIG. 6, the gate electrode 105 and at least the diffusion region (A) 107 do not overlap, and the side wall is formed of the first insulating film 328, the charge storage insulating film 325, and the second insulating film 329. In the lower part of the storage unit, an offset structure is employed.
This structure can be obtained relatively simply by the following method, for example. That is, after forming the gate electrode 105, the surfaces of the semiconductor layer 101 and the gate electrode 105 are thermally oxidized to form the first insulating film 328, and then the charge storage insulating film 325, the second insulating film 325, and the second insulating film 328 are formed by a method such as CVD. The insulating film 329 is formed and then etched back by an anisotropic etching technique, whereby the sidewall memory portion can be formed. Further, diffusion annealing (A) 107 and (B) 106 offset from the gate electrode 105 can be formed by performing activation annealing after implanting an n-type impurity such as arsenic.
The charge storage insulating film 325 may be an insulating film having a charge storage function, and may be a silicon nitride film, various high dielectric material films such as aluminum oxide and hafnium oxide, or a laminated film thereof. It is also possible to use an insulating film (silicon oxide film or the like) containing therein a dot capable of storing charges such as a conductor. In particular, the use of a silicon nitride film has the merit that it can be most easily handled in a general production line and can be manufactured at low cost.

At the time of writing, as described above, the writing operation is performed using the diffusion region (A) 107 as the drain region and the diffusion region (B) 106 as the source region. At this time, the channel width Wb (111) and the channel width Wa (112) are set. In the vicinity, the channel resistance is high and hot electrons are generated with high efficiency. A part of the hot electrons are present on the side wall of the gate electrode 105 on the diffusion region (A) 107 side (right side of the drawing) as shown in FIG. The charge storage insulating film 325 is injected into the lower portion of the charge storage insulating film 325 to be stored charge 326.
Also in the present embodiment, the accumulated charge 326 is retained in the insulating film, and is blocked from the outside by the first insulating film 327 and the second insulating film 328. As explained, the structure is suitable for long-term holding. As shown in FIGS. 6 and 7, when the sidewall memory portions are formed on both sides of the gate electrode, a 2-bit memory is formed, and when the sidewall memory portions are formed on the right side or the left side of the gate electrode, It becomes a 1-bit memory. At the time of reading, as described above, the reading operation is performed using the diffusion region (B) 106 as the drain region and the diffusion region (A) 107 as the source region. Here, the diffusion region (A) 107 serving as the source region and the gate are performed. Since the electrode 105 has an offset structure, the magnitude of the read current is easily affected by whether or not the accumulated charge 326 exists above the offset portion, and thus information can be read.

Also in the third embodiment, as described in the first and second embodiments, the drain region side channel width is small at the time of writing and the drain region side channel width is large at the time of reading. Disturb has a strong advantage. Further, as described in the second embodiment, since the resistance on the drain region side is low at the time of reading, there is an advantage that the accumulated charge 326 has a large influence on the reading current, and the reading window is large and the reliability is high. In addition to these, in this embodiment, since there is no charge storage film between the gate electrode and the channel region, the distance between the two is short, and the structure is such that the gate electrode and the diffusion region are offset. There is a strong merit in effect, and a memory device with less off-leakage can be obtained.
The third embodiment can be used as a 2-bit memory because the side wall-like storage portions are formed on both sides of the gate electrode 105. In addition, in the case where a side wall-like storage portion is formed only on one side of the gate electrode 105, it can be used as a 1-bit memory.

  In particular, as described above, when the diffusion region (A) side (drain region side) on which writing is performed has an offset structure, generally, electric field concentration at the drain region end hardly occurs at the time of writing, and writing efficiency is low. Tend to be. The third embodiment provides a semiconductor memory device that has a high write efficiency while suppressing the read disturb while having such an offset structure. In particular, when the step portion where the channel width is switched from Wb to Wa is located under the side wall-like storage portion on the diffusion region (A) side, a particularly remarkable effect can be obtained.

(Fourth embodiment)
The fourth embodiment substantially conforms to the second embodiment, but provides a storage device that is more resistant to read disturb than this. The difference from the second embodiment is that, as shown in FIG. 8, an n-type region 430 having a lower concentration than the diffusion region (B) 106 is provided below the gate electrode 105 at the end of the diffusion region (B) 106. It is that you are.
As a result, the pn junction at the end of the diffusion region (B) 106 becomes gentle, so that the lateral electric field at the end of the diffusion region (B) 106 that becomes the drain region at the time of reading is further relaxed, and the read disturb is reduced. It is a structure that is unlikely to occur. At the same time, at the time of writing, since the low concentration region 430 is not provided on the diffusion region (A) 107 side serving as a drain region, a steep junction is formed and efficient writing is performed.

The structure of the fourth embodiment can also be obtained, for example, by performing low-concentration n-type implantation at a desired position with a resist mask before forming the gate electrode. Also, after forming the gate electrode 105, the n-type impurity can be obtained. Can also be obtained by oblique implantation from the diffusion region (B) 106 side. In particular, when a plurality of memory cells are formed on a chip, if all the cells are aligned with the diffusion regions (B) 106 and 107 (A) 107, the implantation resist for forming these diffusion regions is used. This low-concentration n-type region can also be formed by using the mask as it is and performing the oblique implantation.
Although the present embodiment has shown an example based on the second embodiment, the present invention is not limited to this. For example, the present embodiment may be applied to the first embodiment, the third embodiment, etc. effective.

(Fifth embodiment)
The fifth embodiment has the same cross-sectional shape (FIG. 4) as that of the second embodiment, and the channel width in the vicinity of one diffusion region (A) is set to the other diffusion region (B) as in the second embodiment. ) The structure is narrower than the vicinity, but has a planar structure, and a schematic plan view thereof is shown in FIG. In the fifth embodiment, the channel 108 has a channel width Wb region 508b from the diffusion region (B) 106 to the diffusion region (A) 107, a region 508c in which the channel width continuously decreases from Wb to Wa, and a channel width. It is divided into a Wa area 508a.
In the fifth embodiment, since the channel width gradually changes from Wb to Wa in the middle of the channel 108, the shape of the portion where the element isolation region 100 has a corner under the gate electrode 105 is, for example, 70 °. It is obtuse so as to have an inclination of -30 °, more preferably 60 ° -50 °. If the tilt angle is smaller than 30 ° or 50 °, the device area increases and the channel resistance does not increase, which is not preferable.
As described above, when writing or erasing is performed, an electric field is prevented from being excessively concentrated on a portion where the element isolation region 100 has a corner, and breakdown of the insulating film is prevented, so that a highly reliable memory device can be obtained. Further, when the corners are rounded, electric field concentration can be prevented.

Further, in the lithography process performed when forming the semiconductor device, the channel length of the region 508b having the channel width Wb and the channel length of the region 508a having the channel width Wa are set on the photomask so as to be larger than the misalignment margin. (At this time, the sum of the channel lengths of the region 508b and the region 508a is larger than twice the misalignment margin). At this time, even if misalignment occurs to the maximum extent, the end of the gate electrode 105 always comes over the regions 508b and 508a having a uniform channel width, and the channel width continuously changes. Since 508c comes in the middle of the channel, variations in on-current due to misalignment can be reduced.
Although the present embodiment has been applied to the second embodiment, the present invention is not limited to this. For example, the present embodiment can be applied to any of the first, third, and fourth embodiments.

(Sixth embodiment)
The sixth embodiment also has the same cross-sectional shape (FIG. 4) as the second embodiment, and the channel width in the vicinity of one diffusion region (A) is set to the other diffusion region (as in the second embodiment). B) Although the structure is narrower than the vicinity, as shown in FIG. 10, at least the channel width Wa (112) on the diffusion region (A) 607 side is defined not by element isolation but by the impurity implantation width. It is characterized by that. That is, at least on the diffusion region (A) 607 side, there is a semiconductor substrate surface 631 adjacent to the direction along the gate electrode 105 where source / drain impurity implantation is not performed, and accordingly, the channel width Wa (112 ) Is smaller than the channel width Wb (111) on the diffusion region (B) 606 side.

In forming the semiconductor memory device of the sixth embodiment, after forming the gate electrode 105, when forming the diffusion region, the shape of the implantation photomask is changed to the diffusion region (A) as shown by the convex portion 632 in FIG. On the side to be formed, the opening width may be narrowed in accordance with the channel width Wa to be formed.
In this embodiment, the channel width is not defined by element isolation, and the current path on the channel is determined by the channel widths Wb and Wa near the diffusion regions (B) and (A) and the electric field during operation. There is an advantage that the influence of the deviation is further reduced, and variation in device characteristics can be more effectively prevented.
Here, the element isolation opening width and the channel width Wb are made to coincide on the diffusion region (B) 606 side, but also on the diffusion region (B) 606 side, the width of the implantation mask 632 is made smaller than the element isolation opening width. The diffusion region (B) 606 width Wb (111) may be determined by implantation. In short, it is sufficient that Wb> Wa.
Although this embodiment has been applied to the second embodiment, the present invention is not limited to this, and can be applied to, for example, the other embodiments described above.

(Seventh embodiment)
For example, in the fifth embodiment, FIG. 12 shows a case where memory cells are two-dimensionally arranged to form a cell array. Gate electrodes 705 that also serve as word lines are arranged in the vertical direction of the drawing, and diffusion regions (B) 706 having a large channel width and diffusion regions (A) 707 having a small channel width are alternately arranged on the left and right sides thereof. In particular, when the memory cells of the fifth embodiment whose channel width continuously changes under the gate are arranged continuously in the word line direction in this way, the device isolation width is ensured by arranging them alternately left and right. However, a dense arrangement is possible, and the chip area can be reduced. In the present embodiment, cells adjacent in the horizontal direction on the paper surface are also reversed left and right in order to share the diffusion region. As described in the first embodiment, the area can be reduced by this.

  In addition, the bit line is arranged so that the contact plug dropped in each diffusion region is connected in the horizontal direction on the paper surface, and the selection transistor is appropriately arranged on the bit line so that operations such as writing, reading, and erasing are appropriately performed. In this case, however, the bit line is divided into a bit line 734 connected to the diffusion region (B) 706 having a large channel width and a bit line 735 connected to the diffusion region (A) 707 having a small channel width. Therefore, as shown in FIG. 12, the bit lines are arranged in a zigzag shape. In this way, the bit line can be divided into two types of roles: a bit line 735 that supplies a drain voltage at the time of writing and a bit line 734 that supplies a drain voltage at the time of reading. Since the read drain voltage supply capability for the latter is not required, the circuit can be simplified and the chip area can be saved.

  An arrangement as shown in FIG. 13 is also possible. In FIG. 13, when the cells are arranged in the word line direction, the arrangement is not the staggered arrangement as described above, but the same orientation, and the diffusion regions (A) 707 are connected in the word line direction to form a common region. (707b). Since the contacts 733 to the common diffusion region (B) 707b can be taken together at the end thereof, for example, the number of bit lines can be reduced, the circuit can be simplified, and the chip area can be saved. Become. When writing to a certain cell, a writing voltage is applied to the word line 705 connected to the cell and the bit line 735 connected to the cell, and the common diffusion region (B) 707b is set to the ground potential. When reading the cell, the read voltage is applied to the word line 705 connected to the cell, the read voltage is applied to the bit line 734 connected to the common diffusion region (A) 707b, and the bit line 735 connected to the cell is grounded. This can be done by setting it to a potential or the like (for example, other bit lines are charged to the same potential as the common diffusion region (A) to be in a floating state).

(Eighth embodiment)
In the eighth embodiment, a semiconductor memory device is formed on an insulating substrate such as a glass substrate or a resin substrate. By not using a semiconductor substrate, inexpensive manufacturing is possible, and a storage device is provided on various substrates, so that it is used as a storage element for each display element such as a liquid crystal display device, an organic EL display device, a plasma display, etc. It can be used for a wide range of applications.
When a substrate having low heat resistance such as a glass substrate is used as in the present embodiment, a low-temperature process is used during manufacturing. In such a case, a p-type device is used rather than an n-type device. It is preferable to form a memory cell because it is possible to perform writing and erasure repeatedly and stably and is more reliable. When a memory cell is manufactured by a process at a relatively low temperature, there is a risk of damage to the insulating film of the memory cell or the interface between the insulating film and the semiconductor layer due to high energy carriers generated during writing or erasing. In the p-type device, this damage is less likely to occur and the memory cell is more reliable.
FIG. 14 is a schematic cross-sectional view of the eighth embodiment. First, an n-type semiconductor layer 808 made of silicon or the like is provided on an insulator substrate 801 made of glass or the like, and patterned appropriately. Thereafter, by a method such as CVD, a first insulating film 802 made of a silicon oxide film, a charge storage insulating film 825 made of a silicon nitride film, a second insulating film 804 made of a silicon oxide film, etc., a metal such as tungsten A gate electrode material 805 is deposited, and a gate electrode 805 is formed by lithography and etching. In addition to the charge storage insulating film 825, various high dielectric material films and insulating films containing conductor dots may be used.

Thereafter, p-type impurity implantation is performed to form a diffusion region. At this time, as shown in FIG. 15, a photoresist mask is provided and implanted on one side of the gate electrode 805 according to the sixth embodiment. Is provided with a diffusion region (B) 806 (channel width Wb: 811) having a wide channel width and a diffusion region (A) 807 (channel width Wa: 812) having a narrow channel width Wa on the other side. As described above, the diffusion region (B) 806 having a wide channel width Wb and the diffusion region (A) 807 having a narrow channel width Wa are formed so that the implantation region at the time of writing and the implantation region at the time of erasure coincide with each other. Design the shape of the channel region. Thereby, the implantation region at the time of writing and the implantation region at the time of erasing can be matched. In general, a semiconductor layer formed on an insulating substrate is more difficult to neutralize charges at the time of rewriting than a semiconductor memory device formed on a semiconductor substrate, which causes rewriting deterioration. However, according to the present invention, the shape of the channel region can be formed so that the injection region at the time of writing coincides with the injection region at the time of erasing, so that charge neutralization at the time of rewriting becomes possible.
Further, as shown in the plan view of FIG. 15, in this embodiment, a body contact region 836 having the same n-type and high impurity concentration as the semiconductor layer 808 is provided on the same side as the diffusion region (A) 807. It has been. On this body contact region 836, contact plugs for body potential control are installed (Naturally, contact plugs are also installed on diffusion region (B) 806 and diffusion region (A) 807. (Not shown). The body contact region 836 can also be easily provided by a well-known lithography technique and implantation technique as in the case of the diffusion region formation.

  The operation of the memory device according to the present embodiment is performed in accordance with each of the above embodiments. In particular, since the present embodiment is formed as a p-type device, the applied voltage is set to a reverse bias with respect to each of the above embodiments. It can be operated. That is, regarding the write operation, when the diffusion region (B) 806 serving as the source is set to the reference potential, the write drain voltage of −6 to −15 V, for example, is applied to the diffusion region (A) 807, and the −6 to −− is applied to the gate electrode 805, for example. For example, the same reference potential as that of the source can be applied to the 18 V write gate voltage and the body contact region 836. Regarding the erase operation, when the body contact region 836 is set to the reference potential, the diffusion region (A) 807 has a negative erase voltage (for example, −8 to −15 V), and the gate electrode 805 has a positive erase voltage (for example, 5 to 20 V). This can be done by applying. In the read operation, when the diffusion region (A) 807 is used as a source and this is set as a reference potential, for example, a read drain voltage of −4V is applied to the diffusion region (B) 806 serving as a drain, and a −4V read gate is applied to the gate electrode 805. This can be done by applying a voltage. The body contact region 836 at the time of reading may be floating, but a more stable reading operation can be performed by applying an appropriate voltage such as the same reference potential as the source.

  In this embodiment, it is a thin film transistor type nonvolatile memory cell, but since a large amount of hot carriers are generated particularly during a write operation, a body contact is provided in order to prevent malfunction due to the generated carriers and a decrease in write efficiency. It is preferable to control the body potential. Here, the present embodiment is advantageous in that the body contact region 836 is provided on the same side as the diffusion region (A) 807 functioning as a drain region at the time of writing, and holes generated in the vicinity of the drain region at the time of writing. Since the semiconductor layer 808 under the gate electrode 805 in the depletion state does not need to move over a long distance and is efficiently discharged from the nearby body contact region 836, fluctuations in body potential can be suppressed. Stable writing operation is possible by suppressing variation between elements. At the same time, since the body contact region 836 is provided on the side of the diffusion region (A) having a small channel width, the layout can be compactly accommodated, and there is also an advantage of space saving that enables a high-density layout.

Here, between the diffusion region (A) 807 and the body contact region 836, a high voltage difference is applied in the opposite direction to the junction at the time of writing, but since the single crystal substrate is not used in the present embodiment, A structure in which a thin n-type region 831 is sandwiched between them is more preferable. Rather than making body contact region 836 and diffusion region (A) 807 directly adjacent to each other, sandwiching thin n-type region 831 in this way can reduce reverse leakage current and reduce power consumption. be able to.
Further, as shown in FIG. 15, the body contact region 836 may be disposed so as to reach the end of the gate electrode 805. With this structure, when performing erasing using a band-to-band tunnel, a negative voltage applied to the gate electrode 805 causes holes to flow from the body contact region 836 under the gate electrode 805 to form an accumulation layer, and from a site where carriers are generated. Since a low-resistance current path to the body contact region 836 can be formed, stable high-speed erasing can be performed.

In general, when a semiconductor memory device is formed over an insulating substrate, the crystallinity of the semiconductor layer 808 and the interface state between the semiconductor layer 808 and the insulating film 802 are not favorable as compared with the case where a single crystal semiconductor substrate is used. In addition, carrier scattering tends to occur in the channel, and hot carriers tend to be generated even in the middle of the channel other than at the end of the drain region. For this reason, carriers are injected in a relatively wide range at the time of writing, and rewriting deterioration due to charge remaining after rewriting can be a greater problem than when a single crystal substrate is used. Hot carriers are also likely to occur during reading, and read disturb can be a major problem. In particular, when using inexpensive glass substrates, etc., there is a merit that the manufacturing cost can be reduced, but since it is not possible to apply a high temperature process, it is difficult to improve the crystal state of the semiconductor layer and the interface state with the insulating film. This problem tends to become obvious.
However, these problems can be very effectively suppressed by the technique of the present embodiment described above. In other words, by reducing the channel width on the drain region side during writing, the lateral electric field in the region other than the drain region end can be relaxed, and charge injection can be localized at the drain region end. There is a big effect. By reducing the channel width at the end of the source region at the time of reading, the lateral electric field other than at the end of the source region is relaxed, and reading disturb is prevented.

In addition, since the device formed on an insulating substrate has a relatively large variation in characteristics, even if the same voltage condition is applied during writing, the distribution of the internal electric field varies depending on the device, and the position where charge is injected varies. This can also cause deterioration of rewriting due to charge remaining during rewriting. Also in this regard, the technique of the present embodiment concentrates the lateral electric field at the time of writing on the end of the drain region and can suppress variations in charge injection position, so that a high yield can be realized.
In the present embodiment, the charge storage insulating film 825 is used for charge storage, but a floating gate structure may be used as in the first embodiment. However, as described in the second embodiment, if a charge leakage path occurs in a part of the first insulating film or the second insulating film, all the accumulated charges may flow out in the floating gate structure. However, when an insulating film is used as the charge storage film 825, all charges do not flow out at once. In particular, when a substrate having low heat resistance is used as in the present embodiment, a high-temperature manufacturing process cannot be used. Therefore, the first insulating film 802 and the second insulating film 804 that block the charge storage portion from the outside. In some cases, a high-density and highly insulating film cannot be formed. In this case, since there is a higher possibility that the above-described charge leak path is generated, the use of the insulating film as the charge storage film 825 is advantageous in terms of long-term charge retention and is particularly preferable.
In this embodiment, the charge storage portion is provided below the gate electrode. However, the charge storage portion may be formed in a sidewall shape as in the third embodiment.

1 is a schematic cross-sectional view of a memory cell portion of a semiconductor memory device according to a first embodiment of the present invention. 1 is a schematic plan view of a memory cell portion of a semiconductor memory device according to a first embodiment of the present invention. 1 is a schematic diagram illustrating a configuration of a semiconductor memory device according to a first embodiment of the present invention. It is a schematic sectional drawing of the memory cell part of the semiconductor memory device of 2nd Embodiment of this invention. It is a schematic sectional drawing of the write-in state of the memory cell part of the semiconductor memory device of 2nd Embodiment of this invention. It is a schematic sectional drawing of the memory cell part of the semiconductor memory device of 3rd Embodiment of this invention. It is a schematic sectional drawing of the write-in state of the memory cell part of the semiconductor memory device of 3rd Embodiment of this invention. It is a schematic sectional drawing of the memory cell part of the semiconductor memory device of 4th Embodiment of this invention. It is a schematic plan view of the memory cell part of the semiconductor memory device of 5th Embodiment of this invention. It is a schematic plan view of the memory cell part of the semiconductor memory device of 6th Embodiment of this invention. It is a schematic plan view showing the photo process for source / drain region formation of the memory cell part of the semiconductor memory device of 6th Embodiment of this invention. It is a schematic plan view of the memory cell array part of the semiconductor memory device of 6th Embodiment of this invention. It is a schematic plan view of the memory cell array part of the semiconductor memory device of 6th Embodiment of this invention. It is a schematic sectional drawing of the memory cell part of the semiconductor memory device of 8th Embodiment of this invention. It is a schematic plan view of the memory cell part of the semiconductor memory device of 8th Embodiment of this invention. It is a schematic sectional drawing of the conventional semiconductor memory device. It is a schematic sectional drawing showing the write-in operation | movement of the conventional semiconductor memory device. 1 is a schematic plan view of a semiconductor memory device of Patent Document 1. FIG.

Explanation of symbols

100 element isolation region 101 silicon substrate 102 first insulating film 103 floating gate 104 second insulating film 105 gate electrode 106 diffusion region (B)
107 Diffusion region (A)
108 Channel region 115 Memory cell 225 Charge storage insulating film 226 Stored charge 227 Region 228 where charge is stored by writing 228 Region where charge is not stored by writing 325 Charge storage insulating film 326 Stored charge 327 Gate insulating film 328 First insulating film 329 Second insulating film 430 Low-concentration n-type region 508a Channel width Wa region 508b Channel width Wb region 508c Region 606 in which channel width continuously decreases from Wb to Wa Diffusion region (B)
607 Diffusion area (A)
631 Semiconductor substrate surface 632 without source / drain impurity implantation Photoresist mask opening 705 for source / drain impurity implantation Gate electrode (word line)
706 Diffusion region (B)
707 Diffusion region (A)
707b Common diffusion region 733 Contact plug 734 Bit line 735 that connects diffusion regions (B) in the horizontal direction on the paper surface Bit line 801 that connects diffusion regions (A) in the horizontal direction on the paper surface Insulating substrate 802 First insulating film 804 Second insulating film 805 Gate electrode 806 Diffusion region (B)
807 Diffusion area (A)
808 Semiconductor layer 811 Channel width Wb of portion where diffusion region (B) and gate electrode face
812 Channel width Wa of the portion where the diffusion region (A) faces the gate electrode
831 Semiconductor substrate surface 832 in which source / drain impurity implantation and body contact implantation are not performed High concentration region for body contact 1001 Read drain voltage control circuit 1002 Write drain voltage control circuit 1003 Word line control circuit 1004 selection circuit

Claims (20)

A semiconductor layer;
A charge storage film formed on the semiconductor layer and having a charge storage function;
A gate electrode formed on the charge storage film;
A channel region formed in the semiconductor layer below the gate electrode;
Two first conductivity type diffusion regions (A) and (B) formed in the semiconductor layer on both sides of the channel region;
A control circuit for applying a predetermined voltage to the gate electrode and the two diffusion regions (A) and (B),
The channel region is formed such that the channel width Wb on the side in contact with the other diffusion region (B) is larger than the channel width Wa on the side in contact with the one diffusion region (A), and the control circuit Applies a higher voltage to the one diffusion region (A) than the other diffusion region (B) during the storage operation, and from the one diffusion region (A) to the other diffusion region (B) during reading. A semiconductor memory device that applies a higher voltage.   2. The charge storage film according to claim 1, wherein at least part of the charge storage film includes, in order from the semiconductor layer side, a first insulating film, a conductor film made of the same material as the gate electrode, and a second insulating film. The semiconductor memory device described.   The semiconductor memory device according to claim 1, wherein the charge storage film is an insulating film.   4. The charge storage film according to claim 3, wherein at least part of the charge storage film has a structure including a first insulating film, an insulator having a charge storage function, and a second insulating film in order from the semiconductor layer side. Semiconductor memory device. A semiconductor layer;
Two diffusion regions (A) and (B) of the first conductivity type formed in the semiconductor layer;
A channel region formed in the semiconductor layer between the two diffusion regions (A) and (B);
A gate electrode formed on the channel region so as to be offset with respect to at least one diffusion region (A) via a gate insulating film;
A gate sidewall insulating film formed on a sidewall of at least one of the gate electrodes on the diffusion region (A) side;
A memory cell made of an insulator having a charge trap level disposed in the gate sidewall insulating film;
A control circuit that applies a predetermined voltage to each of the semiconductor layer, the gate electrode, and the two diffusion regions (A) and (B), and the channel region is on the side in contact with the one diffusion region (A) The channel width Wb on the side in contact with the other diffusion region (B) is formed larger than the channel width Wa, and the control circuit transfers the other diffusion region (A) to the one diffusion region (A) during the storage operation. A semiconductor memory device that applies a voltage higher than B) and applies a voltage higher than that of the one diffusion region (A) to the other diffusion region (B) at the time of reading.   6. The semiconductor memory device according to claim 1, wherein the semiconductor layer includes a well region of a second conductivity type different from the two diffusion regions. 7.   The semiconductor memory device according to claim 1, wherein a ratio of the channel width Wa to the channel width Wb is 20% to 80%.   The end of the other diffusion region (B) includes a first conductivity type region having a lower impurity concentration than the other diffusion region (B) in the semiconductor layer under the gate electrode. The semiconductor memory device according to any one of the above.   The channel region includes (1) a region having the channel width Wb from the other diffusion region (B) toward the one diffusion region (A), and (2) from the channel width Wb to the channel width Wa. 9. The semiconductor memory device according to claim 1, wherein the semiconductor memory device comprises a decreasing region and (3) a region having a channel width Wa.   10. The semiconductor memory device according to claim 1, further comprising an intrinsic semiconductor region or a second conductivity type semiconductor region in a region adjacent to at least the one diffusion region (A) in the gate electrode extending direction. 11.   2. A plurality of memory cells in at least a word line direction, wherein adjacent memory cells, the one diffusion region (A) and the other diffusion region (B) are arranged alternately. 11. The semiconductor memory device according to any one of up to 10.   A plurality of memory cells are two-dimensionally arranged, and a bit line is provided in a zigzag pattern so as to connect the one diffusion region (A) and the other diffusion region (B). Item 12. The semiconductor memory device according to Item 11.   11. The semiconductor memory device according to claim 1, comprising a plurality of memory cells in at least a word line direction, wherein the other diffusion region (B) is shared by adjacent memory cells.   The semiconductor memory device according to claim 1, wherein the semiconductor layer is formed on an insulating substrate.   15. The semiconductor memory device according to claim 14, further comprising a body contact region having a second conductivity type impurity concentration higher than the well concentration on the same side as the one diffusion region (A) with respect to the gate electrode.   16. The semiconductor memory device according to claim 15, wherein a region having a low impurity concentration is provided between the body contact region and the one diffusion region (A).   17. The semiconductor memory device according to claim 15, wherein a part of the body contact region is close to or overlaps with the semiconductor layer region immediately below the gate electrode. A method of manufacturing a semiconductor memory device according to claim 8, comprising:
The method of manufacturing a semiconductor memory device, wherein the introduction of the impurity in the first conductivity type region having a low impurity concentration is performed by implanting the first conductivity type impurity at an angle of 15 ° or more with respect to the vertical after the gate electrode forming step. A method for manufacturing a semiconductor memory device according to claim 10, comprising:
Forming a gate electrode;
Providing an implantation mask;
And sequentially injecting the first conductivity type impurity in the diffusion region (A) and the diffusion region (B) by ion implantation,
A method of manufacturing a semiconductor memory device, wherein the opening width of the implantation mask in the gate electrode direction is narrower in the diffusion region (A) portion than in the diffusion region (B) portion.   20. The operation method of a semiconductor memory device according to claim 1, wherein the one diffusion region (A) and the gate electrode are connected to each other with reference to the potential of the semiconductor layer during the storage operation. A method of operating a semiconductor memory device to which a reverse bias is applied.

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