JPH0368543B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit device, and more particularly to a method for manufacturing a semiconductor device such as a semiconductor memory circuit device using a semiconductor nonvolatile memory element in which stored information can be written and erased.

2. Description of the Related Art Insulated gate field effect transistors that utilize traps in a gate insulating film or floating gates are known as semiconductor nonvolatile memory elements. In this type of insulated gate field effect transistor, when charge is injected into the trap or floating gate in the gate insulating film due to the tunnel effect or hot carriers caused by avalanche breakdown, the threshold value The voltage changes from one stable value to another. The state of one of the threshold voltages is made to correspond, for example, to a binary signal of 0, and the state of the other threshold voltage is made to correspond to a binary signal of 1.

The above charges can be removed by an appropriate method.

Therefore, the above type of insulated gate field effect transistor has the advantage of being usable as a nonvolatile memory element in which stored information can be written and erased.

A plurality of the semiconductor nonvolatile memory elements described above are arranged regularly on, for example, a semiconductor substrate, and are selected for reading or writing stored information.

The above-mentioned semiconductor nonvolatile memory element requires a high-voltage, high-level signal that reaches several times the signal level when writing, for example, compared to the signal level required for reading stored information.

However, since the signal level may be limited by the characteristics of the circuit elements, the semiconductor memory circuit device requires a circuit device specifically designed for the above-mentioned high level signals.

In addition, since the overall configuration of semiconductor memory circuit devices becomes complicated due to the use of circuit devices that process the above-mentioned high-level signals, it is necessary to prevent the semiconductor substrate used from increasing in size and to improve performance such as operating speed. must be taken into account so as not to be harmed.

On the other hand, although such semiconductor circuit devices are required to be realized mainly using insulated gate field effect transistors, they are also required to partially use bipolar transistors to improve the circuit configuration and functionality. It is required to realize a circuit device as a so-called semiconductor integrated circuit device formed on a single semiconductor substrate. It is necessary to improve the efficiency of the manufacturing process for such a semiconductor integrated circuit device, and it is therefore required to realize the electronic circuit using a simple manufacturing process.

Therefore, one object of the present invention is to provide a semiconductor memory circuit device that uses a semiconductor nonvolatile memory element and has a high operating speed.

Another object of the present invention is to provide a semiconductor memory circuit device that uses semiconductor nonvolatile memory elements and can be miniaturized.

Another object of the present invention is to provide a semiconductor memory circuit device in which individual circuit devices are arranged at desired positions on a semiconductor substrate.

Another object of the present invention is to provide a novel semiconductor memory circuit device using a semiconductor nonvolatile memory element that can electrically write and erase stored information, such as an insulated gate field effect transistor that utilizes a trap in a gate insulating film. It is about providing.

Another object of the present invention is to provide a semiconductor memory circuit device having a structure that achieves a semiconductor nonvolatile memory element in which stored information can be electrically written and erased.

Another object of the invention is to provide a circuit device suitable for processing high voltage signals.

Another object of the invention is to provide a circuit device that is less likely to be destroyed.

Another object of the invention is to provide a novel circuit device including a bipolar transistor and an insulated gate field effect transistor.

Still another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device for realizing the various electronic circuit devices described above.

The various objects and configurations of the present invention described above will become clear from the following detailed description and accompanying drawings.

Hereinafter, this invention will be explained in detail based on examples.

Although not particularly limited, in the following examples, the semiconductor non-volatile memory element uses an extremely thin silicon oxide film (oxide) and a relatively thick silicon nitride film (nitride) formed on this oxide film. Insulated gate field effect transistor (hereinafter referred to as
(referred to as MNOS). With respect to this MNOS, not only storage information can be written but also erased electrically.

FIG. 12 shows a cross-sectional view of the MNOS.
In the figure, an n-type source region 2 and a drain region 3 are formed on the surface of a p-type silicon region 1 and separated from each other, and the source/drain region 2,
For example, on the surface of the p-type silicon region 1 between the
A gate electrode made of n-type polycrystalline silicon is formed via a gate insulating film made of a silicon oxide film 4 having a thickness of 20 mm and a silicon nitride film 5 having a thickness of 500 Å. The p-type silicon region 1 constitutes the basic gate region of MNOS.

In the erased state or in the state in which no memory information is written, the gate voltage VG vs. drain current ID characteristic of MNOS is, for example, as shown in curve A in Figure 13, and its threshold voltage is a negative voltage of 4 volts. (hereinafter written as -4V).

In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

In the write operation, for example, 0V, which is approximately the ground potential of the circuit, is applied to the base gate 1, and a high voltage of, for example, +25V is applied to the gate 6.
A low voltage of approximately 0V or a high voltage such as +20V is applied to the source region 2 and drain region 3 depending on the information to be written.

A channel 7 is induced in the surface of the silicon region 1 between the source region 2 and the drain region 3 in response to the positive high voltage applied to the gate 6. The potential of this channel 7 becomes equal to the potentials of the source region 2 and drain region 3.

When a voltage of 0V is applied to the source region 2 and drain region 3 as described above, a high electric field corresponding to the high voltage of the gate 6 acts on the gate insulating film.
As a result, electrons as carriers are injected into the gate insulating film from the channel 7 due to the tunneling phenomenon. The VG-ID characteristic of MNOS changes from curve A to curve B in FIG. The threshold voltage changes from the above-mentioned -4V to, for example, +1V.

When +20V is applied to the source region 2 and drain region 3 as described above, the potential difference between the gate 6 and the channel 7 is reduced to several volts. Such a low potential difference is insufficient to cause electron injection by tunneling. Therefore,
The characteristics of MNOS do not change from curve A in FIG.

In a semiconductor memory circuit device, a plurality of MNOS are coupled to one digit line. In the write operation described above, the voltage as described above is applied to the selected MNOS. considered unselected
A voltage of approximately 0V is applied to the gate of the MNOS, or a high voltage such as the aforementioned +20V is applied to the source and drain regions.

Erasing of stored information is performed by applying a high electric field to the gate insulating film in the opposite direction to the electric field for writing. A tunneling phenomenon occurs due to this high electric field in the opposite direction, and holes as carriers flow into the gate insulating film. The electrons injected during writing are neutralized by the holes, and as a result, the characteristics of MNOS are as shown by curve B in Figure 13.
It returns to curve A again.

According to this embodiment, for the above-mentioned erasing, instead of applying a negative high voltage to the gate 6 while applying 0V to the base gate 1, for example, 0V is applied to the gate 6 as will be clearer from the description below. At the same time, a positive high voltage such as +25V is applied to the base gate 1. By applying the positive high voltage to the base gate 1 as described above, the circuit configuration for applying the high voltage to the gate 6 can be simplified. Furthermore, high voltages of the same polarity can be used for writing and erasing, and as a result, the number of external terminals of the semiconductor memory circuit device and the number of power supplies for driving the semiconductor memory circuit device can be reduced.

The characteristics of MNOS are curve A or B in Figure 13 above.
Therefore, the information stored in the MNOS is read by detecting the conduction state between the source and drain when the gate voltage VG is 0V, for example. 1 due to single polarity signal
In order to select one of the plurality of MNOS coupled to one digit line, a unit storage element (hereinafter referred to as a memory cell) is connected to MNOSQ1 and this as shown in the equivalent circuit in FIG. Series-connected insulated gate field effect transistors for switches (hereinafter referred to as MISFETs for switches)
It consists of Q2. When reading, MNOSQ
1 gate voltage is maintained at 0V, for switch
The gate voltage of MISFET is set to 0V by the selection signal.
Or a positive voltage such as +5V.

FIG. 1 shows a circuit of a semiconductor memory circuit device according to an embodiment.

The memory circuit of this embodiment includes circuits that form relatively low voltage signals such as an X decoder, Y decoder, and control circuit, and circuits that form relatively high voltage signals such as a write circuit and an erase circuit. I'm here.

Although not particularly limited, a low power supply voltage of +5V is supplied to the power supply terminal VCC for the circuit that forms the above-mentioned low voltage signal. Depending on the power supply voltage, the high level of the low voltage signal is approximately +5V, and the low level is approximately 0V, which is the ground potential of the circuit.

A high voltage terminal VPP is provided in the circuit device for circuits such as the write circuit and erase circuit.
This high voltage terminal VPP is used when the circuit device performs a write operation and an erase operation.
A high voltage such as +25V is supplied. Depending on the high voltage mentioned above, the high level of the high voltage signal is approximately +25V or +20V, and the low level is approximately +25V or +20V.
It is assumed to be 0V.

In Figure 1, MA is a memory array,
Memory cells arranged in matrix MS11 or
Contains MS22.

Memory cells MS11 arranged in the same row,
The gates of each switch MISFET Q2 of MS12 are commonly connected to the second word line W11,
The gates of each MNOSQ1 are commonly connected to the second word line. Similarly, the gates of the switch MISFETs and MNOS of the other memory cells MS21 and MS22 arranged in the same row are respectively connected to the first word line W21. , are commonly connected to the second word line W22.

Memory cells MS11 arranged in the same column,
The drains of the switch MISFETQ2 of MS21 are commonly connected to the digit line D1, and the sources of MNOS are commonly connected to the reference potential line ED1.
Memory cells MS arranged in other identical columns on the same line
12. The drain of the MISFET for the switch of MS22 and the source of the MNOS are connected to the digit line D2, respectively.
Commonly connected to the reference potential line ED2.

According to this embodiment, the memory information of the MNOS is erased by applying a positive high voltage to the base gate, so the semiconductor region forming the memory cell is It is electrically separated from the semiconductor region forming peripheral circuits such as. As will be explained later, the above semiconductor region is, for example, a p-type semiconductor region formed on the surface of an n-type semiconductor substrate.
Consists of type well area.

For the above-mentioned erasure, individual memory cells can be formed in independent well regions, or memory cells arranged in the same row or column can be formed in a common well region. Now, the entire memory cell, that is, the memory array
MA is formed in one common well region.

In Figure 1, the line WELL represents the memory array
Connected to the well region as common substrate gate of MA.

The first word lines W11 and W21 are connected to the output terminals of the X decoders XD1 and XD2, respectively,
The second word lines W12 and W22 are write circuits.
Connected to the output terminals of WA1 and WA2.

The X decoder XD1 is connected to the power supply VCC as shown in the figure.
depletion type load MISFETQ3 connected between the output terminal and the gate and source shorted.
and enhancement-type MISFETs Q4 to Q6 connected between the output terminal and the ground terminal and receiving non-inverted outputs or inverted outputs from address buffers B0 to B6 at their respective gates, essentially forming a NOR circuit. There is. When the X decoder
When selected, all the signals on the address input lines a0 to a6 become low level, and a high level signal of approximately 5V is output.

The X-decoder XD2 has the same configuration as the X-decoder XD1, except that the connected address input lines are different.

In FIG. 1, a depletion type MISFET such as MISFETQ3 is marked with a different symbol from an enhancement type MISFET as shown.

The write circuit WA1 includes MISFETs Q15 and Q16 connected in series between the first word line W11 and the output terminal (second word line W12), and a power supply to which the above-mentioned +25V voltage is applied during writing and erasing to the output terminal. connected between terminal VPP
It consists of MISFETQ19 and MISFETQ17 and Q18 connected in series between the output terminal and the ground terminal. The gate of MISFETQ15 is connected to the write control line Wl, the gate of MISFETQ18 is connected to the read and erase control line, and
The gates of MISFETQ16 and Q18 are power supply terminals
Connected to VCC.

The control circuit CRL with the configuration described later allows the write control line to be
The Wl signal is set to a low level of approximately 0V, and the signal on the control line is set to a high level of approximately +5V.
Therefore, MISFETQ15 is in an off state, whereas MISFETQ18 is in an on state. The output terminal (second word line W12) is connected in series.
It is connected to the ground terminal of the circuit via MISFET Q17 and Q18, and is therefore brought to approximately 0V.

In write operation, +25V to power supply terminal VPP
A high voltage is applied to the write control line Wl,
Let's turn MISFETQ15 on.
A high level signal of 5V is applied to the control line,
Approximately 0V to turn MISFETQ18 off.
signal is added.

On state of MISFETQ15 above and MISFETQ
18, the second word line W12
The signal level of the first word line W11 is determined according to the signal level of the first word line W11.

That is, if the driving MISFETs Q4 to Q6 of the X decoder XD1 are all turned off so as to select the first word line W11,
For MISFETQ16, Q15 and above drive
Current paths for MISFETQ4 to Q6 are not configured. Therefore, MISFETQ is connected to the second word line W12.
+25V of the power supply terminal VPP appears through the terminal 19. In other words, almost + is applied to the selected first word line.
Corresponding to the application of 5V, approximately +25V will be applied to the selected word line.

If the first word line W11 is not selected, that is,
MISFETQ4 to Q6 for driving decoder XD1
If at least one of the is turned on,
For MISFETQ16, Q15 and above drive
Output terminal (second
A current path is formed to ground the word line W12). As a result, the output terminal is brought to approximately 0V.

In the write circuit WA1, MISFETQ16 receives the power supply voltage VCC at its gate,
Q17 is used to prevent the high voltage signal applied to the second word line W12 from being limited by the breakdown of MISFET Q15 or Q18.

That is, for example, if the MISFETQ17 is omitted, the high voltage (+25V) of the second word line W12 will be applied to the drain D of the MISFETQ18. As mentioned above, a low voltage of approximately 0V is applied to the gate of MISFETQ18 from the control line vp, so the depletion layer that should spread around the drain junction of MISFETQ18 is caused by the low voltage of this gate in the vicinity of the gate. It will be limited by voltage. As a result, the drain junction of MISFETQ18 breaks down at a relatively low voltage.

If MISFETQ17 is installed as shown,
The voltage applied to the drain of MISFETQ18 is clamped to a value increased by the threshold voltage of MISFETQ17 from the power supply voltage VCC. As a result, breakdown of MISFETQ18 is prevented. MISFETQ17 has its gate connected to the power supply VCC.
Since it is connected to the drain, it has a relatively high drain breakdown voltage.

MISFETQ16 is also used for the same reason as MISFETQ17.

According to this embodiment, the configuration using the well region as described above is effectively utilized.

Load MISFETQ1 in write circuit WA1
9 is other MISFETQ15 or Q18 etc.
It is formed in a well region independent from the well region forming the MISFET. That is, MISFETQ
The 19 base gates are electrically isolated from the base gates of the other MISFETs.

As shown in the figure, the load MISFET Q19 has its base gate and source short-circuited to prevent high voltage from acting on the channel between the base gate and the source/drain.

For the connections shown, the body gate
If it is connected to the ground terminal like MISFET, the voltage required at the output terminal (second word line W12) is large, so it is due to the substrate bias effect.
The threshold voltage of MISFETQ19 increases significantly compared to other MISFETs for handling low voltages. As a result, the voltage supplied to the high voltage terminal VPP must be significantly larger than the voltage required at the output terminal (second word line W12).

On the other hand, in the case of the illustrated connection, the voltage of the body gate is equal to the voltage of the source, so that the increase in the threshold voltage of MISFET Q19 due to the body bias effect can be substantially ignored. As a result, the high voltage supplied to the high voltage terminal VPP can be made relatively small.

As mentioned above, by creating a configuration that allows the voltage supplied to the high voltage terminal VPP to be lowered, it is not necessary to make the withstand voltages of various pn junctions to which this high voltage terminal VPP is connected abnormally high. Alternatively, various undesirable leakage currents in the pn junction can be reduced. Furthermore, it is possible to prevent undesirable parasitic channels from being induced on the semiconductor surface due to the electric field from the wiring connected to the high voltage terminal VPP.

Each reference potential line ED1, ED2 of memory array MA
is connected to the write inhibit circuit IHA1.

In the write-protect circuit IHA1, a wire connected in series between the reference potential line ED1 and the ground terminal
MISFETQ20 and Q21 constitute a unit switch circuit. In this unit switch circuit
MISFETQ21 receives a control signal from the control circuit CRL via the control line r. The control signal is set at a level of +5V so as to turn on the MISFETQ21 during a read operation of stored information, and to turn off the MISFETQ21 during a write operation and an erase operation.
It is assumed to be at a level of 0V.

Therefore, the unit switch circuit sets the reference potential line ED1 to approximately 0V during the read operation.

MISFETQ22 is connected between the reference potential line ED1 and the high voltage signal line IHV. A signal is applied to the high voltage signal line IHV from a write inhibit voltage generation circuit IHA2, which will be described later, to a high voltage level of approximately +20V during write and erase operations, and to approximately 0V during read operations. Ru.

Therefore, in write and erase operations,
When MISFETQ21 of the above unit switch circuit is turned off, the reference potential line ED1 has a
The above high voltage signal line IHV via MISFETQ22
A high voltage is applied from

Between the reference potential line FD2 and the ground terminal
A unit switch circuit similar to the above consisting of MISFETQ23 and Q24 is connected, and the reference potential line ED2
and the high voltage signal line IHV is MISFETQ25.
is connected.

In the above write-protect circuit IHV1, MISFETQ2 receives +5V power supply voltage VCC on its gate.
Since the high voltage mentioned above is applied to the reference potential lines ED1 and ED2, MISFETs Q16 and Q23 provided in the write circuit WA1 are connected to MISFETs Q16 and Q23.
It is used for the same reason as 7.

MISFETQ22, Q25 are the MISFETQ1
9, in order to prevent the threshold voltage from increasing due to the substrate bias effect and to prevent the voltages of the reference potential lines ED1 and ED2 from decreasing with respect to the high voltage of the high voltage signal line IHV, separate wells are provided. Formed in the area.

Each digit line D1, D2 of memory array MA
A Y gate circuit is connected between the common digit line CD and
YGO is connected.

In the Y gate circuit YGO, the digit line D
MISFEQT11 and Q12 connected in series between Y decoder YD1 and common digit line CD constitute a unit gate circuit, which couples the digit line D1 and common digit line CD in accordance with the output of Y decoder YD1. Similarly, MISFETQ13 and Q14 constitute another unit gate circuit, and this unit gate circuit connects the digit line D according to the output of the Y decoder YD2.
2 and the common digit line.

Since a high voltage signal appears on each digit line D1 and D2 during write operation and erase operation, the unit switch circuit in the Y gate circuit YGO is as follows.
The gate receives +5V power supply voltage as shown.
Use MISFETQ12 and Q14.

Y decoders YD1 and YD2 are the X decoders
Non-inverted signals a7 to a1 of address signals A7 to A10, which have a similar configuration to XD1 and XD2, and are output from address buffers B7 to B10.
By selectively receiving 0 and inverted signals 7 to 10, the respective output lines Y1 and Y2 have
High level of +5V when selected, and when not selected
Outputs a decode signal that becomes 0V.

The common digit line CD connected to the Y gate circuit YGO has a sense circuit IOS and a data input circuit.
IOW is connected.

The sense circuit IOS consists of a load MISFETQ47 whose gate and source are connected as shown in the figure, and a switch MISFETQ whose gate receives a signal from a connection line r.
It consists of 48. In the lead-out operation, the switch MISFETQ48 is turned on by setting the signal on the line r to a high level of +5V.

The output of the sense circuit IOS above is the inverter I1
4, I15, NOR circuit NR3, NR4 and
It is supplied to the output buffer circuit IOR consisting of MISFETQ49 and Q50.

In the output buffer circuit IOR, the NOR circuit NR
3. One input terminal of each of NR4 is the control line
Connected to CS1. The signal on the control line 1 is set to a low level of 0V during the read operation,
Set to high level of +5V during write and erase operations. The other input terminal of the NOR circuit NR3 is connected to the output terminal of the inverter IN14, and NR4
The other input terminal of the inverter IN15 is connected to the output terminal of the inverter IN15 which receives the output of the inverter IN14.

Therefore, the NOR circuits NR3 and NR4 output signals having opposite phases to each other during the read operation. The series-connected MISFETs Q49 and Q50 are push-pull driven by the NOR circuits NR3 and NR4.

When the signal on the control line 1 is at high level, the NOR circuits NR3 and NR4 both output low level signals of 0V, and both MISFETs Q49 and Q50 are turned off. Above output buffer circuit
The output terminal of IOR is connected to input/output terminal PO. In the simultaneous off-state of MISFETs Q49 and Q50, the output buffer circuit has a significantly high output impedance and therefore does not limit the input signal applied to the input/output terminal PO.

In the above output buffer circuit IOR, the power supply terminal
The above connected between VCC and the output terminal
MISFETQ49 is formed in a well region independent from the well regions of other MISFETs. The well region as a substrate gate is connected to its source. As a result, the increase in threshold voltage due to the body bias effect is substantially eliminated, so that the output buffer circuit IOR can output a substantially high level signal of the voltage power supply VCC.

As shown in the figure, the data input circuit IOW includes an input buffer circuit IN16, a MISFETQ51 controlled by the output of this input buffer circuit, and a MISFETQ51 that is controlled by the output of this input buffer circuit.
MISFETQ51 drain and common digit line
The MISFET Q52 is connected between the MISFET Q52 and the CD, and receives a signal from the control line Wl at its gate.

The write inhibit voltage generating circuit IHA2 is composed of MISFETs Q26 to Q36 as shown in the figure. The MISFETQ26 to Q28 constitute a first high voltage inverter, and upon receiving a low voltage control signal from the control line Wl, output a high voltage signal to the output terminal, that is, the drain of the MISFET Q27. The connections shown vary the output signal level from approximately 0V to VPP.
MISFETQ29 to Q31 constitute a second high-voltage inverter, and output a high-voltage signal to the drain of MISFETQ30 by receiving the same signal as the first high-voltage inverter. Its output signal level varies from approximately +5V (VCC) to VPP. MISFETQ32 to Q36 constitute a high voltage push-pull circuit. 1st and 2nd above
MISFETQ28, Q3 that receives control signals in the high voltage inverter and push-pull output circuit of
1. Connected between Q36 and each output terminal, and receives +5V power supply voltage on the gate.
MISFETQ27, Q30, Q35 are as described above.
Like MISFETQ16, Q17, etc., it is used to ensure high output voltage of the circuit. Load MISFETQ2 in the first and second high voltage inverters
6, Q29 is configured such that the body gate is connected to each source as shown in the figure, eliminating the drop in output voltage due to the body bias effect and sufficiently driving MISFET Q33, Q32, and Q34 of the push-pull output circuit. There is.

In the above push-pull output circuit,
MISFETQ32 is used to limit the voltage applied to the drain of MISFETQ33 when the output of the first high voltage inverter is approximately 0V.
In other words, the output of the first high voltage inverter is approximately
When the voltage is 0V, the reference potential of the second high voltage inverter is a low voltage of +5V, so the voltage is +5V.
Outputs 5V. As a result, +5V is applied to the gate of MISFETQ32, and the drain voltage of MISFETQ33 is limited. MISFETQ3
4, after the output line IHV is set to a high voltage of +20V due to the outputs of the first and second high voltage inverters becoming high voltages, the outputs of the first and second high voltage inverters become approximately When it reaches the low level of 0V,
It is used to limit the high voltage applied from the output line IHV to the source of MISFETQ33. As a result, undesired breakdown of the source and drain junctions of the switched MISFET Q33 is prevented.

The erase circuit ERS is MISFETQ40 or Q42
A push-pull circuit includes MISFETs Q43 to Q46 and a bipolar transistor Q44. The high voltage inverter has the same configuration as the write inhibit voltage generation circuit IHA2.

In the push-pull output circuit, bipolar transistor Q44 and MISFET Q43 are connected in parallel and driven by the output of the high voltage inverter. The well region forming the memory array constitutes a heavy capacitive load for the erase circuit, as will be apparent from the structure of the circuit arrangement described below. Therefore, the erase circuit ERS is required to have a sufficiently low output impedance characteristic in order to perform a high-speed erase operation. Bipolar transistors are used in semiconductor integrated circuit devices, even though they are formed with relatively small dimensions (area).
It exhibits sufficiently low operating resistance characteristics. Therefore, as shown in the figure, the erase circuit ERS, which uses the bipolar transistor Q44 as an output transistor, can be used in a memory array even if it is formed in a small area in a semiconductor integrated circuit device.
Drive the MA well region at a sufficiently high speed. the above
The structure and manufacturing method of the bipolar transistor formed on the same semiconductor substrate as the MISFET will be explained later.

In the erase circuit ERS, when only the bipolar transistor Q44 is used, the threshold voltage (base-emitter voltage) of this bipolar transistor is, for example, 0.6V.
Even if the high voltage inverter composed of MISFETs Q40 to Q42 outputs a signal of approximately the power supply voltage VPP, the voltage signal output to the output line 1 is lowered by the threshold voltage of the transistor Q44.

The illustrated erase circuit ERS is a depletion type in which the base gate is integrated with the base gate of the load MISFETQ40 of the high voltage inverter, and the gate together with the base gate is connected to the source of the load MISFETQ40, that is, the output terminal of the high voltage inverter. MISFET Q43 is connected in parallel with the bipolar transistor Q44. the above
In the MISFETQ43, the high potential of the base gate rises almost to the power supply voltage VPP, so there is virtually no increase in threshold voltage due to the body bias effect. Therefore, the high voltage on output line l is
The MISFETQ43 allows the voltage to be raised to almost the power supply voltage VPP.

The base gate of the MISFETQ 43 may be connected to its source, ie, the output line l, through the connections shown. Even in this case, it is possible to prevent the output level of the output line l from decreasing due to the substrate bias effect. However, if you do this, MISFETQ4
The well region serving as the base gate of Q43 cannot be shared with the well region serving as the base gate of Q43, and must be separated from each other. The requirement for a certain spacing of the well regions from each other has the disadvantage that the required area of the semiconductor substrate must be increased.

The control circuit CRL is connected to the inverter IN1 or IN1.
2. NAND circuit NA1 to NA4, NOR circuit
NR1, NR2 and series connected MISFETQ37
or Q39. This control circuit CRL is
The write inhibit voltage generation circuit IHA receives a write control signal, a chip selection signal, and a write and erase signal to the external terminals PGM and VPP, respectively.
line 1 by receiving the output signal from 2,
Control signals are output to r, Wl, and.

The signal supplied to the terminal VPP is a high voltage signal of +25V which is shared as a power supply voltage for the write circuits WA1 and WA2, the write inhibit voltage generation circuit IHA2, and the erase circuit ERS.

The control circuit CRL uses MISFETQ as described above to control the write or erase operation only when the signal on the terminal VPP reaches a predetermined level or higher.
It includes a level shift circuit consisting of Q37 to Q39.

The operation of the semiconductor memory circuit shown in FIG. 1 will be explained as follows using the timing charts shown in FIGS. 2 through 4. Note that FIG. 2 shows a timing chart for a read operation, and FIG. 3 shows a timing chart for an erase operation. Furthermore, FIG. 4 shows a timing chart of a write operation.

In the read operation, the write control signal at the terminal PGM is set to a low level of approximately 0V. In addition, the terminal VPP is set to almost 0V or floating, and the gate is connected to +
A nearly 0V write and erase control signal appears at the drain of MISFET Q39, which is receiving a 5V voltage VCC.

Due to the low-level write control signal at the terminal VPP and the low-level write and erase signals at the drain of the MISFET Q39, the signals on the control lines r and are at high level, and the signal on Wl is at low level.

Therefore, each reference potential line ED of memory array MA
1 and ED2 are set to almost 0V by the write inhibit circuit IHA1, and the respective second word lines W12,
Similarly, W22 is set to approximately 0V by write circuits WA1 and WA2.

The timing is not particularly limited, but for example, the time
At t0, the signals at address input terminals A0 to A10 are set corresponding to the selected memory cell. For example, if the memory cell to select is MS1
1, the output of the X decoder XD1 becomes high level due to the outputs of the address buffers B0 to B6, and the output of the Y decoder YD1 becomes high level due to the outputs of the address decoders B7 to B10.

As a result, there is a connection between the drain of MNOSQ1 of memory cell MS11 and the common digit line CD.
A current path is formed via MISLETQ1, Q10, digit line D1, and MISFETQ2 for switch. Also, due to the high level of the signal on the control line r, the common digit line CD and the sense circuit
A current path is formed between the IOS and the load MISFETQ47.

MNOSQ1 of memory cell MS11 is shown in FIG. 13A.
If the output line of the sense circuit IOS is in the on state as shown in the characteristics of
It will be grounded via 1. As a result, the output line of the sense circuit IOS becomes low level. If MNOSQ1 of the memory cell MS11 is in the off state as shown in the characteristics shown in FIG. 13B, then the load
The current path for MISFETQ47 is not configured,
As a result, the output line of the sense circuit IOS becomes high level.

At time t1, the chip selection signal at the terminal is changed from high level to low level, and at approximately the same time t2, the signal on control line 1 becomes low level. As a result, the output buffer circuit IOR comes to output a signal corresponding to the output level of the sense circuit IOS from the high output impedance state. For example, if the sense circuit IOS is outputting a high level signal, the output buffer circuit IOR outputs a high level signal to the output terminal.

When the chip selection signal returns from low level to high level at time t3, the signal on control line 1 changes from low level to high level at approximately the same time t4, and in response, the output buffer circuit IOR returns to the high output impedance state. Become.

For the erase operation, a +25V write and erase signal is applied to the terminal VPP in advance, and a 0V low-level chip selection signal is applied to the terminal.

The signal on the control line is at a high level due to the chip selection signal at the above level, so the write circuits WA1 and WA2 set the second word lines W12 and W22 to approximately 0V.

As shown in FIG. 3, when the write control signal is set to high level at time t10, the output of NAND circuit NA4 becomes low level in response. The erase circuit ERS outputs a high voltage of +25 to the output line 1 because its MISFETs Q42 and Q46 are turned off by the low level signal of the NAND circuit NA4.

As mentioned above, since the signals on the second word lines W12 and W22 are set to 0V, the erase circuit ERS
When the well region WELL is brought to a high voltage of +25V by the output of , a high voltage for erasing is applied to the gate insulating film of the MNOS of the memory array.

The positive voltage in the well region is the voltage of the memory cell.
This direction biases the source and drain junctions of MNOSQ1 and switch MISFETQ2 in the forward direction. Therefore, if a current path is formed between at least one of the reference potential lines ED1, ED2 and the digit lines D1, D2 and the ground terminal of the circuit, the voltage to be applied to the well region will decrease.

The illustrated circuit operates as follows to prevent the voltage drop in the well region described above.

The signal on the control line r becomes low level in response to the write control signal becoming high level at time t11, which is substantially the same as time t10.

MISFETQ21, Q24 of the write inhibit circuit IHA1 and MISFET Q3 of the write inhibit voltage generating circuit IHA2 are activated by the signal on the control line r.
6 is turned off. As a result, each reference potential line ED1, ED2 of the memory array is substantially floated.

The signal on the control line Wl is at a low level in response to the low level of the chip selection signal. Therefore, MISFETQ52 in the data input circuit IOW connected to the common digit line CD is in an off state. On the other hand, MISFETQ48 in the sense circuit IOS connected to the common digit line CD is turned off by the signal on the control line r.

Due to the floating of common digit line CD, each digit line D1, D2 of memory array MA becomes floating regardless of the operation of Y gate YGO.

At time t11, when the signal at terminal PGM returns to low level, the erase circuit responds to this.
The ERS output also returns to low level.

As described above, the erase operation is performed in the chip selected state, whereas the write operation is performed in the chip non-selected state, that is, when the signal at the terminal CS is at a low level. For a write operation, a +25V write and erase signal is applied to the terminal VPP in advance.

At time t20, an address signal is set to select, for example, memory cell MS11. That is, the first word class W1 is processed by the X decoder XD1.
1 is set to a high level, and the line Y1 is set to a high level by the Y decoder YD1.

At time t21, the information to be written is transferred to terminal P0.
added to. If the information to be written is 0, the terminal
P0 is brought to 0V and the data input circuit responds accordingly.
IOW's MISFETQ51 is the input buffer circuit IN
It receives a high level signal of +5V from 16 and turns on. The write state is 1, that is, for example +
If it is 5V, the MISFETQ51 is turned off by the 0V output from the input buffer circuit IN16.

When the write control signal on the terminal PGM becomes high level at time t22, the signal on the control line Y becomes low level at time t23 after a slight delay time caused by inverters IN1, IN2 and NOR circuit NR2 in the control circuit CRL. . As a result, MISFETQ21 of write-protected circuit IHA1,
Q24, Write inhibit voltage generation circuit IHA2
MISFETQ36 and sense circuit IOS MISFETQ
48 is turned off.

Time t24 after a slight delay from the above time t23
At this point, the signal on the control line becomes low level.
The write inhibit voltage generation circuit IHA2 outputs a high voltage of approximately +20V to the line IHV due to the signal on the control line, and in response, each reference potential line ED1 and ED2 of the memory array is set to the above +20V. Become.

At almost the same time as the above time t24, the control line We
signal becomes high level. In response, MISFETQ52 of the data input circuit 20W is turned on. At the same time, the write circuit WA
1. MISFETQ15 of WA2 is turned on.

When the signal on the output line IHV of the write inhibit voltage generation circuit IHA2 becomes sufficiently high voltage, this line
The control circuit CRL receiving the IHV signal outputs a low level signal to the control line at time t25.
The signal on the above control line is used as a write start signal, as will be explained next. As described above, by configuring the configuration to output the write start signal after the signal on the line IHV reaches a sufficient write inhibit level, it is possible to prevent information from being erroneously written to memory cells that are not selected. can.

As mentioned above, when the signal on the control line becomes low level, the write circuit WA
1, MISFETQ18 of WA2 is turned off.
The write circuit WA1 outputs a high voltage of approximately +25V to the second word line W12 since the first word line W11 is selected and is set at approximately +5V.

Since the first word line W21 is not selected and is set at approximately 0V, the write circuit WA2 outputs approximately 0V to the second word line W22 accordingly.

In the memory cell MS11 to be selected
MNOSQ1 is MISFETQ2 for switch, digit line D1, MISFETQ12 for Y gate MGO,
Q11, common digit line CD and MISFETQ5
MISFETQ51 receives the output of input buffer circuit IN16 via MISFETQ51. If the information to be written is 1, the ON state of MISFETQ51 causes the information in the memory cell MS11 to be
MNOSQ1 has its drain and source almost
becomes 0V, and its gate (second word line W22)
Electrons are injected into the gate insulating film by the high voltage. If the information to be written is 0, the above
Due to the OFF state of MISFETQ51, the source and drain of MNOSQ1 in the memory cell MS11 are set to +20V of the write inhibit voltage generation circuit IHA2. Therefore, the electrons mentioned above are not injected. A second word line W is connected to the memory cell MS21 in another row coupled to the same digit line D1.
Since the signal of 22 is set to almost 0V as mentioned above,
No information is written.

The other digit line D2 is connected to the corresponding Y gate.
Since MISFETQ13 in YG0 is in the off state, it is maintained at +20V by the output of write inhibit voltage generation circuit IHA2.

The write control signal at terminal PGM is at time t26.
As shown in Figure 3, the control line goes low at times t27, t28, and t29, respectively.
The signals at vP, , r become high level.
Accordingly, the second word line w12, the reference potential line
The signal of ED1 also becomes almost 0.

The semiconductor memory circuit of the present invention can have a relatively large capacity, for example 16K bits.

FIG. 5 shows a block diagram of a semiconductor memory circuit using the circuit of FIG.

In FIG. 5, the memory array MA is, for example,
It includes 16,384 memory cells arranged in 128 rows and 128 columns. For the memory array MA, an X decoder XD is provided which selects 128 memory cell rows by receiving 7-bit address input signals from address buffers B0 to B6. Also, 8 select each 16 memory cell rows.
Y gates YG0 to YG7 are provided, and these Y gates are controlled by a Y decoder YD which receives 4-bit address input signals from address buffers B7 to B10. Corresponding to the Y gates YG0 to YG7, input/output circuits I0 to I7 each include a sense circuit, an output buffer circuit, and a data input circuit as shown in FIG.
is provided. MISFETQ20 or Q as shown in Figure 1 corresponding to each memory cell column.
A write inhibit circuit IHA including 22 and one write inhibit voltage generating circuit is provided, and a write circuit WA is provided corresponding to the memory cell row. Furthermore, a control circuit CRL and an erase circuit QRS are provided.

Therefore, the semiconductor memory circuit shown in FIG. 5 stores 8 bits of information in 11 bits, that is, 2048 addresses.

As mentioned above, the configuration of the X-decoder can be simplified by configuring the memory cell with MNOS and switch MISFET and making the X-decoder and write circuit independent circuits. . Therefore, it becomes easy to speed up the selection of word lines by the X decoder, and it becomes possible to provide a memory circuit that operates at high speed.

MISFETQ22,Q in write protection circuit
The source of 25 is connected to the reference potential line ED as shown in Figure 1.
Instead of being connected to digit lines D1 and ED2, for example, they may be connected to digit lines D1 and D2. Even in the above case, it is possible to supply the write inhibit voltage to the memory array. However, if the above is done, stray capacitance such as the junction capacitance and wiring capacitance of the MISFETs Q22 and Q25 will be coupled to each digit line D1 and D2, and as a result, when reading and writing stored information, each digit line Care must be taken because the speed of signal change is limited. As shown in Figure 1, MISFETQ22,Q2
5 to the reference potential lines ED1 and ED2, the signal change speed of the digit line can be increased.

Each of the circuits described above is formed on one semiconductor substrate using semiconductor integrated circuit technology.

According to the present invention, each of the circuits described above is formed on a semiconductor substrate in an arrangement that does not limit the circuit characteristics and does not increase the size of the semiconductor substrate used.

FIG. 6 shows a pattern of regions for each circuit and wiring formed on the silicon substrate 1. As shown in FIG.

In the figure, an X decoder XD is placed at the center of the surface of the substrate 1. Memory array is MA
It is divided into two parts, MA1 and MA2, one of which is located on the left side of the X decoder XD, and the other MA
2 is placed on the right side.

A write circuit WAa is placed on the left side of the memory array MA1, and a write circuit WA6 is placed on the right side of the memory array MA2.

A Y gate YGa is arranged above the memory array MA1, and a Y gate YGb is similarly arranged above the memory array MA2. Above Y gate
A Y decoder YD is arranged between YGa and YGb, that is, above the X decoder XD.

The area around the memory array, X decoder, write circuit, Y gate, and Y decoder is a wiring area WIR as indicated by dots.

The above memory array MA across the wiring area WIR
Write inhibit circuits IHAa and IHAb are arranged below each of MA1 and MA2.

Around the surface of the board 1 are an input/output circuit IO, control circuits CRL1 and CRL2, and an input buffer circuit A.
1 to A12 are arranged. Also, around the above, there are bonding pads P1 for connecting various input terminals and output terminals to terminals outside the circuit device.
thru P26 are arranged.

To construct the circuit shown in FIG. 5, memory arrays MA1 and MA2 each have a size of 128 rows by 64 rows. Memory array MA1 and MA2
The corresponding first word lines of are simultaneously selected by the X decoder XD. The input line of the X-decoder XD is connected to an input buffer circuit arranged around the substrate 1 via wiring in the wiring area WIR.

Y gates YGa and YGb are simultaneously connected to corresponding memory arrays by the output of Y decoder YD.
The MA1 and MA2 digit lines are selected. The Y gates YGa and YGb are connected to the input/output circuit IO via wiring in the wiring area WIR.

Write inhibit circuits IHAa and IHAb are connected to reference potential lines of corresponding memory arrays MA1 and MA2 via wiring in wiring region WIR, respectively.

As mentioned above, embodiments of the present invention use well regions for the memory array and its peripheral circuitry.

FIG. 7 shows a pattern of a well region formed on the surface of silicon substrate 1, corresponding to the circuit arrangement shown in FIG. Figure 8 shows A- in Figure 7 above.
A sectional view from A is shown.

In FIGS. 7 and 8, independent P-type well regions 10a and 10b are formed on the surface of an n-type silicon substrate 1 to form a memory array.

Around the well regions 10a and 10b, peripheral circuits such as an X decoder, a Y decoder, a Y gate, a write circuit, a write inhibit circuit, an input/output circuit, an input buffer circuit, and a control circuit are formed separately from the well regions 10a and 10b. A P-type well region 11 is formed.

At the top of Figure 7, the output buffer circuit of Figure 1 is shown in a large size due to space limitations.
In order to form a MISFET that connects the source and the base gate like the MISFET Q49 in the IOR, independent P-type well regions 11a and 11b are formed apart from the above-mentioned P-type well region 11.

Similarly, on the left side of the receiving P-type well region 10a and on the right side of the receiving P-type well region 10b, there are independent P-type well regions 11c and 11c, respectively, in order to form a MISFET such as Q19 in the write circuit WA1 in FIG.
11d and 11e to 11f are formed. Furthermore,
At the bottom of the page in Figure 7 are the write inhibit circuit IHA1 and the write inhibit voltage generation circuit IHA2 in Figure 1.
Requires a similar independent substrate gate such as
In order to form a MISFET, P-type well regions 11g to 11h and 11i to 11j, each independent from other P-type well regions, are formed.

Although not shown in FIGS. 7 and 8, the n-type silicon substrate 1 is exposed at a predetermined portion within the P-type well region 11 in order to form a MISFET to be described later.

According to this embodiment, since various P-type well regions are formed on the n-type silicon substrate 1 as described above, various effective elements such as transistors for semiconductor memory circuit devices can be formed. I can do it.

For example, channel stoppers for preventing parasitic channels are formed on the surface of the n-type silicon substrate 1 between a plurality of P-type well regions by impurity ion implantation, as will be described later. Channel stops are effectively used.

That is, for example, FIG. 9 shows a cross-sectional view of a MISFET that provides high breakdown voltage characteristics. In the figure, 11m is a P-type well region, and 21 is a substrate 1 extending over a part of the well region 11m.
an n-type channel stopper formed on the surface of the
95 and 96 are n ⁺ type source region and drain region, 63
is a gate insulating film made of silicon oxide, 60
1 is a thick silicon oxide film that covers the surface of the substrate 1 and the well region other than the region where elements such as MISFET are formed; 84 is a gate electrode made of n-type polycrystalline silicon; 120 is an insulating film made of, for example, phosphosilicate glass; Reference numerals 121 and 122 are a drain electrode and a source electrode made of, for example, vapor-deposited aluminum, respectively.

In FIG. 9, the substantial drain region of the MISFET is the region 9S for contacting the electrode 121.
and a channel stopper 21. The channel stopper 21 is connected to the n-type substrate 1.
The impurity concentration is relatively low to prevent parasitic channels from being induced on the surface. Therefore, the portion of the channel stopper 21 extending above the P-type well region 11m has a sufficiently higher resistivity than the region 95 for contacting the electrode 121. The MISFET shown in FIG. 9 has a channel stopper as part of the drain region as described above, and therefore has a large drain breakdown voltage.

Therefore, in the embodiment, the n-type substrate 1 is connected to the high voltage terminal VPP (see Figure 1), and the MISFET whose drain is connected to this high voltage terminal VPP is connected.
Assume that the MISFET has the structure shown in Fig. 9 above. In other words, the write inhibit voltage generation circuit IHA2 in FIG.
Depression type MISFETQ26,Q
29, Q32, depletion type MISFETQ19 in write circuits WA1, WA2, depletion type MISFETQ4 in erase circuit ERS
0, Q43 and the enhancement type MISFET Q37 in the level shift circuit or voltage divider circuit Q37 to Q39 in the control circuit CRL.
Let it be a MISFET with the structure shown in the figure.

In addition, the depression type MISFET mentioned above is
As will become clearer from later description, it is formed by ion-implanting a P-type impurity, for example, boron, into the surface of the P-type well region 11m below the gate electrode 84.

FIG. 10 shows a cross-sectional view of an npn transistor. In the figure, the n-type substrate 1 is used as the collector region of the transistor, the P-type well region 11n is used as the base region, and the n ⁺ -type region 97 is used as the emitter region. The above n ⁺ type deposit 97 is
These regions are formed at the same time as the source and drain regions of the MISFET. The above npn transistor is used in the erase circuit ERS of FIG.

The above-mentioned MNOS and various MISFETs may have a structure with an aluminum gate, but it is more preferable to have a structure with a silicon gate as described above.

Therefore, when explaining in detail the structure of the elements and wiring constituting each of the above circuits using silicon gate technology, the manufacturing method will first be explained for easier understanding.

Below, based on FIGS. 11A to 11O, an MNOS element, an enhancement type
A manufacturing process for forming a MOS element, a depletion type MOS element, and a bipolar transistor will be described in detail.

(A) As the substrate wafer 1, an n-type single crystal silicon (Si) wafer having a (100) crystal plane and a resistivity of 8 to 12 Ωcm (impurity concentration of about 5×10 ¹⁴ cm ⁻³ ) is used. The resistivity of this wafer is preferably as high as possible (low impurity concentration) in order to form wells with low impurity concentration with good reproducibility.
Alterable Read Only Memory (electrically rewritable read-only memory)
Since the impurity concentration of the well was set to about 3×10 ¹⁵ cm ⁻³ , a silicon (Si) wafer with the above-mentioned impurity concentration was used.

As shown in FIG. 11A, after cleaning the surface of the silicon wafer 1 with an appropriate cleaning solution (O ₃ -H ₂ SO ₄ solution or HF solution), a silicon oxide film (SiO ₂ ) of about 50 nm is formed by thermal oxidation. 2 and continue to develop CVD (Chemical Vapor
A _silicon nitride (Si ₃ N ₄ ) film 3 is formed to a thickness of approximately 100 to ₁₄₀ nm using a chemical vapor deposition (chemical vapor deposition) method. Comparisons were made between horizontal CVD equipment and low-pressure horizontal CVD equipment, but no significant differences were found. However, the film thickness obtained using a low-pressure CVD apparatus has the best uniformity, and is within ±3% within the wafer, which is convenient for microfabrication. Although there are some differences depending on the method, the appropriate deposition temperature is in the range of 700 to 1000°C. This result is also the same for the Si ₃ N ₄ film formation used below.

(B) Next, a photoresist film 4 is formed on this silicon nitride film 3 by photoetching only in areas other than the areas where wells are to be formed (between the wells). In other words, the Si ₃ N ₄ film is exposed on the surface of the region where the well is to be formed. In this state, the exposed portion of the Si ₃ N ₄ film is removed by plasma etching, and SiO ₂ is deposited on the surface as shown in FIG. 11B.
Membrane 2 is exposed. After this, the resist film 4
Using as a mask, boron (B) ions are injected into the Si substrate where there is no resist film through the SiO ₂ film 2 exposed on the surface at an energy of 75 KeV.
P-type semiconductor regions 5 and 6 are implanted at a total dose of 3×10 ¹² cm ² .

(C) Thereafter, after removing the resist film 4, well diffusion is performed in dry oxygen (O ₂ ). Since boron becomes an acceptor type impurity in Si, a P-type well is formed. 1200
After 16 hours of diffusion at .degree. C., the formed P-type wells 10 and 11 have a surface concentration of ^{3.times.10.sup.15} cm.sup. ^{-3 and} a diffusion depth of about 6 .mu.m. However, this value is a value obtained from the results of measuring the surface sheet resistance using the four-probe method and the diffusion depth using the stain etching method, assuming that the impurity distribution in the well is a Gaussian distribution. It is. The reason why well diffusion is performed in oxygen is to form a uniform well with a low concentration.

At the end of well diffusion, Figure 11C
As shown in FIG.
Silicon oxide films 12 and 13 with a thickness of 0.85 μm are formed, and an oxide film with a thickness of about 10 μm is formed on the surface of the Si ₃ N ₄ film 3. Therefore, by removing approximately 50 nm of the SiO ₂ film by full-surface SiO ₂ etching, approximately 0.8 μm thick silicon oxide films 12 and 13 remain on the well surface, and between the wells.
The surface of the Si ₃ N ₄ film 3 is exposed.

(D) Next, the Si ₃ N ₄ film 3 is heated with hot phosphoric acid (H ₃ PO ₄ ).
The approximately 50 nm thick SiO ₂ film (No. 11
Figures D14, 15, 16) are exposed. In this state, there is approximately 0.8μm on the well and approximately 0.8μm between the wells.
A 50nm SiO ₂ film is formed. In this state, phosphorus (P) ions are implanted into the entire surface at an energy of 125 KeV and a dose of 1×10 ¹³ cm ⁻² .
In this case, thick SiO ₂ films 12, 13 on the wells
serves as a mask, and phosphorus ions are not implanted into the wells except in the peripheral areas of the well regions, and phosphorus ions are implanted between the wells, forming the N-type semiconductor regions 20, 21, 22. is formed. It should be noted that the well expands laterally from the edge of the Si ₃ N ₄ film used as a mask during the well diffusion, and a difference of about 6 μm occurs at the Si ₃ N ₄ film edge (that is, the thick layer on the well). SiO ₂ film edge)
and exists at the well edge. In other words, the phosphorus ion implantation layer described above extends approximately from the well edge into the well.
It is formed up to a thickness of 6 μm. Furthermore, this phosphorus ion implantation layer has a depth of about 1 μm when measured after passing through the final heat wave.

In this way, by implanting phosphorus ions between wells in a self-aligned manner, wells (P
Hereinafter, these phosphorus implanted layers 20, 21, 22 are used as SAP.
(Self Aligned P chaunel field ion
This layer is called the insplautation layer.

As mentioned above, the p-well diffusion region is made of Si ₃ N ₄
N-type impurities are formed by heat treatment in an oxidizing atmosphere using the film as a mask, and N-type impurities are implanted into the N-type substrate surface between the wells, using the thick oxide film formed on the well surface as a mask, spanning each well. By adopting a method of forming an SAP layer to prevent channel generation, ion implantation between wells can be performed without increasing the number of masks, and the well diffusion region and the ion implantation layer between wells are self-aligned. can be formed,
This technique will hereinafter be referred to as the SAP method.

After this, the SiO ₂ formed on the Si substrate surface
All films 12, 13 and 14, 15, 16 are removed. In this state, p-type well regions (10, 11) and n-type (having an impurity concentration higher than the substrate n-type impurity concentration) regions (20, 21, 22) are formed on the Si substrate surface. An unevenness 17 (step) of approximately 0.4 to 0.5 μm is formed at the boundary between the two. Using this step, mask alignment for the next photoetching process can be performed.

Next, the so-called LOCOS (Local
Oxidation of Silicon) A process called oxidation is performed.

(E) First, as mentioned above, after removing all the SiO ₂ film on the Si surface, a layer of approximately 50 nm is deposited on the front surface of the substrate.
A SiO ₂ film 24 is formed by a thermal oxidation method. Subsequently, by _CVD method, 100 ~
A 140 nm Si ₃ N ₄ film is formed.

Next, by photoetching, a photoresist film is left only in predetermined areas such as areas where active elements are to be formed (35 in FIG. 11E,
36, 37, 38, 39, 40). That is, in this state, the photoresist film is removed and the Si ₃ N ₄ film is exposed on the surface of the portion where it is necessary to form a thick oxide film for isolation between elements. Perform plasma etching in this state,
The exposed Si ₃ N ₄ film was removed to expose the previously formed SiO ₂ film 24 of about 50 nm on the surface. After that, using the resist film as a mask, boron (B) ions are injected into the Si substrate in the areas where there is no resist film through the SiO ₂ film 24 exposed on the surface at an energy of 75 KeV and a total dose of 2×10 ¹³
implanted at cm ^-2 , p-type semiconductor layers 41, 42, 4
3, 44, 45, 46 are formed. At this time, the photomask is designed so that the end of the Si ₃ N ₄ film is located within the SAP implant layer at the well end where it is necessary to form a high voltage DMOS. In this way, as shown in FIG. 11E, an active region is formed spanning the SAP layer 21 and the well. Note that this poron ion implantation is hereinafter referred to as field implantation (F implantation).

(F) Thereafter, after removing the resist film, field oxidation is performed in wet oxygen (O ₂ ). By performing this oxidation treatment at 1000° C. for about 4 hours, a SiO ₂ film 60 of about 0.95 μm is formed on the surface of the Si substrate where the Si ₃ N ₄ film has been removed. In this state, approximately
On the part where a 0.95 μm thick field oxide film is formed, for example, on the Si surface of F20 in Figure 11,
Phosphorus from SAP and boron from F implant are mixed, and in terms of doses, phosphorus is implanted at a higher dose of 1×10 ¹³ cm ^-2 and boron is implanted at a higher dose of 2×10 ¹³ cm ^-2 . However, the amount of boron that segregates into SiO ₂ during field oxidation is larger; in other words, boron in Si _is
It depletes (depletes) at the interface with phosphorus in Si, but piles up (accumulates) at the interface with phosphorus in _SiO2 .
(See FIGS. 28 and 29), so that the surface between the wells has a high phosphorus concentration and sufficiently functions as a channel stopper. Thus said SAP method and LOCOS
By sharing the process, as mentioned above, phosphorus and boron
By making good use of the difference in behavior at the SiO ₂ interface, we implanted phosphorus at the lowest possible concentration without using a masking process (this is a method of implanting high-voltage depletion MOSFETs as described later).
Items required for use as a drain)
and boron implantation, which requires a higher dose (necessary to maintain the threshold voltage of the parasitic MOS (field MOS) to a certain degree), and ultimately increase the phosphorus concentration. becomes possible. Thus, the 11th
P-type semiconductor regions 51 to 51 under the thick oxide film on the substrate surface correspond to the p-type ion implantation layers 41 to 46 in Figure E.
56 is formed.

Now, in the state immediately after this field oxidation is performed, as shown in _FIG .
Si ₃ N ₄ films 25 to 30 with a thickness of 140 nm and an oxide film with a thickness of approximately 20 nm are formed on the surface thereof, and an SiO ₂ film 60 with a thickness of approximately 0.95 μm is formed in the field region.

(G) In this state, when the entire surface is etched with SiO ₂ to remove approximately 50 nm of SiO 2 film, approximately 0.9 μm of SiO ₂ film 60 remains in the field region, _and 50 nm of SiO ₂ film 24 and 100～
A 140nm Si ₃ N ₄ film 25-30 remains, and this
The Si ₃ N ₄ film is exposed. Continuing there,
The Si ₃ N ₄ films 25 to 30 are removed using, for example, hot phosphoric acid (H ₃ PO ₄ ) solution. In this way, the previously formed SiO ₂ film 24 of approximately 50 nm remains in the active region.
Although it is possible to use the SiO ₂ film 24 as an active MISFET gate oxide film,
An abnormal area parasitic on the edge of LOCOS (generally
(It is thought that this is a Si ₃ N ₄ film), which tends to cause defects in gate breakdown voltage, so this thin oxide film 24 and the Si 3 N ₄ film above it are removed once as shown in Figure 11G. Then, after repeating the formation and removal of SiO ₂ of, for example, 45 nm, SiO ₂ films 62 to 67 of about 75 nm, which are actually used as gate insulating films, are heated at 110°C at 1000°C in dry O ₂ , for example, as shown in FIG. 11H. Form in minutes.

(H) Furthermore, among MOS transistors, EMOS
(Enhaucement mode MOS: High threshold voltage, gate voltage 0V, current is practically 0)
In order to set the threshold voltage, boron ions are implanted into the entire surface through the thin gate insulating films 62 to 67 at an energy of 40 KeV and a total dose of 2×10 ¹¹ /cm ² (Fig. 11 H71 to 7).
6). Naturally, this boron is not implanted into the field region which has a thick oxide film, and SiO ₂ is implanted into the Si substrate surface below the active region where the approximately 75 nm SiO ₂ film is present. Driven through the membrane.

(I) Next, since the EAROM described in this example uses an E/D inverter to speed up the peripheral circuit, in addition to the EMOS mentioned above, it also uses DMOS.
(Depletion mode MOS: low threshold voltage,
It is necessary to form a device that allows current to flow at a gate voltage of 0V). In order to form this DMOS in a predetermined portion, a photoresist film is deposited on the SiO ₂ films 60, 62 to 67, and then a DMOS is formed by a photoetching process as shown in FIG. 11I.
The photoresist film on the area where it is necessary to form the photoresist film 80 is removed, and the other parts are covered with the photoresist film 80.
Using this as a mask, phosphorus ions are implanted only in designated areas (81), and the DMOS
Set the threshold voltage. Here, for example,
It was implanted with an energy of 100 KeV and a dose of 12×10 ¹² /cm ² . This also applies to the high voltage DMOS region (I81 in FIG. 11). In this way, by forming a depletion MOSFET on the boundary surface around the wells made by the self-aligned separation (SAP) method between wells, it is possible to realize It becomes possible to coexist the nonvolatile memory element MNOS and high voltage DMOS without increasing the number of photomasks.

(J) Next, after removing the photoresist film 80, a polycrystalline silicon (polySi) layer of about 0.35 μm thick is formed on the SiO ₂ film at about 580° C. by CVD method. Regarding the poly Si formation method, we compared the normal pressure method and the low pressure method, but apart from the fact that the latter has better uniformity of film thickness, there were no particularly large differences in characteristics. Subsequently, polySi was doped with phosphorus by diffusion. The conditions in this case are, for example, to deposit and diffuse P from a POCl3 source on the polySi surface at 1000°C for 20 minutes, and then to deposit and diffuse P from a _POCl3 source for 20 minutes.
The resistance of poly Si was approximately 15 Ω/□ by stretching for 1 minute.

After this, the phosphorus glass formed on the polySi surface is removed by etching with a solution containing HF, etc., and then the photoresist is left only in a predetermined area by a photoetching method, and the remaining photoresist is removed by a puelasma etching method. Posy Si was removed from areas other than those where the posy Si was present, and a gate electrode and wiring were formed using the first layer of polySi on the SiO ₂ film (J83 and 84 in FIG. 11).

Next, using the first polySi layers 83 and 84 as a mask, the gate oxide film 62 is selectively etched to partially expose the substrate surface as shown in FIG. 11J.

(K) After this, oxidation is carried out at 850℃ for 20 minutes in a wet atmosphere, and approximately 40 nm is deposited on the exposed Si substrate surface.
SiO ₂ films 85 and ₈₆ of approximately 200 nm in thickness are formed on the polySi surface (K87 in FIG. 11).
After this, the entire surface is etched with SiO ₂ film for about 60n.
By removing m of the SiO ₂ film, about 140 nm of SiO ₂ is left on the poly Si. in this way
In order to form a thick oxide film on poly Si and a sufficiently thin oxide film on the Si substrate surface,
It is important to contain at least 10 ²⁰ cm ^-3 or more of phosphorus in the polySi and to perform the oxidation in a wet atmosphere at a temperature in the range of 600 to 1000°C.

(L) Next, the SiO ₂ film 85, 8 left on the poly Si
6 as a mask (i.e. SiO ₂ in this case
(prevents etching of the highly doped first polySi layer), the exposed Si substrate surface is
After lightly etching with an etching solution containing NH ₃ - _{H 2} O ₂ and HCl - H ₂ O ₂ , a thin oxide film of approximately 2 nm (K88 in Fig. 11) was etched in N ₂ diluted O ₂ .
Formed by oxidation at 850℃ for 120 minutes, followed by
A Si ₃ N ₄ film 90 of approximately 50 nm is formed by CVD. Here, we compared the formation method of the formed Si ₃ N ₄ film using various methods as mentioned earlier, but in the end, we decided to use high temperature H ₂ annealing, which will be described later.
In either case, satisfactory characteristics could be obtained.

After this, _polySi ( _second
After depositing a layer of about 0.3 μm, it is processed by photoetching to form a second layer (second) polySi gate (L91 in FIG. 11). Subsequently, using the second layer polySi91 as a mask, 1×
Phosphorus ions are implanted into the silicon substrate at 10 ¹⁶ cm ^-2 and 90 KeV to form N-type semiconductor regions (92 to 100) such as sources and drains, and at the same time, a second layer of polySi
91 was also doped with phosphorus. At this time, the first
Since the polySi layers 83 and 94 have already been doped with phosphorus and the crystal grains have increased, there is a risk that phosphorus will be implanted into the surface of the Si substrate under the first polySi layer by implanting phosphorus ions. As shown, there is a layer of about 140 nm on the first layer polySi.
This risk is eliminated because the SiO ₂ films 85 and 86 and the 50 nm Si ₃ N ₄ film 90 are formed.

(M) Next, using the Si ₃ N ₄ film 90 formed under the second layer polySi 91 as a mask, the second layer polySi
91, 84 in a wet atmosphere, e.g. 850℃
After selective oxidation for 10 minutes, the Si ₃ N ₄ film is selectively removed using this oxide film 102 as a mask. In other words, the highly doped second polySi layer is protected from the Si ₃ N ₄ etching solution by the upper oxide film. In this state, the breakdown voltage between the second layer polySi gate and the source or drain (gate breakdown voltage) is poor, so after this, oxidation treatment is performed in a wet atmosphere at 850°C for 30 minutes to increase the gate breakdown voltage of the second layer polySi gate. In addition to improving the first layer
The shape of the edges of the polySi83 and 84 gates has been improved to improve breakdown voltage. In this state, as shown in FIG. 11M, the first polySi layer 83,
SiO ₂ films 85 and 86 with a thickness of about 0.3 μm are formed on the second layer polySi layer 91 and SiO ₂ films 102 and 104 with a thickness of about 0.2 μm are formed on the second polySi layer 91 and the source and drain n ⁺ diffusion layers.
112 is formed.

As mentioned above, a material that can withstand high temperatures, such as polysilicon, is used as the gate electrode in Figures 11J and K.
After forming a MOS device as shown in the figure, an oxide film is formed on this gate electrode using a low-temperature oxidation method, and the Si
The thin SiO ₂ film on the substrate (well) is removed, another SiO ₂ film is formed on the substrate, and Si ₃ N ₄ is added on top of it.
A film is provided, and a poly-Si gate electrode is partially formed on the film. Using the Si ₃ N ₄ film as a mask, the surface of the poly-Si gate is oxidized to form an oxide film. Using this oxide film as a mask, Si ₃ By adopting the method of removing the N ₄ film and forming the MNOS element as shown in FIG. 11M, the MNOS element is formed after the MOS, so that the deterioration of the characteristics of the MNOS element is reduced. Furthermore, since the selective oxidation method is applied to cover the gate of the MOS or MNOS with an oxide film, a device with favorable characteristics such as interlayer breakdown voltage or interlayer capacitance can be obtained.

In this way, an MNOS element is formed,
If the MNOS element formation part and the MOS element formation part are drawn using enlarged sectional views corresponding to FIGS. 11L and 11M, they become as shown in FIGS. 30 to 33. That is, as shown in FIG. 30, Si ₃ N ₄ deposited on an extremely thin SiO ₂ film 88 of 10 nm or less
A polysilicon layer 91 is partially formed on the film 90, impurities for forming sources and drains are introduced into the substrate surface using this polysilicon layer as a mask, and then a Si ₃ N ₄ film is formed as shown in FIG. The surface of this polysilicon layer 91 is oxidized as a mask, and a relatively thick oxide film (SiO ₂ ) is formed on the surface.
102 is formed. Furthermore, as shown in Figure 32,
Using this formed oxide film 102 as a mask,
The Si ₃ N ₄ film 90 is partially etched away. At this time, the thin SiO ₂ film 88 is also removed from the substrate surface, but as shown in FIG. 33, an oxide film (SiO ₂ ) 104, 10
form 5. Depending on the combination of gate electrode material and Si ₃ N ₄ film etching solution (or gas),
There is a risk that the gate electrode may also be etched, but after patterning the gate electrode as described above, oxidize it using the Si ₃ N ₄ film as a mask, cover the gate electrode with an oxide film, and use this oxide film as a mask.
Since the Si ₃ N ₄ film is etched, this method can protect the fine gate electrode even when the gate electrode material is etched by the Si ₃ N ₄ etching solution. Furthermore, as shown in FIG. 33, the SiO ₂ film 102 on the polysilicon layer 91 and the SiO ₂ film 1 formed on the silicon substrate (well) surface
Since the Si ₃ N ₄ film 90 is completely covered with 04 and 105, by performing sufficient oxidation treatment in this way, a so-called protected gate structure can be formed in a self-aligned manner. Therefore, the gate breakdown voltage of the MNOS element can be improved, and the parasitic capacitance can be reduced.

Furthermore, as understood from FIGS. 30 to 33, MNOS elements and MOS
By forming both elements and leaving the Si ₃ N ₄ film 90 only under the gate of the MNOS element, the oxidation treatment performed to improve the gate breakdown voltage of the MNOS element as shown in FIG. The end of the gate electrode of the MOS element is also oxidized to form an inverted canopy structure, and the gate breakdown voltage of the MOS element can also be improved.As a result, the gate breakdown voltage of both types of elements can be improved.

(N) Next, after completing the process shown in FIG. 11M, use the photoetching method to remove the underlying n ⁺ layer or
If it is necessary to make conductive connections with the polySi layer, remove the SiO ₂ film at (106, 112) and predetermined portions (110, 111) that need to be in contact with the p-well by etching. .
In this case, since the SiO ₂ film is etched to a thickness of approximately 0.3 μm, only a portion of the oxide film in contact with the p-type well is etched, and approximately
A 0.3 μm SiO ₂ film remains.

(O) After this, after removing the photoresist film used in the above step, the P ₂ O ₂ concentration was reduced to approximately 1 by CVD method.
A phosphorus phosphosilicate glass (hereinafter referred to as phosphorus glass) 20 is deposited, and then heat treatment is performed at 900°C for 20 minutes in an H ₂ atmosphere to densify the phosphorus glass and improve the characteristics of the MNOS element. .

Thereafter, the phosphor glass on the regions where it is necessary to make electrical connections with the above-described n ⁺ layer, polySi layer, p-type well layer, etc. is removed by photoetching. At this time, the holes 114 to 118 in the oxide film made to the light and the holes in the phosphor glass are made to share at least a part of the area,
Expose that portion of the Si substrate surface or polySi surface. In this state, the film thickness of the parts (116, 117, 60) that make contact with the p-well decreases slightly due to over-etching during photo-etching, but the film thickness is still approximately 0.2 μm.
In addition, since a SiO ₂ film of about m remains,
Using a photo-etching method, the remaining SiO ₂ film of about 0.2 μm is removed by etching so that the photoresist hole is located inside the phosphor glass hole previously drilled.

When drilling a contact hole in a two-layer film of phosphor glass and SiO ₂ film, the etching speed of phosphor glass is fast and the etching speed of SiO ₂ is slow, so if the two-layer film is drilled at once, the hole size will become large. However, as can be seen from the explanation of FIGS. 11N and 11O and partially enlarged views of FIGS. 34 to 36, First, a hole 119 is formed in the SiO ₂ film 105 on the surface of the substrate by etching using a contact mask, and then a phosphor glass 120 is deposited, and then a phosphor glass 120 is formed so as to share at least a part of the contact hole 119. glass layer 12
By drilling a hole at 0 and providing the hole 125, the drilling can be performed with higher accuracy than the design value. In addition, the third
In Figure 6, the hole 125 of the phosphor glass is slightly shifted from the hole 119 of the SiO ₂ film, but in order to prevent the metal wiring such as aluminum from breaking, the hole 119 of the SiO ₂ film It is more desirable to form the phosphor glass hole 125 so as to expose even the end surface of the SiO ₂ film.

(P) Next, after removing the photoresist used above, an Al vapor deposition film is formed on the entire surface at about 300°C. The film thickness is approximately 0.8 μm.

Next, by photo-etching, a wiring pattern is formed on the Al film as shown in FIG.
After forming 2, 123, 124 and removing the photoresist, in order to ensure contact between the above Al and the n ⁺ , polySi or p-type well,
In order to reduce surface states, heat treatment is performed at approximately 450°C for 60 minutes in an H ₂ atmosphere.

By completing the steps (A) to (P) described in abnormal detail, as shown in FIG.
In addition to an enhancement type MOS element having a gate electrode 84 and a depletion type MOS element having a gate electrode 84, an NPN type bipolar transistor consisting of semiconductor regions 97, 11, and 1 can be integrated into a single semiconductor substrate 1 without adding a special photomask. can be formed on it. In addition, 121 in the same figure is
The source or drain electrode of the EMOS element is
2 is the emitter electrode of the bipolar transistor,
123 constitutes the base electrode and the electrode of the p-type well region 11 of the transistor, and 124 constitutes the electrode of the region 22 and the substrate.

FIG. 15 shows a plan view of the memory array before forming the phosphor glass layer, and FIG. 16 shows a plan view of the memory array after forming the aluminum wiring. Also, Figures 17, 18 and 19
The figures are a cross section taken along line AA in the plane of FIG. 16, and
A BB cross section and a CC cross section are shown.

The memory array is formed on a P-type well region 10a formed on an n-type silicon substrate 1.

In FIG. 15, the source region, drain region, and channel region of the MNOS of the memory cell and the MISFET for the switch are shown separated by dashed-dotted lines. P-type well region 10a other than the areas CH1 and CH2 surrounded by the dashed line above
A thick silicon oxide film 60 is formed on the surface.

On the surface of the P-type well region 10a, a plurality of polygons are formed on the surface of the P-type well region 10a in a direction crossing the areas CH1 and CH2 through a silicon oxide film, and are used as gate electrodes of MISFETs for switching of memory cells and as first word lines. Crystalline silicon layers W11, W21, W31, W
41 are arranged.

Similarly, a plurality of polycrystalline silicon layers W12, W22, W32, and W42 are arranged, which serve as gate electrodes of the MNOS of the memory cells and serve as second word lines.

Areas not covered by each of the above polycrystalline silicon layers
An n-type impurity is introduced into the surface of the P-type well region 10a in CH1 and CH2 by the manufacturing method described above with reference to FIG. ^{A +} type region is formed.

In area CH1, n ⁺ type region 92a, polycrystalline silicon layers W11, W12 and n ⁺ type region 92a,
A first memory cell is configured. That is, n ⁺ type region 92a constitutes the drain region of the switching MISFET, and polycrystalline silicon layer W11 constitutes its gate electrode. Further, the S gate electrode of the polycrystalline silicon layer W12MNO is formed, and the n ⁺ type region 94a is formed as its source region.

In the area CH1, the n ⁺ type region 92b adjacent to the first memory cell, the polycrystalline silicon layers W21, W22, and the n ⁺ type region 94b constitute a second memory cell. That is, the above 92b, W2
1, W22 and 94b are for switches respectively
MISFET drain region, its gate electrode,
Configures the gate electrode of MNOS and its source region.

Similarly, in the area CH1, 94c,
W32, W31, and 92c constitute a third memory cell, and 92d, W41, W42, and 94d constitute a fourth memory cell.

First to fourth memory cells are also formed in the area adjacent to the area CH1, although no symbols are attached thereto.

Each memory cell formed in the area CH1 constitutes a first memory cell column and similarly forms the area CH1.
Each memory cell formed in CH2 constitutes a second memory cell column.

Polycrystalline silicon layer W11 as the first word destination
15, has extended portions W11a to W11c extending across the bottom of the polycrystalline silicon layer W12 on the thick silicon oxide film 60.

Since the polycrystalline silicon layer W12 constitutes the second word line as described above, it receives a high voltage such as +25V when writing storage information. Therefore, P under the polycrystalline silicon layer W12
A parasitic channel may be induced on the surface of the mold well region 10a. Polycrystalline silicon layer W11
constitutes the first word line and receives a low voltage signal such as +5V mentioned above. Therefore, the parasitic channel induced on the surface of the P-type well region 10a under the polycrystalline silicon layer W12 is caused by the extensions W11a to W11 of the polycrystalline silicon layer W11.
11c, respectively.

As a result, the memory cells in the areas CH1 and CH2 are electrically coupled to each other by the parasitic channel, and as a result, it is possible to prevent an undesirable operation such as information not being written to the selected memory cell. I can do it.

A phosphor glass layer 120 is formed on the surface of the memory array shown in FIG. 15 by the manufacturing method explained in FIG.
is formed, and then the phosphorus glass layer 120 and the oxide film thereunder are selectively removed to provide openings CNT1 to C5 (see FIG. 6) that expose the n ⁺ type region.

Next, aluminum is deposited and selectively etched to form aluminum wiring layers ED1, ED2, D1 and D2 as shown in FIG.

The wiring layer ED1 has the above-mentioned open-hole CNT.
1. In CNT3 and CNT5, n ⁺ regions 94a, 94b, 94c and 94d (15th
(see figure). Therefore, this wiring layer ED1
constitutes the reference potential line of the memory array.

The wiring layer D1 has the above-mentioned open-hole CNT2 and
In the CNT4, n ⁺ type regions 92a, 92b, 92c and 9 serve as drain regions of switch MISFETs in the first to fourth memory cells.
Contact 2d. Therefore, this wiring D1 constitutes a digit line of the memory array.

Similarly, the wiring layers ED2 and C2 constitute other reference potential lines and digit lines, respectively.

In the above memory array, as shown in FIG. 15, the arrangement of MNOS and switching MISFET in memory cells in the same memory column is alternately reversed. Therefore, for example, 92a, 92b, 94
The n ⁺ type regions of adjacent memory cells can be shared as shown in b and 94c, and the dimension in the column direction can be made smaller than in the case where the n ⁺ type regions for each memory cell are formed independently. be able to.

Furthermore, as shown in FIG. 16, the aluminum wiring layers ED1, ED2, D1, and D2 are inclined with respect to the direction in which the areas CH1 and CH2 extend so that the areas CH1 and CH2 where memory cells are formed also serve as wiring areas. Therefore, the dimension in the row direction, that is, in the lateral direction of the paper surface, can be made smaller than in the case where the wiring area is set independently of the above-mentioned area.

In addition, it can be used as a reference potential line and digit line.
Since an aluminum wiring layer is used as shown in the figure instead of using a semiconductor such as an n ⁺ type semiconductor wiring region, its resistance can be sufficiently reduced. The reduction in interconnect resistance allows the memory array described above to operate at high speeds.

Fig. 20 shows the pattern of the unit X decoder before forming the phosphor glass layer, and Fig. 21 shows the pattern after forming the aluminum wiring layer in the portion corresponding to Fig. 20 above. .

Since each of the unit X decoders is provided corresponding to a memory cell row of the memory array, each of the unit X decoders is taken into account so as not to increase the pitch of the memory cell row. for that,
Although not particularly limited, as explained below, the second
In FIGS. 0 and 21, the combination of two unit X decoders is substantially one unit.

In FIG. 20, the X decoder is formed on a P-type well region 11 formed on an n-type silicon substrate 1. In FIG. The region for forming each MISFET is surrounded by a dashed line in the figure. A thick silicon oxide film 60 is formed on the surface of the P-type well region 11 other than the above-mentioned region, as described above.

On the silicon oxide film 60 and the gate oxide film on the region surrounded by the one-dot chain line, first layer polycrystalline silicon layers W11, W21, a0 have a pattern as shown by the combination of dots and solid lines. ,a
0', a1, a1' are formed. In the area surrounded by the above-mentioned dashed line, except under the above-mentioned polycrystalline silicon layer, n ⁺
A mold region is formed.

In Fig. 20, the channel region of the enhancement type MISFET is formed under the polycrystalline silicon layer in the area marked with diagonal lines on the lower left and the lower right. This means that a channel region of a depletion-type MISFET is formed under the polycrystalline silicon layer where these are combined.

In the upper half of the paper ⁱⁿ FIG ^.
MISFETQ3 is configured, and enhancement type MISFETQ4 is configured by n ⁺ type region W11c, polycrystalline silicon layer a0', and n ⁺ type region GNDa,
n ⁺ type region W11c, polycrystalline silicon layer a1' and n ⁺
Enhancement type by type area GNDb
MISFETQ5 is configured.

In the lower half of the paper in Figure 20, the same
MISFETQ3', Q4' and Q5' are configured.

As shown in FIG. 21, a phosphor glass layer 120 is formed on the surface of the decoder shown in FIG. 20, and then holes are formed in the phosphor glass layer and the oxide film thereunder by selective etching.

Various aluminum wiring layers are formed by aluminum vapor deposition and selective etching as shown in FIG. In the figure, the openings provided in the phosphor glass layer and the insulating film such as the oxide film are indicated by x marks. Therefore, each aluminum wiring layer contacts the underlying polycrystalline silicon layer or semiconductor region at the x-marked portion.

In FIG. 21, the wiring layer W11a is a short circuit wiring layer, and MISFETQ3 (see FIG. 20)
The polycrystalline silicon layer W11 serving as the gate electrode of the MISFET Q4 and the n ⁺ type region W11b serving as the source region and the common drain region of the MISFETs Q4 and Q5 are short-circuited. The wiring layer VCC is a wiring layer for power supply, and MISFETQ3 and Q3' (see Figure 20)
The n ⁺ type region as a common drain region is in contact with VCCa. The wiring layer GND is a wiring layer for grounding, and is in contact with the n ⁺ type region GNDa as a common source region of MISFETQ4, Q4'. As shown in FIG. 20, the n ⁺ type region GNDb, which serves as a common source region of MISFETs Q5 and Q5', is continuous with the n ⁺ type region GNDa.

The wiring layers a0 and 0 are a pair of wiring layers that receive address signals of opposite phases to each other, and a selected one of them, that is, a0 in the illustrated case, contacts the polycrystalline silicon layer a0' and contacts the polycrystalline silicon layer a0''. are doing.

Similarly, wiring layers a1 and a1 are a pair of wiring layers that receive other address signals having opposite phases to each other. In the illustrated case, wiring layer a1 is in contact with polycrystalline silicon layer a1', and wiring layer 1 is in contact with polycrystalline silicon layer a1''.

As described above, a unit decoder such as the X decoder XD1 of FIG. 1 is configured in the upper half of FIG. 12, and another unit decoder such as XD2 is configured in the lower half.

The unit X decoders are arranged corresponding to memory cell rows. Therefore, the wiring layer VCC, GND, a
0, 0, a1, 1, etc. are common to a plurality of unit X decoders.

22A and 22B show the unit write circuit patterns before forming the phosphor glass layer, and FIGS. 23A and 23B show the patterns shown in FIGS. 22A and 22B, respectively. The pattern after forming the aluminum wiring layer in the portion corresponding to B is shown. In addition, the right end of FIG. 22A as a pattern is connected to the left end of FIG. 22B, and similarly, the right end of FIG.
The right end of Figure A connects to the left end of Figure 23B.

The patterns in FIGS. 22A, B and 23A, B are shown using the same notation as in FIGS. 20 and 21.

For the same reason as the X decoder, the two unit write circuits are essentially one unit.

Polycrystalline silicon layers W11 and W21, which serve as first word lines, are extended onto the P-type well region 10b indicated by the two-dot chain line for configuring the memory array through the thick silicon oxide film 60, and are made of aluminum. MISFETQ15 formed in the P-type well region 11 via wiring layers W11C and W21C,
It contacts the drain regions W11d and W21d of Q15'.

Note that the P-type well region 10b is in contact with an aluminum wiring layer e to which a signal from an erasing circuit (see FIG. 1) is applied as shown.

A signal from a control line We (see FIG. 1) is applied to the polycrystalline silicon layer We serving as the gates of the MISFETs Q15 and Q16.

Polycrystalline silicon layer W1 as second word line
2, W22 are aluminum wiring layers W1, respectively.
2a and W22a, MISFETQ1 formed in the P-type well region 11 indicated by the two-dot chain line
6 and Q17 common drain region W12b,
It contacts the common drain region W22b of MISFET Q16' and Q17', and also contacts the polycrystalline silicon layers W12c and W22c, respectively.

Above MISFETQ16, Q17, Q16', Q1
Polycrystalline silicon layer VCC as common gate of 7'
+5V power supply voltage is applied to.

The common drain region GNDa of the MISFETs Q18 and Q18' is in contact with an aluminum interconnection layer GND set to a ground potential.

The polycrystalline silicon layer W12c is used as the gate electrode of the MISFET Q19 formed in the independent P-type well region 11r, and the aluminum wiring layer W12
Source region W1 of MISFETQ19 by d
2e and the P-type well region 11r.

Similarly, the polycrystalline silicon layer W22c is connected to the MISFETQ formed in the other independent P-type well region 11s.
19', and is in contact with the source region W22e of the MISFET Q19' and the P-type well region 11s through the aluminum wiring layer W22d.

The above MISFETs Q19 and Q19' have the structure as explained in FIG. 9 or FIG. 11 above. The above extended on the n-type silicon substrate 1
Common drain region of MISFETQ19 and Q19'
VPPa is in contact with an aluminum wiring layer VPP to which high voltages for writing and erasing methods are applied.

The MISFETs Q15 to Q19 constitute, for example, the circuit WA1 in FIG. 1, and the MISFETs Q15' to Q19' constitute another circuit WA2.

The unit write circuits shown in FIGS. 22A and 22B and 23A and 23B are arranged in correspondence with the memory cell rows, similar to the X decoder described above.

FIG. 24 shows the pattern of the Y gate before forming the phosphor glass layer, and FIG. 25 shows the pattern of the portion corresponding to FIG. 24 after forming the aluminum wiring layer.

Polycrystalline silicon layer as common digit line
An aluminum wiring layer CDa for connecting unit gates in parallel is in contact with CD.

The above aluminum wiring layer CDa is MISFETQ1
It is in contact with the common drain region CDb of Q1 and Q13. Polycrystalline silicon layers Y1a, Y2a serving as gate electrodes of MISFETs Q11, Q13 are in contact with aluminum wiring layers Y1, Y2, which receive outputs from Y decoders YD1, YD2 (see FIG. 1), respectively.

The source region of MISFET Q11 and the drain region of Q12 are a common n ⁺ type region D1b, and similarly
The source region of MISFET Q13 and the drain region of Q14 are a common n ⁺ type region.

A power supply voltage of +5V is supplied to the polycrystalline silicon layer VCC serving as the gate electrode of the MISFETs Q12 and Q14.

The source region D1a of the MISFETQ12 is in contact with the aluminum wiring layer D1 as a digit line, and similarly the source region D2a of the MISFETQ14 is in contact with the source region D1a of the MISFETQ12.
is in contact with an aluminum wiring layer serving as another digit line.

26A and 26B show the patterns of the write inhibit circuit before forming the phosphor glass layer, and FIGS. 27A and 27B show the patterns after forming the aluminum wiring layer. 26th above
The pattern of the part corresponding to FIG. A and FIG. 26B is shown. Note that as a pattern, the lower end of FIG. 26A is connected to the upper end of FIG. 26B, and similarly, the lower end of FIG.
The lower end of Figure A connects to the upper end of Figure 27B.

As shown in Figure 6, the wiring area WIR is placed between the memory array and the write inhibit circuit, so
Although not particularly limited, the aluminum wiring layer ED as a reference potential line explained in FIGS. 15 and 16
1, ED2 are polycrystalline silicon layers ED1a, ED formed simultaneously with the polycrystalline silicon layer of each MISFET.
2a, respectively. Above wiring area
In WTR, the polycrystalline silicon layer ED1
a, Various aluminum wiring layers are formed on ED1a via an oxide film and a phosphorus glass layer.

Note that FIGS. 26A and B and FIGS. 27A and B are shown using the same notation as the previous figures. Therefore, the description of the structure of the write inhibit circuit in FIGS. 26A, B and 27A, B will be omitted.

According to this invention, as shown in FIG. 6, since the decoder and the write circuit are placed across the memory array, the operating speed, particularly the read operating speed, can be increased. On the other hand, if the decoder and write circuit are placed on one side of the memory array, for example, the wiring from the decoder to the memory cell becomes long, and since multiple circuits are placed on one side of the memory array, it is difficult to The number of well-known cross-wiring locations will increase. As a result, the signal transmission characteristics of the wiring paths that supply signals to the memory array deteriorate, and the operating speed is limited.

As mentioned above, when placing the decoder and write circuit across the memory array, the pitch between the unit decoder and write circuit can be made relatively small, so the size of the memory array does not have to be limited by these circuits. Become good.

Furthermore, since a gate or decoder and a write inhibit circuit are placed across the memory array, high-speed operation can be achieved for the same reason as above.

As mentioned above, the configuration in which a decoder and a write circuit are placed across a memory array, or the configuration in which a gate or a decoder and a write circuit are placed across a memory array, are different from other configurations that use a write circuit or a write-protection circuit. It can be applied to various types of storage devices.

According to the present invention, the well region is used as described above, and this well region can be effectively used for a high voltage circuit.

Enhancement type MISFETQ3 shown in Figure 1 above
In a voltage divider circuit in which MISFETQ37 is connected in series, the highest voltage is applied to the drain of MISFETQ37, so if MISFETQ37 is destroyed by high voltage, the destroyed MISFETQ37
A high voltage will be applied to Q38 via. As a result, the MISFETs connected in series are destroyed one after another.
However, when the highest voltage above is applied
If MISFETQ37 is made to have a structure that utilizes a well region as described above to achieve a high breakdown voltage, the above-mentioned breakdown can be prevented even if the other MISFETQ38 to Q39 have a normal structure. The voltage divider circuit as described above can be used in circuit devices other than the memory circuit device of the embodiment.

Similarly, circuits such as the erase circuit and write inhibit voltage generation circuit shown in FIG. 1 can be used for other purposes.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of a semiconductor memory circuit, FIGS. 2, 3, and 4 are operation timing charts of the circuit in FIG. 1, FIG. 5 is a block diagram of a semiconductor memory circuit, and FIG. is a plan view of the semiconductor memory circuit device, FIG. 7 is a plan view of a semiconductor substrate forming the semiconductor memory circuit device of FIG. 6, and FIG. 8 is a plan view of the semiconductor memory circuit device of FIG.
9 is a cross-sectional view of the semiconductor substrate on which the MISFET is formed, and FIG. 10 is a cross-sectional view of the semiconductor substrate on which the bipolar transistor is formed.
1A to 1O are cross-sectional views of a semiconductor substrate in each manufacturing process of a semiconductor memory circuit device, and FIG.
Cross-sectional view of MNOS, Figure 13 is the MNOS in Figure 12
14 is an equivalent circuit diagram of a memory cell, FIG. 15 is a plan view of the memory array before forming the phosphorus glass layer, and FIG. 16 is a diagram of the memory array after forming the aluminum wiring layer. Floor plan, 1st
7, 18, and 19 are cross-sectional views of the A-A', B-B', and C-C' sections of FIG. 16, respectively, and FIG. 20 is the cross-sectional view of the section before forming the phosphorus glass layer. FIG. 21 is a plan view of the X decoder, and FIG. 22 is a plan view of the X decoder after forming the aluminum wiring layer.
Figures A and 22B are plan views of the write circuit before forming the phosphor glass layer, Figures 23A and 23
Figure B is a plan view of the write circuit after forming the aluminum wiring layer, Figure 24 is a plan view of the Y gate before forming the phosphor glass layer, and Figure 25 is a plan view of the Y gate after forming the aluminum wiring layer. 26A and 26B are plan views of the gate, FIG. 26A and FIG.
7A and 27B are plan views of the write inhibit circuit after forming the aluminum wiring layer, and FIG.
Figure 3 and Figure 29 are phase diagrams showing the concentration distribution of phosphorus and boron impurities at the Si-SiO ₂ interface, respectively.
0 to 33 and 34 to 36 are cross-sectional views of the main parts of the semiconductor device for each manufacturing process. MA...Memory array, XD1, XD2...X decoder, YG0...Y gate, YD1, YD2...
Y decoder, WA1, WA2...Writing circuit,
IHA1...Write inhibit circuit, IHA2...Write inhibit voltage generation circuit, ERS...Erase circuit,
CRL...Control circuit, IOS...Sense circuit, IOR...
...output buffer circuit, IOW...data input circuit,
B0 to B10...Input buffer circuit.

Claims (1)

[Scope of Claims] 1. A method for manufacturing a semiconductor device including an MNOS element, which includes the steps of: forming a lower layer film of oxide and an upper layer film of silicon nitride to cover the main surface of a semiconductor substrate; Regions to become sources and drains are formed on the main surface of the semiconductor substrate by forming a semiconductor layer for a gate electrode thereon and introducing impurities into the main surface of the semiconductor substrate using the semiconductor layer for gate electrode as a mask. a step of forming an oxide film by oxidizing the surface of the gate electrode semiconductor layer using the silicon nitride film as an oxidation-resistant mask; A method for manufacturing a semiconductor device, comprising the step of removing the silicon nitride film exposed from the gate electrode semiconductor layer using the oxide film formed on the surface as an etching mask. 2. The method of manufacturing a semiconductor device according to claim 1, wherein after the step of removing the silicon nitride film, the surfaces of the source and drain regions are oxidized.