JPH02358A - Semiconductor storage circuit device - Google Patents

Abstract

PURPOSE:To simplify the construction of an X decoder and to enable the X decoder to select a word line rapidly, by composing a memory cell of an MNOS and a switching MISFET and providing the X decoder and a writing circuit independent of each other. CONSTITUTION:An X decoder XD is arranged at the center of a substrate 1 and memory arrays MA1 and MA2 are arranged on the opposite sides of the X decoder. Writing circuits WAa and WAb are arranged on the left- and right-hand sides of the memory arrays MA1 and MA2, respectively and Y gates YGa and YGb are arranged on the upper side while a Y decoder YD is interposed between the Y gates. Write inhibit circuits IHAa and IHAb are arranged below the memory array. Each of memory cells constituting the memory arrays consists of an MNOS element and an MOS element which are electrically connected in series between a pair of interconnections seving as a reference potential line and digit line. The gate thereof is electrically connected to the word line.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor memory circuit device, and more particularly to a semiconductor memory circuit device using a semiconductor nonvolatile memory element in which storage information can be written and erased.

2. Description of the Related Art As a semiconductor nonvolatile memory element, an insulated gate electric field (hereinafter referred to as blank space) effect transistor is known, which utilizes a trap in a gate insulating film or a floating gate. In this type of insulated gate field effect transistor, due to the tunnel effect,
Or, <When charge is injected into the trap or floating gate in the gate insulating film by hot carriers generated by Rancier breakdown, the threshold voltage changes from one stable value to the other stable value. do. The state of one of the threshold voltages is made to correspond, for example, to a binary signal of 0, and the state of the other threshold voltage is made to correspond to a binary signal of 1.

The above charges can be removed by an appropriate method.

Therefore, the above type of insulated gate field effect transistor has the advantage of being usable as a nonvolatile memory element in which stored information can be written and erased.

A plurality of the semiconductor nonvolatile memory elements described above are arranged regularly on, for example, a semiconductor substrate, and are selected for reading, reading, or writing stored information.

The above-mentioned semiconductor non-volatile memory element requires a high-level signal with a high voltage that reaches several times the signal level at the time of writing, for example, compared to the signal level required for reading the stored information.

However, since the signal repp may be limited by the characteristics of the circuit elements, the semiconductor memory circuit device requires a circuit device specifically designed for the above-mentioned high level signals.

In addition, since the overall configuration of semiconductor memory circuit devices becomes complicated due to the use of circuit devices that process the above-mentioned high-level signals, it is necessary to prevent the semiconductor substrate used from increasing in size and to ensure that performance such as operating speed is not impaired. must be considered as such.

On the other hand, power-driven semiconductor circuit devices are required to be realized mainly using insulated gate field effect transistors, but are also required to partially use bipolar transistors to improve circuit configuration and functionality. It is required to realize such a semiconductor circuit device as a so-called semiconductor integrated circuit device formed on a single semiconductor substrate. and,
It is necessary to improve the efficiency of the manufacturing process for such a semiconductor integrated circuit device, and it is therefore required to realize the electronic circuit using a simple manufacturing process.

Therefore, one object of the present invention is to provide a semiconductor memory circuit device that uses a semiconductor nonvolatile memory element and has a high operating speed.

Another object of the present invention is to provide a semiconductor memory circuit device that uses semiconductor nonvolatile memory elements and can be miniaturized.

Another object of the present invention is to provide a semiconductor memory circuit device in which individual circuit devices are arranged at desired positions on a semiconductor substrate.

Another object of the present invention is to provide a novel semiconductor memory circuit using a semiconductor nonvolatile memory element in which stored information can be written and erased electrically, such as an insulated gate field effect transistor that utilizes a trough in a gate insulating film. The goal is to provide equipment.

Another object of the present invention is to provide a semiconductor memory circuit device having a structure that achieves a semiconductor nonvolatile memory element in which stored information can be electrically written and erased.

Another object of the invention is to provide a circuit device suitable for processing high voltage signals.

Another object of the invention is to provide a circuit device that is less likely to be destroyed.

Another object of the invention is to provide a novel circuit device including a bipolar transistor and an insulated gate field effect transistor.

Still another object of the present invention is to provide a method for manufacturing a semiconductor integrated circuit device for realizing the various electronic circuit devices described above.

The various objects and configurations of the present invention described above will become clear from the following detailed description and the accompanying drawings.

Hereinafter, this invention will be explained in detail based on examples.

Although not particularly limited, in the following examples, an extremely thin silicon oxide film (
An insulated gate field effect transistor (hereinafter referred to as MNOS) having a gate insulating film having a two-layer structure of a gate insulating film formed on the oxide film Q and a gate insulating film formed on the oxide film Q is used. This MNO
With respect to S, not only storage information can be written but also erased electrically.

FIG. 12 shows a cross-sectional view of the MNOS.

In the same figure, an n-type source region 2 and a drain region 3 are formed on the surface of a p-type silicon region 10, spaced apart from each other, and on the surface of the p-type silicon region 10 between the source and drain regions 2 and 3, 20X thick silicon oxide film 4
A gate electrode made of n-type polycrystalline silicon is formed via a gate insulating film made of a silicon film 5 having a thickness of 500×. The p-type silicon region 1 is an MNOS
constitutes the basic gate area.

In the erased state or when the stored information is omitted (in the state where no stored information is left out), the MNOS guttit pressure VG vs. drain current I
The D characteristic is, for example, curve A in FIG. 13, and its threshold voltage is a negative voltage of 4 volts (hereinafter referred to as -4■).

In order to write or erase stored information, a high electric field is applied to the gate insulating film so that carrier injection occurs due to a tunneling phenomenon.

In a write operation, the substrate gate 1 has e.g.
A ground potential OV of the circuit is applied, and a high voltage of +25V, for example, is applied to the gate 6.

A low voltage of yOv or a high voltage of +20V is applied to the source region 2 and drain region 3 depending on the information to be written.

Silicon region 1 between source region 2 and drain region 3
A channel 7' is induced on the surface in response to the high positive voltage of the gate 6. The potential of this channel 7 becomes equal to the potentials of the source region 2 and drain region 3.

When a voltage of Ov is applied to the source region 2 and drain region 3 as described above, a high electric field corresponding to the high voltage of the gate 6 acts on the gate insulating film.

As a result, electrons as carriers are injected into the gate insulating film from the channel 7 due to a tunneling phenomenon. MNO
The VG-ID characteristics of S change from curve A to curve B in Figure 13. The threshold voltage changes from the above-mentioned 14V to, for example, +1V.

+20 as above for source region 2 and drain region 3
When V is applied, the potential difference between the gate 6 and the channel 7 is reduced to several square meters. Such a low potential difference is insufficient to cause electron injection by tunneling. Therefore, the characteristics of MNOS do not change from curve A in Figure 13.

In a semiconductor memory circuit device, a plurality of MNOS are coupled to one digit line. In the above write operation, the above voltage is applied to the selected MNOS. MNOS's non-selection) K is KOV
, or a high voltage such as the aforementioned +20V is applied to the source and drain regions.

Erasing of stored information is carried out by applying a high electric field to the gate insulating film in the opposite direction to the electric field for writing. A tunneling phenomenon occurs due to this high electric field in the opposite direction, and holes as carriers flow into the gate insulating film. The electrons injected during the writing are neutralized by the holes, and as a result, the characteristics of MNO3 return from the curve B in FIG. 13 to the curve HA.

According to this embodiment, for the above-mentioned erasing, instead of applying a negative high voltage to the gate 6 while applying OV to the substrate gate 1, for example, OV is applied to the gate 6 as will be clearer from the description below. The configuration is such that a positive high voltage such as +25V is applied to the base gate 1 while the voltage is applied. By applying a positive high voltage to the base gate 1 as described above, the circuit configuration for applying a high voltage to the gate 6 can be simplified. Also, it is now possible to use high voltages of the same hardness for writing and erasing.
As a result, the number of external terminals of the semiconductor memory circuit device and the number of power supplies for operating the semiconductor memory circuit device can be reduced.

Since the characteristics of ~1NO3 are either curve A or B in FIG. 13 above, reading the stored information of MNOS is done by detecting the conduction state between the source and drain when the gate voltage is vGfJ''-ov, for example. In order to be able to select one of a plurality of MNOS coupled to one digit line by a single polarity signal, a unit storage element (hereinafter referred to as a memory cell) is
As shown in the equivalent circuit of FIG. 14, it is composed of an MNO3QI and an insulated gate field effect transistor for switching (hereinafter referred to as MISFET for switching) Q2 connected in series with the MNO3QI. When reading, MNO8Q1
The gate voltage of is maintained at OV, and the switch M I S
(FET) 14 pressure is set to O by the selection signal.
It is assumed to be a positive voltage such as V or +5V.

FIG. 1 shows a circuit of a semiconductor memory circuit device according to an embodiment.

The memory circuit of this embodiment includes circuits that form relatively low voltage signals such as an X decoder, Y decoder, and control circuit, and circuits that form relatively high voltage signals such as a write circuit and an erase circuit. I'm here.

Although not particularly limited, a low power supply voltage of +5V is supplied to the power supply 1:5 CC for the circuit forming the above-mentioned low voltage signal. Depending on the power supply voltage, the high level of the low voltage signal is set to r+sv, and the low level of the low voltage signal is set to Ov, which is the ground potential of the g circuit.

A high voltage terminal VPP is provided in the circuit device for circuits such as the write circuit and erase circuit. This high voltage terminal V
A high voltage such as g+25V is supplied to PP when the circuit device performs a write operation and an erase operation. Depending on the above-mentioned high voltage, the high level of the high voltage Ig is set to y+25V or +20V, and the low level is set to rQ■.

In FIG. 1, MA is a memory array and includes memory cells MSII to MS22 arranged in a matrix.

The gates of the switch MISFETs Q2 of the memory cells MSII and MS12 arranged in the same row are commonly connected to the second word mW11,
The gates of QI are commonly connected to the second word line.

Similarly, other memory cells MS21 arranged in the same row
．． The gates of the switch MISFET and MNOS of MS22 are connected to the first word line W21. 2nd word scarlet W2
2 are commonly connected.

The drains of the switching MISFETs Q2 of the memory cells MSII and MS21 arranged in the same column are commonly connected to the digit line D1, and the sources of the MNOS are commonly connected to the reference potential i-line E D 1.

A memory cell MS12 arranged in another same column on the same line,
MS22 switch MISFET drain and MN
The OS source is 1 digit D2. Commonly connected to reference potential #ED2.

According to this embodiment, the memory information of the MNOS is erased by applying a positive high voltage to the base gate, so the semiconductor region forming the memory cell is used for the X decoder, Y decoder, etc. described below. It is electrically separated from the semiconductor region forming the peripheral circuit. As will be explained later, the above semiconductor region is composed of, for example, a p-type well region formed on the surface of an h-type semiconductor substrate.

For the above erasing, (IiJ memory cells can be formed in independent well regions, or memory cells arranged in the same row or column can be formed in a common well region. In the embodiment, the entirety of the memory cells, ie, the memory array MA, is formed in one common well region.

In FIG. 1, mwELL is connected to the well region as a common body gate of memory array MA.

The first word lines W 11 z W 21 are connected to the output terminals of the X decoders XDI and XD2, respectively, and
Word Ryo W12. W22 is the write circuit WAl, WA
It is connected to the second output terminal.

As shown in the figure, the X decoder It consists of enhancement type MISFETs Q4 to Q6 that receive non-inverted outputs or inverted outputs from address buffers BO to B6, and substantially constitutes a NOR circuit.

When not selected, the X decoder XDI outputs a low level signal of approximately OV to the word 11VW11 due to the high level of the signal on at least one of the address input lines aO to a6, and when selected, the X decoder XDI outputs a low level signal of approximately OV to the word 1lVW11. All signals at become low level, and outputs a high level signal of W5V.

The X-decoder XD2 has the same configuration as the X-decoder XD1 described above, except that the connected address input lines are different.

In FIG. 1, a depletion type MISFET such as MISFETQ3 is marked with a different symbol from an enhancement type MISFET as shown.

The write circuit WAI has M connected in series between the first word +JW11 and the output terminal (second word, WW12).
ISFETQI 5. MI 5FET QI connected between Ql 6 and the above output terminal and the power supply terminal VPP to which the above +25V voltage is applied during writing and erasing.
9, and an MI 5FETQI 7°Ql8 connected in series between the output terminal and the ground terminal. Above MI
Is the gate of 5FETQI 5 write control? tiAW
The gate of MISFETQI8 is connected to read and erase control line vp, and the gate of MISFETQI8 is connected to
The gates of 6 and Ql8 are connected to the power supply terminal vCC.

A control circuit CRL having a configuration to be described later causes the signal on the write control line Wl to be r
ov is set to low level, and the signal below the control line is r+s.
It is considered to be a high level of v. Therefore MI 5FETQ
I5 is in the off state, whereas MI5FETQ
I8 is in the on state. Output terminal (1st word + JW
12) MI 5FET QI7 and Ql8 connected in series
and connected to the ground terminal of the circuit via 1. For that, r
It is made into an ov.

In the write operation, a high voltage of +25V is applied to the power supply terminal VPP, and the MI5FE is applied to the write control line Wl.
A high level signal of y+5V is applied to turn on TQI 5, and MISFET QI8 is applied to the control line.
A signal at X:OV is applied to turn off.

On state of MISFETQI5 above and MISFETQ
Due to the off state of I8, the signal level of the second word wwx2 can be determined according to the signal level of the first word line Wll.

That is, if all of the drive MISFETs Q4 to Q6 of the X decoder XDI are turned off so as to select the first word line Wll, the MISFETs QI6. Q
The current paths of I5 and the driving MISFETs Q4 to Q6 are not configured.

Therefore, +25V of the g power supply terminal VPP appears on the second word line W12 via the MISFET QI9. That is, in response to the fact that W+5V is applied to the selected first word, a voltage of r+25V is applied to the selected word W.

If the first word line Wll is not selected, that is, if at least one of the driving MISFETs Q4 to Q6 of the X decoder XDI is turned on, the MISFET
QI6. Ql5 and above, driving M I S 1” E
'r A current path is formed to ground the output terminal (second word line W12) via Q4 to Q6. As a result, the output terminal is set to yov.

In the write circuit WAI, MISFETs QI6 and Ql7, which constantly receive the power supply voltage VCC at their gates, are as follows:
The high voltage signal applied to the second word line W12 is
Used to prevent being limited by breakdown of TQI 5 or Ql8.

That is, for example, if MISFETQI7 is omitted,
The second word line W is connected to the drain D of MI 5FETQI 8.
12 high voltages (+25V) will be applied. As mentioned above, the low voltage of yov is applied to the gate of MI 5FET QI 8 from the control line vp, so
The depletion layer that should spread to all sides of the drain junction of MISFET QI8 is limited by the low voltage of this gate in the vicinity of the gate. As a result, MISF
The drain junction of ETQ18 will break down at relatively low voltages.

If MISFET QI7 is provided as shown, MI 5
The voltage applied to the drain of FETQI 8 is the power supply voltage v
It is clamped to a voltage increased by the threshold 1 direct voltage of MISFET QI7 from CC.

As a result, breakdown of MISFETQI8 is prevented. MISFETQI7 has its gate connected to the power supply VC.
Since it is connected to C, it has a relatively high drain breakdown voltage.

MI 5FETQI 6 is also the above MI 5FETQI 7
used for the same reason.

According to this embodiment, the configuration using the well region as described above is effectively utilized.

The load MISFET Q19 in the necking circuit WAI is a MISFET such as other MISFETs QI5 to Q18.
It is formed in a well region independent from the well region forming the ET. That is, the base gate of MI 5FET QI 9 is electrically isolated from the base gates of other MISFETs.

As shown in the figure, the load MISFET Q19 has its base gate and source short-circuited to prevent high voltage from acting on the channel between the base gate and the source and drain.

Regarding the connection shown in the figure, if the body gate is connected to the ground terminal like other MISFETs, the voltage required at the output terminal (second word line W12) is large, so the MISFET Q19 due to the body bias effect Increase in threshold voltage of MISFET to handle other low voltages
significantly larger than that of As a result, the voltage supplied to the high voltage terminal VPP must be significantly larger than the voltage required at the output terminal (second word line W12).

In contrast, in the case of the illustrated connection, the voltage at the substrate gate is equal to the voltage at the source, so that the increase in the threshold voltage of MISFET QI 9 due to the substrate effect can be virtually ignored. , high voltage terminals V, P
The high voltage supplied to P can be made relatively small.

As described above, by adopting a configuration in which the voltage supplied to the high voltage terminal VPP can be reduced, this high voltage terminal V
It is no longer necessary to make the withstand voltages of various pn junctions to which PP is connected abnormally high, or various undesirable leakage currents in pn junctions can be reduced.

Furthermore, it is possible to prevent undesirable parasitic channels from being induced on the semiconductor surface by the electric field of the wiring connected to the high voltage terminal VPP.

Each reference potential HED1. of memory array MA. ED2 is connected to the write inhibit circuit IHAI.

In the write inhibit circuit IHAI, the reference potential @ED1
M15FETQ2 connected in series between
0 and Q21 constitute a unit switch circuit. The MI 5FETQ21 in this unit switch circuit receives a control signal from the control circuit CRL via the control i1r. The control signal is applied at +5V so as to turn on the MISFET Q21 during the read operation of stored information.
It is set to the level O, and is set to the level O2 so as to be in the off state during the input operation and the erase operation.

Therefore, the unit switch circuit sets the reference potential 5ED1 to yOV during the read operation.

M between the reference potential line EDI and the high voltage signal #IHV
ISFETQ22 is connected. The high voltage signal line IHV includes a write inhibit voltage generation circuit IHA, which will be described later.
2, +20 V during write and erase operations
A signal of yOv is applied during a read operation.

Therefore, in a write operation and an erase operation, when MI5FETQ21 of the unit switch circuit is turned off, a high voltage is applied to the reference potential line EDI from the high voltage signal line IHV via M15FETQ22.

MISFETQ is connected between the reference potential line FD2 and the ground terminal.
23 and Q24 similar to the above unit switch circuit are connected, and the reference potential is E D 2 and the high voltage signal a
I HV Between the trunk M I S F E TQ25
is connected.

In the above write inhibit circuit I I-I A I,
MISFET whose gate receives +5v power supply voltage VCC
Q20. Since the high voltage mentioned above is applied to the reference potential lines EDI and ED2, Q23 is connected to the write circuit W mentioned above.
MISFET Q16 provided in AI. It is used for the same reason as Q17.

MISFETQ22. Q25 is the MISFETQ1
9, in order to prevent an increase in the threshold voltage due to the substrate bias effect and to prevent the voltages of the reference potential lines EDI and ED2 from decreasing with respect to the high voltage of the high voltage signal 111HV, an independent well region is provided. It is formed.

A Y gate circuit YGo is connected between each digit line DI, D2 of memory array MA and common digit 1fSCD.

In the Y gate circuit YGO, the MI 5 connected in series between the digit line D1 and the common disk) [C'
FETQI 1 and Q12 constitute a unit gate circuit,
The above digit line DI corresponds to the output of the Y decoder MDI.
and the common digit ii+l1ICD. Similarly, MI 5FET QI 3 and Q14 constitute a unit gate circuit of the song, and this unit gate circuit is connected to the Y decoder YD.
The digit 11D2 and the common digit line are connected according to the output of the digit 11D2 and the common digit line.

During write operation and erase operation, each digit iD1.
Since a high voltage signal appears on D2, the above Y gate circuit Y
The unit switch circuit in GO consists of MISFETQ12. Q1
Use 4.

The Y decoders MDI, YD2 are the X decoders XDI,
It has a configuration similar to that of XD2, and has non-inverted signals a7 to alO and inverted signals a7 to a of address signals A7 to AIO output from address buffers B7 to BIO.
By selectively receiving lo, each output line Y
1, Y2 outputs a decoded word which becomes a high level of +5■ when selected and becomes OV when not selected.

A sense circuit IO8 and a data input circuit IOW are connected to the common digit cocoon CD connected to the Y gate circuit YGO.

~The sense circuit IO3 has a load MISFET Q47 whose gate and source are connected as shown in the figure, and a control a to a gate 1.
It consists of a switch MISFETQ48 that receives a signal from f. In the derivation operation, the signal at ht is +
The above switch M is set to a high level of 5V.
ISFETQ48 is turned on.

The output of the sense circuit IO8 is connected to the inverter 114.1.
15. NOR circuit NR3, NR4 and MISFETQ49
．． An output buffer circuit 10RK consisting of Q50 is supplied.

In the output buffer circuit IOR, NOR circuits NR3, N
One input terminal of each of R4 is connected to control #C81. The signal of the control NC 81 is set to a low level of 0■ during a read operation, and set to a high level of +5■ during a write and erase operation. The other input terminal of the NOR circuit NR3 is connected to the output terminal of the inverter IN14, and the other input terminal of NR4 is connected to the output terminal of the inverter IN1.
It is connected to the output terminal of the inverter INI 5 which receives the output of the inverter INI 4.

Therefore, the NOR circuits NR3 and NR4 output signals having opposite phases to each other during the read operation. M connected in series
ISFETs Q49 and Q50 are push-pull driven by the NOR circuits NR3 and NR4.

If the signal on the control line C81 is at a high level, the NOR circuit N
Both R3 and NR4 output low level signals of Ov, and both MISFETs Q49 and Q50 are turned off. The output terminal of the output buffer circuit IOR is connected to the input/output terminal PO. MISFETQ above
In the simultaneous off-state of Q49 and Q50, the output buffer circuit has a significantly high output impedance;
Therefore, the input signal applied to the input/output terminal PO is not limited.

In the above output buffer circuit IOR, the power supply terminal vCC
The above MISFETQ49 connected between
is formed in a well region independent from the well regions of other MISFETs. The well region as a substrate gate is connected to its source. As a result, an increase in the threshold voltage due to the body bias effect is substantially eliminated, so that the output buffer circuit IOR can output a high-level signal of the power supply voltage vCC.

The data input circuit IOW includes an input buffer circuit INI 6, an MI 5FETQ51 controlled by the output of this input buffer circuit, and a MI 5FE circuit as shown in the figure.
MI is connected between the drain of TQ51 and the common digit line CD, and receives a signal from the control line WJ at its gate.
It is composed of 5FETQ52.

The write inhibit voltage generation circuit IHA2 has an M voltage as shown in the figure.
It is composed of ISFETs Q26 to Q36. The above-mentioned MISFETs Q26 to Q28 constitute a first high voltage inverter, and by receiving a low voltage system control signal from the control line Wl, output terminals, that is, MISFETs
A high voltage signal is output to the drain of TQ27. With the connections shown, the output signal level is from XOV to VPP.
changes up to. MISFETQ29 to Q31 are the second
MI 5FETQ3 is configured as a high voltage inverter and receives the same signal as the first high voltage inverter.
A high voltage signal is output to the drain of 0. The output signal level varies from +5V (vCC) to VPP. MI 5FETs Q32 to Q36 constitute a high voltage push-pull circuit. Above 1st. MISFET Q28. which receives control signals in the second high voltage inverter and push-pull output circuit. Q31. MISFET Q27°Q30.Q36 is connected between Q36 and each output terminal, and receives a +5cm power supply voltage at its gate. Q35 is
Similar to the aforementioned MI 5FET QI 6°Q17, etc., it is used to ensure a high output voltage of the circuit. Load MISFET Q2 in the first and second high voltage inverters
6. As shown in the figure, Q29 is a MISFET Q in a push-pull output circuit whose body gate is connected to each source, so that there is no drop in output voltage due to the body bias effect.
33 and Q32. It is configured to be able to sufficiently drive Q34.

In the above push-pull output circuit, MISFETQ3
2 is used to limit the voltage applied to KMI 5FETQ3317))'L/in when the output of the first high voltage inverter is yOv.

That is, when the output of the first high voltage inverter is yOV, the reference potential of the second high voltage inverter is +
Since it is considered to be a low voltage of 5V, it outputs +5V. As a result, +5■ is applied to the gate of MISFgTQ32, and the drain voltage of MISFETQ33 is limited. MI 5FETQ34 is the first. After the output line IHV is set to a high voltage of +20V due to the output of the second high voltage inverter becoming a high voltage, the output of the second high voltage inverter becomes a low level of yov. , is used to limit the high voltage applied from the output AIIHV to the source of MISFETQ33. As a result, undesired breakdown of the source and drain junctions of MISFET Q33, which is operated as a switch, is prevented.

Erasing circuit ER3 includes MI 5FETQ40 to Q42.
A push-pull circuit includes MISFETs Q43 to Q46 and a bipolar transistor Q44. The high voltage inverter is connected to the write inhibit voltage generation circuit IH.
It has the same configuration as A2.

In the above push-pull output circuit, bipolar transistor Q44 and MI 5FET Q43 are connected in parallel,
It is driven by the output of the high voltage inverter. The well regions forming the memory array constitute a heavy capacitive load for the erase circuit, as will be apparent from the structure of the circuit arrangement described below. Therefore, the erase circuit ER8 is required to have sufficiently low output impedance characteristics in order to perform a high-speed erase operation. In a semiconductor integrated circuit device, a bipolar transistor exhibits sufficiently lower operating resistance characteristics than a MISFET even if it is formed with a relatively small size (area). Therefore, as shown in the figure, the erase circuit ER8 having the bipolar transistor Q44 as an output transistor drives the well region of the memory array MA at a sufficiently high speed even if it is formed in a small area to be mounted on a semiconductor integrated circuit. Structure of a bipolar transistor formed on the same semiconductor substrate as the above MISFET, I! The law will be explained later.

In the erase circuit ER3, when only the bipolar transistor Q44 is protected, the threshold voltage (base-emitter voltage) of this bipolar transistor is, for example, 0.6V, so the MISFETs Q40 to Q44
Even if the high voltage inverter consisting of the above outputs a signal of the power supply voltage PP, the voltage signal output to the output line I is lowered by the threshold voltage of the transistor Q44.

In the illustrated erase circuit ER3, the base gate is integrated with the base gate of the load MISFET Q40 of the high voltage inverter, and the gate is integrated with the base gate of the load MISFET Q40 of the high voltage inverter.
Depletion type MI 5FET connected to the source of FETQ40, that is, the output terminal of the high voltage inverter
Q43 is connected in parallel with the bipolar transistor Q44. In the MI 5FET Q43, the high potential of the substrate gate rises to the y power supply voltage vPP, so there is virtually no increase in threshold voltage due to the substrate bias effect. Therefore, the high voltage at the output ff1AIIc is
Depending on I5FETQ43, the y power supply voltage can be raised to VPP.

The body gate of the MI 5FET Q43 may be connected to its source, ie the output iN 13, from the connections shown. Even in this case, it is possible to prevent the output level of output 1 from decreasing due to the substrate bias effect. However, in this case, due to the structure of the circuit device, the well region serving as the base gate of MISFET Q40 and the well region serving as the base gate of MISFET Q43 cannot be shared, and must be separated from each other.

The requirement for a certain spacing of the well regions from each other has the disadvantage of increasing the required area of the semiconductor substrate.

The control circuit CRL includes inverters INI to lNl2,
NAND circuit NAI to NA4, NOR circuit NRI, NR
2 and series connection) MISFET Q37 to Q39. This control circuit CRL has an external terminal P
By receiving a write control signal, a chip selection signal, a write and erase signal to GM, C8 and VPP, respectively, and receiving an output signal from the write inhibit voltage generation circuit IHA2, lines C81, F, WA', Wl and vpK are connected.
Outputs a control signal.

The signal supplied to the terminal VPP is the write circuit W.
AI, WA2, write inhibit voltage generation circuit I HA 2
This is a high voltage signal of 25 V which is shared as the power supply voltage for the erase circuit ER3.

The control circuit CRL controls the MISFETs Q37 to Q as described above so that the filling or erasing operation is controlled f1 only when the signal at the terminal VPP reaches a predetermined level or higher.
It includes a level shift circuit consisting of 39 circuits.

The operation of the semiconductor memory circuit shown in FIG. 1 is shown in FIGS. 2 to 4.
This will be explained as follows using the timing chart shown in the figure. Note that FIG. 2 shows a timing chart of a read operation, and FIG. 3 shows a timing chart of an erase operation. Further, FIG. 4 shows a timing chart of a write operation.

In the read operation, the write control signal at the terminal PGM is at a low level of yov. In addition, the terminal VPP is set to yoV or floated, and the gate is set to +5 V (7) i voltage V CC
The drain of MISFETQ39 receiving
A write and erase control signal of V is present.

The signals on the control lines t', Wl, and vp are at high level due to the low-level write-in control signal at the terminal VPP and the low-level write-in and erase signal at the drain of MI 5FETQ39, and the signals on the control lines t', Wl, and vp are at high level.
The signal at is at low level.

Therefore, each reference potential line ED1 . ED
2 is set to yO■ by the write inhibit circuit IHAI, and each second word JW12°W22 is similarly set to KOV by the write circuits WAI and WA2.

Although the timing is not particularly limited, for example, at time to, a signal at the address input terminal AO (・LAIO) is set corresponding to the selected memory cell. For example, if the selected memory cell is "-MS11", the address (The output of the X decoder XDI becomes high level due to the output of B6, and the output of the Y decoder MDI becomes high level due to the output of address decoders B7 to BIO.

As a result, MISFETQ is connected between the drain of MNO3QI of memory cell MSII and common digit i#cD.
1. QIO, Digit Katsu D1 and MI for switch
A current path is formed through the 5FETQ2. Also,
By the level of the signal on the control line r, the common digit MCD and the load MI5FE of the sense circuit IO3
A current path is formed between TQ47.

If MNO3QI of memory cell MSII is in the on state as shown in the characteristic of FIG. 13A, sense circuit IO8
The output line of is grounded via the current path and MNO3QI. As a result, the output line of the sense circuit IO3 becomes low level.

If MNO3QI of the memory cell MS11 is in the off state as shown in the characteristic shown in FIG. 13B, then the load MI5
A current path to FETQ47 is not formed, and as a result, the output line of sense circuit IO8 becomes high level.

At time t1, the chip selection signal at terminal C8 is changed from high level to low level, so that g
At the same time t2, the signal on the control line C81 becomes low level. As a result, the output buffer circuit IOR comes to output a signal corresponding to the output level of the sense circuit IO3 from the high output impedance state. For example, the sense circuit IOR outputs a NO level signal to its output terminal.

When the chip selection signal returns from low level to high level at time t3, the control line C3 changes at the same time t4.
The signal I changes from low level to low level, and in response, the output buffer circuit 1OR again enters a high output impedance state.

For the erase operation, a +25V write and erase signal is applied to the terminal VPP in advance, and a low-level chip selection signal of 0■ is applied to the terminal C8.

The signal on the control line is at the no-y level due to the chip selection signal at the above level, so the write circuits WAI and WA2 are connected to the second word line W12. W22 is...
I am using ROV.

As shown in FIG. 3, when the write control signal is set to the no-y level at time 110, the NAND circuit N
The output of A4 becomes low level. The above NAND circuit NA4
The erase circuit ER8 is activated by the low level signal of the MI
Since the SFETs Q42 and Q46 are in the off state, +250 high voltage and voltage are output to the output tti.

Second word #Wx 2. as described above. Since the signal at W22 is set to OV, when the well region WELL is brought to a high voltage of +25V by the output of the erase circuit ER8, a high voltage for erasing is applied to the gate insulating film of the MNOS of the memory array. .

The positive voltage in the well region is the MNO3QI of the memory cell.
and forward biasing the source and drain junctions of the switch MI 5FETQ2. Therefore, the reference potential lines EDI, ED2, D2) iDI, D2
If a current path is formed between at least one of the well regions and the ground terminal of the circuit, the voltage to be applied to the well region will be reduced.

The illustrated circuit operates as follows to prevent the voltage drop in the well region described above.

The signal at the control signal t becomes low level in response to the write control signal becoming irregular at the same time tll as the time tlo.

Write inhibit circuit I by the signal on the control line r
HAI's MISFET Q2, 1. Q24 and MISFET Q36 of the write inhibit voltage generation circuit IHA2 are turned off. As a result, each reference potential line E of the memory array
DI and ED2 are substantially floated.

The signal on the control line Wl is at a low level in accordance with the low level of the chip selection signal. Therefore, M in the data input circuit IOW connected to the common digit line CD
I5FET Q52 is in the off state. On the other hand, MISFETQ48 in the sense circuit IO8 connected to the common digit line CD is turned off by the signal on the control line r.

Floating the common digit line CD causes each digit line D I , D 2 of the memory array MA to float regardless of the operation of the Y gate YGO.

At time tll, when the signal at the terminal PGM returns to the low level, the output of the erase circuit ERS also returns to the low level accordingly.

As described above, the erase operation is performed in the chip selected state, whereas the write operation is performed in the chip non-selected state, that is, when the signal at terminal C8 is at a low level. For a write operation, a +25V write and erase signal is applied to the terminal VPP in advance.

At time t20, address signal a is set to select, for example, memory cell MSII.

That is, the first word line Wl is
l is set to high level, and the line Y is set to high level by the Y decoder MDI.
1 is considered a high level.

At time t21, information to be written is added to terminal PO. If the information to be written is 0, the terminal PO is Ov.
and accordingly the data input screen MIOW MI 5
FE=TQ51 is +5 from input buffer circuit lN16
②Receives the no-repel signal and turns on. If the information to be written is 1, for example +5V, the above MISF
ETQ51 outputs 0 from the input buffer circuit IN16.
■The switch turns off.

When the write control signal on the terminal PGM becomes high level at time t22, the signal on the control line Y becomes low level at time t23 after a slight delay time caused by inverters INI, IN2 and NOR circuit NR2 in control circuit CRL. As a result, the write inhibit circuit IHA
MISFETQ21. Q24, write inhibit voltage generation circuit ■MISFETQ36 of HA2 and sense circuit■
MISFETQ48 of O8 is turned off.

At time t24 after a slight delay from time t23, the control iWe signal becomes low level. The write inhibit voltage generation circuit IH is activated by the signal on the control line We.
A2 now outputs a high voltage of y+20■ to the line IHV, and accordingly, each reference potential line E of the memory array
D1. ED2 becomes the above +20V.

At the same time as the time t24, the signal on the control line We becomes high level. In response, MISFETQ52 of the data input circuit 20W is turned on. At the same time, MISF of write circuits WAI and WA2
ETQ15 is turned on.

Output of the above write inhibit voltage generation circuit IHA 2 @
When the IHV signal becomes high enough, this line IHV
The control circuit CRL receiving the signal outputs a low level signal to the control line vP at time t25. The signal on the control line vP mentioned above is used as a write start signal, as will be explained next. As described above, by configuring the write start signal to be output after the signal on the line IHV reaches a sufficient write inhibit level, it is possible to prevent information from being accidentally written to unselected memory cells. can.

As described above, when the signal on the control line vP becomes low level, the write circuit WAI.

MISFET Q18 of WA2 is turned off.

Since the first word line W11 is selected and set to +5V, the inset circuit WAI outputs a high voltage of M+25V to the second word 1QW12.

The write circuit WA2 outputs approximately Ov to the second word line W22 in response to this, since the first word line W21 is not selected and is set to approximately 0.

MNO8QI in memory cell MSII to be selected includes switch MI 5FETQ2, digit line D1,
MISFETQ5 which receives the output of input buffer circuit INI6 via MISFETQ12, Qll of Y gate YGO, common digit machine CD and MISFETQ52.
1. If the information to be written is 1, due to the ON state of MISFET Q51, the drain and source of MNO3QI in memory cell MS11 become almost OV, and its gate (second word line W
Electrons are injected into the gate insulating film by the high voltage of 22). If the information to be written is O, the above MISF
Due to the OFF state of ETQ51, the memory cell MS11
The source and drain of MNO8QI are set to +20V of the overflow inhibiting voltage generation circuits IH and A2.

Therefore, the electrons mentioned above are not injected. Memory cells MS21 in other rows coupled to the same disk ID1 include:
Since the signal on the second word line W22 is set to approximately OV as described above, no information is written.

Other dates! Since MI 5FETQI 3 in the corresponding Y gate YGO is in the off state, D2 is
+2 by the output of write inhibit voltage generation circuit IHA2
It is maintained at 0V.

When the write control signal at terminal PGM becomes low level at time t26, as shown in FIG. 3, at time t27. t28. At t29, the control lines vP, w
The signals at e and r become high level. Correspondingly, the signals of the second word tijw 12 and the reference potential line ED1 also become approximately O.

The semiconductor memory circuit of the present invention can have a relatively large capacity, for example 16 bits.

FIG. 5 shows a block diagram of a semiconductor memory circuit using the circuit of FIG. 1.

In FIG. 5, memory array MA includes, for example, 16384 memory cells arranged in 128 rows×128 columns. For the memory array MA, 128 memory cell rows are selected by receiving a 7-bit address input signal from address buffers BO to B6.
A decoder XD is provided. In addition, 16 of the memory cell column
Eight Y gates YGO to YO2 are provided to select one address at a time, and these Y gates are connected to address buffer B7.
It is controlled by a Y decoder YD which receives a 4-bit address input signal from the BIO. Above Y goo)Y
Input/output circuits 0 to 7 including a sense circuit, output cover 7 circuits, and data input circuit as shown in FIG. 1 are provided corresponding to GO to YO2, respectively. MI5 as shown in FIG. 1 corresponds to each memory cell column.
A write inhibit circuit IHA including FETs Q20 to Q22 and one write inhibit voltage generating circuit is provided, and a write circuit WA is provided corresponding to the memory cell row. Furthermore, a control circuit CRL and an erase circuit ER8 are provided.

Therefore, the semiconductor memory circuit shown in FIG. 5 stores 8 bits of information in 11 bits, that is, 2048 addresses.

As mentioned above, the memory cells are connected to MNOS and switch MI.
The configuration of the X decoder can be simplified by constructing the X decoder and the write circuit as mutually independent circuits. Therefore, X
It becomes easy to speed up the selection of the word green by the decoder, and it becomes possible to provide a memory circuit that operates at high speed.

MI 5FET Q22゜Q2 in write-protection circuit
The sources of 5 are connected to the reference potential lines EDI and ED as shown in FIG.
For example, instead of being connected to digit lines D1 and D2, it may be connected to digit lines D1 and D2. Even in the above case, it is possible to supply the write inhibit voltage to the memory array.

However, if we do the above, each digit line D
I, D2 are the above MISFETQ22. The junction capacitance of Q25, the stray capacitance of the mounting structure, etc. are combined, and as a result, when reading and writing stored information, the speed of signal change of each digit scissor is limited, so care must be taken. As shown in Figure 1, MISFETQ22. When connecting Q25 to the reference potential lines EDI and ED2, digit 1'91
The speed of signal change can be increased.

Each of the above circuits is created using semiconductor integrated circuit technology.
Formed on one semiconductor substrate.

According to the present invention, each of the circuits described above is formed on a semiconductor substrate in an arrangement that does not limit the circuit characteristics and does not increase the size of the semiconductor substrate used.

FIG. 6 shows patterns of regions for each circuit and wiring formed on the silicon substrate 1.
An X decoder XD is arranged at the center of the surface of the substrate 1. The memory array is divided into two parts: MAl and MAl.
On the one hand, MAI is placed on the left side of the X decoder XD, and on the other hand, MA2 is placed on the right side.

A write circuit WAa is arranged on the left side across the memory array MAL, and a storage circuit WA6 is similarly arranged on the right side across the meso array MA2.

A Y gate YGa is arranged above the memory array MAI, and similarly a Y gate YG is arranged above the memory array MA2.
b is placed. A Y decoder YD is arranged between YGa and YGb, that is, above the X decoder XD.

The above memory array, X decoder, 9! input circuit.

The area around the Y gate and the X decoder is a wiring region WIR as indicated by dots.

The above memory arrays MAl, M are located across the wiring region WIR.
A write inhibit circuit IHAa is provided below each of A2.
, IHAb are located.

Around the surface of the board 10, there are an input/output circuit IO and a control circuit C.
RLI and CRL 2. Input buffer circuit AI or A
12 are arranged. Further, around the above-mentioned area, bonding terminals (P1 to P26) for connecting various input terminals and output terminals to terminals outside the circuit device are arranged.

In order to configure the circuit shown in FIG.
L and MAl each have a size of 128 lines x 64 lines. Corresponding first word lines of memory arrays MAI and MAl are simultaneously busy selected by X decoder XD. The input line of the X-decoder XD is connected to an input buffer circuit arranged around the substrate 1 via wiring in the wiring region WIR.

Y gates YGa and YGb are simultaneously connected to corresponding memory arrays MAL and M by the output of Y decoder YD.
The A2 digit line is selected. The Y gates YGa and YGb are connected to the input/output circuit IO via wiring in the wiring region WIR.

The write inhibit circuits IHAa and IHAb are connected to the corresponding memory array MA via wiring in the wiring area WIR.
It is connected to the reference potential line of L and MA-2.

As mentioned above, embodiments of the invention use well regions for the memory array and its peripheral circuitry.

FIG. 7 shows a pattern of well regions formed on the surface of the silicon substrate 1, corresponding to the circuit arrangement shown in FIG. FIG. 8 shows a sectional view taken along the line AA in FIG. 7.

In FIGS. 7 and 8, independent P-type well regions 10a and 10b are formed on the surface of an n-type silicon substrate 1 to form a memory array.

Around the well regions 10a and 10b, there are an X decoder, a Y decoder, and a Y gate separated therefrom.

Write circuit, write protect circuit, input/output circuit.

A P-type well region 11 is formed for forming peripheral circuits such as an input buffer circuit and a control circuit.

In the upper part of FIG. 7, it is shown in a large size due to space limitations, but the output buffer circuit ■OH in FIG.
In order to form a MISFET that connects the source and the base gate like I5FETQ49, a P-type well region 11a that is separated from the above-mentioned P-type well region 11 and is independent is provided.
to llb are formed.

Similarly, on the left side of the P-type well region 10a and on the right side of 1ob, independent P-type well regions 11c to lid and lie to llf are provided to form MISFETs such as Q19 in the write circuit WAI in FIG. is formed. Furthermore, below the paper surface of FIG. 7, other P-types are formed to form MISFETs that require similar independent base gates, such as the write inhibit circuit IHAI and the write inhibit voltage generation circuit IHA2 in FIG. P-type well regions 11g to llh and lli to 11j are formed independent of the type well region.

Although not shown in FIGS. 7 and 8, the n-type silicon substrate 1 is exposed at a predetermined portion within the P-type well region 11 in order to form a MISFET to be described later.

According to this embodiment, as described above, the n-type silicon substrate 1
Since the configuration is such that various P-type well regions are formed on the top,
Various effective transistors and other elements for semiconductor memory circuit devices can be formed.

For example, as will be described later, a channel stopper for preventing parasitic channels is formed on the surface of the n-type silicon substrate 10 between a plurality of P-type well regions by ion implantation of impurities, and this channel stopper is effective. used for.

That is, for example, FIG. 9 shows an MI that can obtain high breakdown voltage characteristics.
A cross-sectional view of the SFET is shown. In the same figure, l1m
is a P-type well region, 21 is an n-type channel stopper formed on the surface of the substrate 10 so as to span a part of the well region 11m, 95.96 is an n-type source region,
drain area.

63 is a gate insulating film made of silicon oxide; 60 is a gate insulating film made of silicon oxide;
A thick silicon oxide film 84 covers the surface of the substrate 1 and the well region other than the region where elements such as MISFET are formed.
The gate electrode 120 is made of type polycrystalline silicon, and the insulating films 121 and 12 are made of phosphosilicate glass, for example.
Reference numerals 2 denote a drain electrode and a source electrode respectively made of, for example, vapor-deposited aluminum.

In the margin of FIG. 9 below, the substantial drain region of the MISFET is constituted by a region 9S for contacting the electrode 121 and the channel stopper 21. The channel stopper 21 is for preventing a parasitic channel from being induced on the surface of the n-type substrate 10, and has a relatively low impurity concentration. Therefore, the portion of the channel stopper 21 extending above the P-type well region 11m has a sufficiently higher resistivity than the region 95 for contacting the electrode 121. The MISFET shown in FIG. 9 has a channel stopper as a part of the drain region as described above, and thus has a large drain breakdown voltage.

Therefore, in the embodiment, the n-type substrate 1 is connected to the high voltage terminal V
PP (see Figure 1) and this high voltage terminal VPP.
The MISFET has the structure shown in FIG. 9, in which the drain is connected to the MISFET.

In other words, the write inhibit voltage generation circuit HA2 in FIG.
depletion type MISFET Q26, Q2 in
9, Q32, write circuit WAI, depletion type MISFET Q19 in WA2, erase circuit EI't
Depression type MI 5FETQ40 in S.
Q43 and the enhancement type MISFET Q37 in the level shift circuit or voltage dividing circuit (Q37 to Q39) in the control circuit CRL are connected to the MISFET Q37 with the structure shown in FIG.
It is assumed to be SFET.

Note that, in the depletion type MISFET, as will become clearer from later description, the P
It is formed by ion-implanting a P-type impurity, such as boron, into the surface of the type well region 11m.

FIG. 10 shows a cross-sectional view of an npn transistor. In the figure, the n-type substrate 1 is used as the collector region of the transistor, the P-type well region 11n is used as the base region, and the n+-type region 97 is used as the emitter region. The r1+ type deposit 97 is formed at the same time as the source region and drain region of the MISFET. The above npn transistor is used in the erase circuit ER3 of FIG.

The above-mentioned MNOS and various MISFETs may have a structure having an aluminum gate, but it is preferable to have a structure having a silicon gate as described above.

Therefore, when explaining in detail the structure of the elements and wiring constituting each of the above circuits using silicon gate technology below, the manufacturing method will first be explained for easier understanding.

Hereinafter, a manufacturing process for forming an MNO8 element, an enhancement type MO3 element, a depletion type MO8 element, and a bipolar transistor on two semiconductor substrates will be described in detail based on FIGS.

■ As a substrate sea urchin, it has a (100) crystal plane.
type single crystal, resistivity 8~12Ωcrn (impurity concentration approx. 5
A silicon (Si) wafer of X 10 "crn-") is used. In order to form wells with low impurity concentration with good reproducibility, it is preferable that the resistivity of this urethane is as large as possible (low impurity concentration).
In the example of the abfe Read 0nly Memory (electrically rewritable read-only memory), the impurity concentration of the well was set to about 3×1015 crn-3.
) using a wafer.

As shown in Figure 11, the surface of the silicon wafer 1 is cleaned with an appropriate cleaning solution (0, -H, 804 solution or HF solution), and then a silicon oxide film (SiO,) of about 50 nm thick is formed by thermal oxidation. 2 and continue CVD (C
Chemical Vapor Deposition：
(Chemical vapor deposition) voltage, silicon nitride (313N)
4) Form the film 3 to a thickness of approximately 100-14 pnm. This Si, N4 film formation method was compared using an atmospheric pressure vertical C-D storage device, an atmospheric horizontal CVD device, a low pressure horizontal CVD device, etc., but no significant difference was found. However, low pressure CV
The film thickness made using the D device has the best uniformity, and is within ±3% within the wafer, which is convenient for microfabrication. Although there are some differences depending on the method, the appropriate deposition temperature is in the range of 700 to 1000°C.

This result is also the same for Si3N film formation used below.

(2) Next, a photoresist film 4 is formed on this silicon nitride film 3 by photoetching only in areas other than the areas where wells are to be formed (between the wells). In other words, the Si3N+ film is exposed on the surface of the region where the well is to be formed. In this state, the exposed portions of the Si, N, and films are removed by plasma etching, and Si, N, and films are removed from the exposed portions of the film as shown in FIG. 11 [F].
2 film 2 is exposed. After that, using the resist film 4 as a mask, boron (
B) Ions are implanted with an energy of 75 KeV and a -taldose of 3×10”α2 to form P-type semiconductor regions 5 and 6.

(Q) After this, after removing the resist film 4, well diffusion is performed in dry oxygen (0□).

Since poron becomes an acceptor type impurity in Si, a P-type well is formed. As a result of diffusion at 1200° C. for 16 hours, the formed P-type well (1o, 11) has a surface concentration of 3×10″cm′ and a diffusion depth of about 6″μm.

However, this value is a value obtained from the results of measuring the surface sheet resistance using the four-probe method and the diffusion depth using the stain etching method, assuming that the impurity distribution in the well is a Gaussian distribution. It is. The reason why well diffusion is performed in oxygen is to form a uniform well at a low concentration.

At the time when the well diffusion is completed, as shown in FIG.
An oxide film of about 10 μm is formed on the surface of the N film 3. Therefore, by performing Sio2 etching on the entire surface, approximately 50n
By removing the SiO* film of m, a thick silicon oxide film 12.13 of approximately 0.8 μm remains on the well surface, and the surface of the 5jsNa film 3 is exposed between the wells.

The approximately 50 nm SiO□ film (Fig. 11 Ω14,
15.16) is exposed. In this state, a SiO2 film of about 0.8 μm thick is formed on the wells and about 50 nm thick between the wells. In this state, phosphorus (P) ions were implanted into the entire surface at an energy of 125 KeV and a dose of I
In this case, the thick SiO film 12.13 on the well serves as a mask, and phosphorus ions are not implanted into the well except for the periphery of the well region. Phosphorus ions are implanted into the wells to form N-type semiconductor regions 20, 21, and 22. Note that Si3N was used as a mask during the well diffusion.

The well expands laterally from the edge of the film during diffusion, and a difference of about 6 μm exists between the edge of the Si3N4 film (that is, the edge of the thick 5102 film above the well) and the edge of the well. In other words, the phosphorus ion implantation layer is formed approximately 6 μm from the end of the well into the well. Further, this phosphorus ion implantation layer has a depth of approximately 1 μm when measured after passing through the final thermal process.

By implanting phosphorus ions between the wells in a self-aligned manner as shown in FIG.
, 22 as S A P (SelrAl i-gned
P chaunel field ion 1nspl
layer.

As mentioned above, the p-type cell expansion region is formed by heat treatment in an oxidizing atmosphere using the Si3N4 film as a mask,
By using a thick oxide film formed on the well surface as a mask, N-type impurities are implanted into the surface of the N-type substrate between the wells across each well to form a SAP layer for preventing channel generation between the wells. Ion implantation between wells can be performed without increasing the number of masks, and the well diffusion region and the ion implantation layer between wells can be formed in a self-aligned manner. This technique will hereinafter be referred to as the SAP method.

After this, a 5iO2 film (1
2, 13 and 14, 15, 16).

In this state, a p-type well region (10
, 11) and n-type (having an impurity concentration higher than the substrate n-type impurity concentration) regions (20, 21, 22) are formed, and furthermore, at the boundary between the two, there is a thickness of approximately 0.4 to 0.5μ.
m unevenness 17 (steps) are formed. Using this step, mask alignment for the next photoetching process can be performed.

Next, the so-called LOG OS (Local 0
A process called oxidation is carried out.

■ First, as mentioned above, after removing all the SiO□ film on the Si surface, approximately 50 nm of SiO film is applied to the entire surface of the substrate.
It is formed by a 24-layer method on two films 24. Continued CVD
A 100-140 nm Si, N, and N film is formed on this Sio2 film by a method.

Next, by photoetching, a photoresist film is left only in predetermined areas such as areas where active elements will be formed (35.36, 37°, 38.39. in FIG. 11(g)).
40). In other words, in this state, the photoresist film is removed from the surface of the portion where it is necessary to form a thick oxide film for isolation between elements, etc., and the Si3N4 film is exposed by π.

In this state, plasma etching is performed to remove the exposed Si and N4 films, and remove the approximately 50 nm film previously formed on the surface.
5in2 membrane (24) was exposed. After that, using the resist film as a mask, boron (B) ions are injected into the 81 substrate in the area where there is no resist film through the SIO2 film (24) exposed on the surface at an energy of 75 keys.
- Implant with Taldose i 2 si, N in the layer
Design the photomask so that the edge of the 4th film is placed.
1) An active region is formed spanning the well. Note that this boron ion implantation is hereinafter referred to as field implantation (F implantation).

[F] After removing the resist film, field oxidation is performed in wet oxygen (0□). By performing this oxidation treatment at 1000°C for about 4 hours, the Si3N, film A 5i02 film (60) with a thickness of approximately 0.95 μm is formed on the surface of the Si substrate where the oxide film is removed.In this state, a thick field oxide film (60) with a thickness of approximately 0.95 μm is formed between the wells. , for example, the 11th
On the Si surface in Figure [F] 20, phosphorus from SAP and boron from F implant coexist, and the dose amount is I x 10 l3cm-2 for phosphorus and 2 for boron.
Although a larger amount of boron is implanted at X 1013 cm-2, the amount of boron that segregates into SiO during field oxidation is greater.In other words, boron in Si is However, as phosphorus in Si piles up (accumulates) at the interface with Si (see Figures 28 and 29), the surface between the wells eventually has a high concentration of phosphorus and plays a sufficient role as a channel stopper. In this way, by sharing the SAP method and the LOCOS process and making good use of the difference in behavior between phosphorus and boron at the 5i02 interface as described above, it is possible to implant phosphorus at as low a concentration as possible without using a masking process. "t" is a matter necessary for use as the drain of a high-voltage depletion MO3 FET DMO3, which will be described later), and boron implantation that requires a higher dose (to keep the threshold voltage of the parasitic MO3 (field MO3) high to a certain extent). It becomes possible to develop a process technology that allows the coexistence of phosphorus (necessary items for

Thus, the p-type ion implantation layers 41 to 4 in FIG.
6, p-type semiconductor regions 51 to 56 are formed under a thick oxide film on the surface of the substrate.

Now, immediately after this field oxidation is performed, as shown in Figure 11, there are about 50
nrM Sio, approximately 100-140 nm on film 24
of Si3N, film (25-30), and about 2
An oxide film with a thickness of 0 nm is formed, and a 5i02 film (60) with a thickness of about 0.95 μm is formed in the field region.

(Q In this state, when the entire surface is etched with S r 02 to remove the approximately 50 nm 5in2 film, the approximately 0.9 μm 5in2 film 60 remains in the field region, and the 50 nm 5in2 film 24 and 10
Si, N, and films 25 to 30 with a thickness of 0 to 140 nm remain, and this Si, N4 film is exposed. Subsequently, the SI3N4 films 25 to 30 are coated with hot phosphoric acid (H3
Remove using PO4) solution or the like.

In this way, the previously formed Sin film 24 of about 50 nm remains in the active region, and this 5i
It is also possible to use the N2 film 24 as an active MISFET gate oxide film, but because of the abnormal region (generally thought to be Si, N, film) that occurs at the Locos edge, the gate Since defects in breakdown voltage and the like are likely to occur, as shown in FIG.
As shown in FIG. 11, a 5102 film (62 to 67) having a thickness of approximately 75 nm, which is actually used as a gate insulating film, is formed at 1000 DEG C. for 110 minutes in, for example, dry 02.

0 Furthermore, among the MOS) transistors, EMOS (
Enhaucement mode MOS: L,
In order to set the threshold voltage (which has a high threshold voltage and the current is practically 0 at the gate voltage Ov), boron ions are implanted into the entire surface through the thin gate insulating films 62 to 67 at an energy of 40 I (eV, total dose of 2 x 10 ”7
Insert at cm2 (Fig. 11()]) 71-76).

Naturally, this boron is not implanted into the field region which has a thick oxide film, and the Si under the active region where about 75 nm of 5iOz film is present.
A SiO2 film is implanted into the substrate surface.

(I) Next, since the EAROM described in this example uses an E/D inverter as a peripheral circuit to increase the speed,
In addition to EMO8 mentioned above, DMO8 (De-pleti
It is necessary to form an on mode MOS (one in which the L threshold voltage is low and a current flows at a gate voltage of 0). In order to form this DMO8 in a predetermined part, S i0
After depositing a photoresist film on the two films 60, 62 to 67, the photoresist film on the area where DMO3 needs to be formed is removed by a photoetching process as shown in FIG. 11(I), and the other areas are removed. The photoresist film 80 is left and, using this as a mask, phosphorus ions are implanted only in predetermined portions (81), and the threshold voltage of the DMO 8 is set. Here, for example, energy 100I (
eV.

It was implanted at a dose of 1:2×1012/α2. this is,
The same applies to the area of high voltage DMO3 (Fig. 11 α) 81
). In this way, the well-to-well self-aligned isolation method (SAP
) By forming a depletion MO8FET on the boundary surface around the well made by the method, the nonvolatile memory element MNO3 and the high voltage DMO8 can coexist on the same chip without increasing the number of photomasks, as can be seen from the following explanation. becomes possible.

(J) Next, after removing the photoresist film 80, polycrystalline silicon (
A polySi ) layer of about 0.35 μm is formed at about 580°C. Regarding the polysi formation method, a normal pressure method and a low pressure method were also compared, and apart from the fact that the latter method was superior in film thickness uniformity, there were no particularly large differences in characteristics. Subsequently, polySi was doped with phosphorus by a diffusion method. In this case, the condition is, for example, 1000
℃ for 20 minutes, P from a POC1 source was deposited and diffused onto the polySi surface, and further stretched for 5 minutes to bring the resistance of the polySi to about 15 Ω/hole.

After that, after removing the phosphorus glass formed on the polysi surface by etching it with a solution containing HF, etc.
By photo-etching, the photoresist is left only in a predetermined area, and by plasma etching, polySt is removed from the area other than the remaining photoresist.
iO, the gate electrode is formed by the first layer polySi on the film,
and wiring was formed (Figure 11 (J) 8:3,84)
.

Next, using the first polySi layer (83, 84) as a mask, the gate oxide film 62 is selectively etched to partially expose the substrate surface as shown in FIG.

■ After this, oxidation is performed at 850°C for 20 minutes in a wet atmosphere, and approximately 40 nm of S is added to the exposed Si substrate surface.
An S io2 film (87 in FIG. 11) with a thickness of about 200 nm (85, 86) is formed on the polySi surface. After this, the entire surface was etched with 5iOz film to remove about 60 nm of the SiO2 film.
About 140 nm of Sio2 is left on the ly Si. In this way, in order to form a thick oxide film on poly-Si and a sufficiently thin oxide film on the surface of the Si substrate, at least 10" cm of phosphorus is added to the poly-Si.
It is important to contain at least -3 and perform the oxidation in a wet atmosphere at a temperature in the range of 600 to 1000°C.

(G) Next, the Sin□ film 8 left on the polySi
5°86 as a mask (that is, 5in2 in this case
(This prevents the etching of the first layer of poly Si, which has been doped with a high concentration of NH), and the exposed Si substrate surface is
After etching with an etching solution containing 3H2O2 and HCL H202, a thin oxide film of about 2 nm (
11th Zuton 88) in N2 Nozomi Translation 02 at 850℃, 120
Formed by oxidation of 1. Subsequently, by CVD method,
A Si3N film (90) of about 50 nm is formed. Here, we compared the formation methods of the formed Si and N4 films using the various methods mentioned earlier, but in the end, the high temperature H2 annealing described later resulted in no problem in the properties in either case. I was able to get

After this, polySi is deposited on this Si3N4 film 90.
After depositing a layer (second layer) of about 0.3 μm, it is processed by photoetching to form a layer (second layer) of polySi.
A gate (Fig. 11, ■91) is formed. Subsequently,
Using the second layer polysi (91) as a mask, 1×1
Phosphorus ions are implanted into the silicon substrate at 0 ”cm-2, 90KeV to form N-type semiconductor regions such as sources and drains (
92-100) and at the same time form a second layer of polysilicon.
91 was also doped with phosphorus. At this time, the first layer of po
Since lysi (83, 84) is already doped with phosphorus and the crystal grains have increased, there is a risk that phosphorus will be implanted into the Si substrate surface under the first layer polysi by implanting phosphorus ions. As you did, the first layer pol
On ysi, there is a S h 02P film 85. of about 140 nm.
86 and 50. nm 5i3N.

Due to the formation of membrane 90, this risk is eliminated.

M Next, using the Si3N4 film (90) formed under the second layer poly Si 91 as a mask, the second layer poly
After selectively oxidizing lySi (91,84) in a wet atmosphere at 850°C for 10 minutes, this oxide film (10
Using 2) as a mask, the film, Si, and N4 films are selectively removed. In other words, the highly doped second polysilicon layer is protected from the Si and N4 etching solution by the upper oxide film. In this state, the breakdown voltage between the second layer polySi gate and the source or drain (gate breakdown voltage) is poor, so after this, oxidation treatment is performed in a wet atmosphere at 850°C for 30 minutes to increase the gate breakdown voltage of the second layer polySi gate. In addition to improving the first layer polysi (83, 84
) The shape of the gate end has been improved to improve the withstand voltage. In this state, as shown in FIG.
2 films 85 and 86 are coated with S t of about 0.2 μm on the second polySi layer 91 and the source and drain n+ diffusion layers.
02 films (102, 104 to 112) are formed.

As mentioned above, after forming a MOS device as shown in FIG. 11 (J) GO using a material that can withstand high temperatures such as 7i>1 silicon as a gate electrode, an oxide film is formed on this gate electrode using a low-temperature oxidation method. , the thin SiO□ film on the Si substrate (well) was removed, a 5in2 film was formed on the substrate, a Si, N film was placed on top of it, and a gate electrode of PoIJSi was partially placed on top of it. A method of forming an oxide film by oxidizing the poly-Si gate surface using the Si3N film as a mask, and removing the Si3N+ film using this oxide film as a mask to form an MNO8 element as shown in Figure 11. By adopting MN after MOS
Since the O8 element is formed, the deterioration of the characteristics of the MNO3 element is reduced. Also, by applying selective oxidation method, MOS or MN
Since the gate of the OS is covered with an oxide film, a device with favorable characteristics such as interlayer breakdown voltage or interlayer capacitance can be obtained.

In this way, three MNO elements are formed, and the eight MNO element forming portions and MNO8 elements are formed corresponding to FIGS.
When the OS element forming portion is drawn using enlarged cross-sectional views, it becomes as shown in FIGS. 30 to 33. That is, as shown in Figure 30, 1
A polysilicon layer 91 is partially formed on a 5isN4 film 90 deposited on an extremely thin SiO film 88 of 0 nm or less, and a source/drain is formed within the substrate surface using this polysilicon layer as a mask. Then, as shown in FIG. 31, the surface of this polysilicon layer 910 is oxidized using the Si, N, and film as a mask, and a relatively thick oxide film (Sin2) 102 is formed on the surface. Furthermore, as shown in FIG. 32, the Si3N4 film 90 is partially etched away using the formed oxide film 102 as a mask. At this time, the thin SiO2 film 88 is also removed from the substrate surface, but as shown in FIG. 33, an oxide film (Si02) 104, 105 is formed on the surface of the exposed source/drain region by heat treatment in an oxidizing atmosphere. Form.

Depending on the combination of the gate electrode material and the Si or N4 film etching solution (or gas), the gate electrode may also be etched, but after patterning the gate electrode as described above, the gate electrode is oxidized using the Si8N4 film as a mask. Covering the electrode with an oxide film and using this oxide film as a mask, Si3N,
Since the film is etched, the gate electrode material is 5isN4.
This method can protect the fine gate electrode even when it is etched by an etching solution. Also, the 33rd
As shown in the figure, Si02 film 1 on polysilicon layer 91
02 and Si formed on the silicon substrate (well) surface.
Since the Si, N4 film 90 is completely covered with the O, films 104 and 105, by performing sufficient oxidation treatment in this way, a so-called protected gate (p?otected gate) is formed.
Since the structure of d gate) can be formed in a self-aligned manner, the gate breakdown voltage of the MNO8 element can be improved and the parasitic capacitance can be reduced.

Furthermore, as can be understood from FIGS. 30 to 33, by forming pixel elements including an MNO5 element and an MO3 element on the same semiconductor substrate, and leaving the Si, N4 film 90 only under the gate of the MNO8 element, As shown in FIG. 33, in the oxidation treatment performed to improve the gate breakdown voltage of the MO8 element, the end of the gate electrode of the MO8 element is also oxidized, creating an inverted canopy structure, which increases the gate breakdown voltage of the MO3 element. As a result, the gate breakdown voltage of both types of devices can be improved.

■ Next, after completing the process shown in Figure 11, electrical connections are made with each of the above oxide films as shown in No. 11N- to the underlying N+ layer or polysi layer by photo-etching. If necessary, for example (106,112
) and a predetermined portion, for example (110°111), of the SiO film that needs to be in contact with the p-type well is etched away. In this case, approximately 0.3 μm of SiO2
Since film etching is performed, only a portion of the oxide film in contact with the p-type layer is etched away, leaving a 5i02 film of about 0.3 .mu.m.

0 After that, after removing the photoresist film used in the above step, phosphorus silicate glass (hereinafter referred to as phosphorus glass) 20 with a P20□ concentration of about 1 mol was removed by CVD.
After that, heat treatment was performed at 900°C for 20 minutes in H2 atmosphere to densify the phosphorus glass and MNO3
Improve the characteristics of the element.

Thereafter, the areas where electrical connections need to be made with the N+ layer, polysilicon layer, p-type well layer, etc. described above are removed by a phosphorus photoetching method. At this time, holes (114 to 118) in the oxide film were opened to the light.
Then, the holes in the phosphor glass share at least a part of the area, and the surface of the Si substrate in that area or the po
Expose the lysi surface. In this state, the portions (116, 117, 60) that make contact with the p-type well have a film thickness of about 0.2 μm, although the film thickness is slightly reduced due to over-etching during photo-etching. Since the film remained, the remaining approximately 0.2 μm was further removed by photoetching so that the hole in the photoresist was placed inside the hole in the phosphor glass that had been previously drilled.
Then, the film is etched away.

When drilling a contact hole in a two-layer film of phosphor glass and 5in2 film, the etching speed of phosphor glass is fast<5I0
Since the etching speed of 2 is slow, there are processing problems such as the size of the holes becoming large or the adhesion between the photoresist and the phosphor glass worsening if holes are made in the two-layer film at once. As can be seen from the description of FIG. 1100 and partially enlarged views of FIGS. 34 to 36, first, holes are made in the S io2 film (105) on the substrate surface by etching using a contact mask (119). After that, phosphor glass (120) is deposited, and then the phosphor glass layer 120 is drilled so as to share at least a part of the contact hole 119 to form a hole 125, thereby forming a pattern. Holes can be drilled more accurately than designed values. Note that although FIG. 36 shows a configuration in which the hole 125 of the phosphor glass is slightly shifted from the hole 119 of the S io2 film, it is necessary to It is preferable to form the phosphor glass hole 125 so that all the holes 119 are exposed, and more preferably, even the end surface of the SiO2 film is exposed.

(g) Next, after removing the photoresist used above, an At vapor deposition film is formed on the entire surface at about 300°C. The film thickness is approximately 0.8 μm.

Next, a wiring pattern is formed on the At film by photoetching as shown in FIG.
After removing the photoresist, the above A/, and n'',
In order to ensure contact with poly Si or p-type well and to reduce the surface state, H2
Heat treatment is performed at about 450° C. for 60 minutes in an atmosphere.

By completing the steps (5) to 0 described in detail above, as shown in FIG. With the depletion type MO3 element, the semiconductor region, NPN consisting of 97, 11, 1, without increasing the special photomall
type bipolar transistors can be formed in and on one semiconductor substrate 1. In the figure, 121 is the source or drain electrode of the EMO8 element, 122 is the emitter electrode of the bipolar transistor, 123 is the space electrode of the same transistor and the electrode of the p-type well region 11, and 124 is the electrode of the region 22 and the substrate. It consists of

FIG. 15 shows a plan view of the memory array before forming the phosphor glass layer, and FIG. 16 shows a plan view of the memory array after forming the aluminum wiring. Also the first
7, FIG. 18, and FIG. 19 respectively show a section taken along line AA, section taken along line BB, and section taken along line CC of the plane shown in FIG. 16.

The memory array consists of P
It is formed on the mold well region 10a.

In FIG. 15, the source region, drain region, and channel region of the MNOS of the memory cell and the switch MISFET are shown separated by dashed lines. Area C) II, CH surrounded by the dashed line above
A thick silicon oxide film 60 is formed on the surface of the P-type well region 10a other than P-type well region 2.

On the surface of the P-type well region 10a, a plurality of polygons are formed on the surface of the P-type well region 10a through a silicon oxide film in a direction crossing the areas CHI and CH2, which are used as gate electrodes of MISFETs for switching of memory cells and as first word lines. Crystalline silicon layer Wl
1, W21, W31°W41 are arranged.

Similarly, a plurality of polycrystalline silicon layers Wl 2 serve as gate electrodes of MNOS of memory cells and serve as second word lines.
, W22, W32, and W42 are arranged.

an area CHI not covered with each of the polycrystalline silicon layers;
An n-type impurity is introduced into the surface of the P-type soil region 10a in CH2 by the manufacturing method described above with reference to FIG. The area is formed.

In area CHI, n+ type region 92a polycrystalline silicon layers Wl 1 , Wl 2 and n+ type region 92a,
A first memory cell is configured. That is, the n+ type region 92a constitutes the drain region of the switching MISFET, and the polycrystalline silicon layer Wll constitutes its gate electrode. Further, the polycrystalline silicon layer W12 constitutes a gate electrode of the MNOS, and the n-type region 94a constitutes its source region.

Within the area CHI, the n+ type region 92b polycrystalline silicon layer W21. is adjacent to the first memory cell. W
22 and n+ type region 94b constitute a second memory cell. That is, 92b above.

W21. W22 and 94b are respectively MIS for switches.
It forms the drain region of the FET, the gate electrode thereof, the gate electrode of the MNOS, and the source region thereof.

Similarly, within said area CHI, 94c.

W32. W31,92c constitutes the third memory cell,
92d, W41. W42 and 94d constitute a fourth memory cell.

First to fourth memory cells are also formed in the area adjacent to the area CI-I 1, although no symbols are attached thereto.

Each memory cell formed in the area CHI constitutes a first memory cell column, and similarly each memory cell formed in the area CH2 constitutes a second memory cell column.

The polycrystalline silicon layer Wll as the first word line
As shown in FIG. 5, an extended portion Wl extends across the bottom of the polycrystalline silicon layer W12 on the thick silicon oxide film 60.
I have LA or Wllc.

Since the polycrystalline silicon layer W12 constitutes the second word line as described above, the voltage of +25V is applied when writing the storage information.
will be exposed to high voltages such as Therefore, a parasitic channel may be induced in the surface of the P-type well region 10a under the polycrystalline silicon layer W12. The polycrystalline silicon layer Wll constitutes a first word line and receives a low voltage signal such as +5V mentioned above. Therefore, the parasitic channel induced in the surface of the P-type well region 10a under the polycrystalline silicon layer W12 is
They are respectively blocked below the extensions W 11 a to Wllc of WII.

As a result, the memory cells in areas CH1 and CI-I2 are electrically coupled to each other by the parasitic channels.
As a result, it is possible to prevent undesirable operations such as information not being written to a memory cell to be selected.

A phosphorus glass layer 120 is formed on the surface of the memory array shown in FIG. 15 by the manufacturing method described in FIG. Open hole CNTl exposing the area
to C5 (see FIG. 6) are provided.

Next, aluminum is deposited and selectively etched, and as shown in FIG.
I, ED2, Dl and D2 are formed.

The wiring layer EDI has the openings CNT1 and CN, respectively.
In T3 and CNT5, the n++ region 94 serves as the source region of the MNOS in the first to fourth memory cells.
a, 94b, 94c and 94d (see FIG. 15). Therefore, this wiring layer EDI constitutes a reference potential line of the memory array.

Wiring layer 1 is the above-mentioned open-hole CNT2 and CNT, respectively.
4, contacts n+ type regions 92a, 92b, 9'2c, and 92d as drain regions of switch MISFETs in the first to fourth memory cells.

Therefore, this wiring D1 constitutes a digit line of the memory array.

Similarly, wiring layer ED2. C2 constitutes another reference potential line and digit line, respectively.

As shown in FIG. 15, the above memory array has an MNOS and a switching M
The arrangement with the ISFET is alternately reversed. Therefore,
For example, the n+ type regions of adjacent memory cells such as 92a and 92b, 94b and 94c can be shared, and the column direction size is larger than that in the case where the n+ type regions for each memory cell are formed independently. can be made smaller.

Also, as shown in FIG. 16, an area C where memory cells are formed
Aluminum wiring layers EDI, ED2 . Di, D2 to the above areas CHI, CH
2 is inclined with respect to the extending direction, the dimension in the row direction, that is, in the lateral direction of the paper surface, can be made smaller than in the case where the wiring area is set independently of the above-mentioned area.

In addition, since an aluminum wiring layer is used as the reference potential line and the digit line as shown in the figure instead of using a semiconductor such as an n++ semiconductor wiring area, the resistance thereof can be made sufficiently small. The reduction in interconnect resistance allows the memory array described above to operate at high speeds. .

Fig. 20 shows the pattern of the unit X decoder before forming the phosphor glass layer, and Fig. 21 shows the pattern after forming the aluminum wiring layer in the portion corresponding to Fig. 20 above. .

Since each unit X decoder is provided corresponding to a memory cell row of the memory array, each unit X decoder is taken into account so as not to increase the pitch of the memory cell row. Therefore, although not particularly limited, as described below, in FIGS. 20 and 21, the combination of two unit X decoders is substantially one unit.

In FIG. 20, the X decoder consists of an n-type silicon substrate 1
It is formed on the P-type well region 11 formed above. The region for forming each MISFET is surrounded by a dashed line in the figure. A thick silicon oxide film 60 is formed on the surface of the P-type well region 11 other than the above-mentioned regions, as described above.

On the silicon oxide film 60 and the gate oxide film on the region surrounded by the dotted chain line, a first polycrystalline silicon layer Wl having a pattern as shown by the combination of dots and solid lines is formed.
1, W21, aO, ao'al, and al' are formed. Of the region surrounded by the above-mentioned dashed-dotted line, an n+ type region is formed by the manufacturing method shown in FIG. 11 above except under the above-mentioned polycrystalline silicon layer.

In FIG. 20, under the polycrystalline silicon layer in the diagonally shaded area on the lower left, there is an enhancement type MISF.
This means that the channel region of the ET is formed, and the channel region of the depletion type MIsFET is formed under the polycrystalline silicon layer in the area where the two diagonal lines on the lower left and lower right sides are combined. It means to be formed.

In the upper half of the paper in FIG. 20, the n+ type region VC
Ca, polycrystalline silicon layer Wll, and n+ type region W11. b
The depletion type MISFETQ3 is configured by the n+ type region Wllc, the polycrystalline silicon layer aO', and the n+ type region GNDa.
A 5FETQ4 is configured, and an enhancement type MISFETQ5 is configured by the n+ type region Wllc, the polycrystalline silicon layer al', and the n+ type region GNDb.

Similar MISF in the lower half of the paper in Figure 20
ETQ3' consists of Q4' and Q5'.

As shown in FIG. 21, a phosphor glass layer 120 is formed on the surface of the decoder shown in FIG. 20, and then holes are formed in the phosphor glass layer and the oxide film thereunder by selective etching.

By aluminum evaporation and selective etching, the 21st
Various aluminum wiring layers are formed as shown in the figure. In the figure, the openings provided in the phosphor glass layer and the insulating film such as the oxide film are indicated by X marks. Therefore, at the x-marked portions, each of the aluminum wiring layers contacts the underlying polycrystalline silicon scrap or semiconductor region.

In FIG. 21, a wiring layer Wlla is a wiring layer for short circuiting, and includes a polycrystalline silicon layer Wll as a gate electrode of MISFETQ3 (see FIG. 20), its source region, and the MISFETQ4. The n+ type region Wllb serving as a common drain region of Q5 is short-circuited. The wiring layer vCC is a wiring layer for power supply, and serves as a common drain region of MISFETQ3 and Q3' (see Fig. 20).
It is in contact with the + type region VCCa. The wiring layer GND is a wiring layer for grounding, and is in contact with the n+ type region GNDa serving as a common source region of MISFETQ4 and Q4'. In addition, as shown in FIG. 20, MISFETQ5.
The n+ type region GNDb as a common source region of Q5' is continuous with the above n+ type region NDa.

The wiring layers aO and aO are a pair of wiring layers that receive address signals of opposite phases to each other, and a selected one of them, that is, aO in the illustrated case, contacts the polycrystalline silicon layer aO' and also contacts the polycrystalline silicon layer aO''. are doing.

Similarly, wiring layers a1 and al are a pair of wiring layers that receive other address signals having mutually opposite phases. In the case shown, wiring layer a
1 is in contact with the polycrystalline silicon layer al', and the wiring layer a1 is in contact with the polycrystalline silicon layer a1''.

As described above, a unit decoder such as the X decoder XDI of FIG. 1 is configured in the upper half of FIG. 12, and another unit decoder such as XD2 is configured in the lower half.

The unit X decoders are arranged corresponding to memory cell rows. Therefore, the wiring layer VCC, GND.

ao, ao, al, :11, etc. are common to a plurality of unit X decoders.

Figures 22 and 22@B show the pattern of the unit write circuit before forming the phosphor glass layer, and the second
Figure 3 Person and Figure 23 B are the above Figure 22 Person and Figure 2, respectively.
2 shows a pattern after forming an aluminum wiring layer in a portion corresponding to FIG. 2B. The right end of the pattern in FIG. 22 is connected to the left end of FIG. 22B, and similarly the right end of the person in FIG. 23 is connected to the left end of FIG. 23B.

The patterns in FIGS. 22A and B and FIGS. 23A and B are shown using the same notation as in FIGS. 20 and 21.

For the same reason as the X-data, the two unit write circuits are essentially one unit.

A polycrystalline silicon layer W serving as a first word line is extended over a P-type well region 10b indicated by a two-dot chain line for configuring a memory array through a thick silicon oxide film 60.
ll and W21 are aluminum wiring layers WIIC, respectively.
, W21C formed in the P-type well region 11
I 5FETQ15. Q15' drain region Wild
, contacts W21d.

As shown in the figure, an aluminum wiring layer e to which a signal from an erase circuit (see FIG. 1) is applied is in contact with the P-type well region 10b.

A signal from a control line We (see FIG. 1) is applied to the polycrystalline silicon layer We serving as the gates of the MISFETs QI 5 and Ql 6.

Polycrystalline silicon layer W12°W22 as second word line
are aluminum wiring layers W12a, respectively.

MI 5FET QI 6 and Ql 7 formed in the P-type well region 11 shown by the two-dot chain line through W22a
The common drain region W12b of MISFETs Q16' and Q17' is in contact with the common drain region W12b of MISFETs Q16' and Q17', and further in contact with the polycrystalline silicon layers Wl 2c and W22c, respectively.

The above MISFETQI 6 , QL 7 , Ql 6'
Polycrystalline silicon layer vCC as common gate of Q17'
A power supply voltage of +5■ is applied to.

Common drain region G of MISFETQlB and Q18'
NDa has an aluminum wiring layer GN that is set to the ground potential.
D is in contact.

The polycrystalline silicon layer W12c is an independent P-type well region 1.
1", and is in contact with the source region W12e of the MISFET QI 9 and the P-type well region 11r through the aluminum wiring layer Wl 2d.

Similarly, the polycrystalline silicon 1W22c is connected to the MISFETQI9' formed in another independent P-type well region 111.
The gate electrode of the aluminum wiring layer W22
d, the source region W of the MISFET Q19'
22e and the P-type well region 11s.

The MISFETs Q19 and Q19' have the structure as explained in FIG. 9 or FIG. 11 above. - The above MI 5FETQI extended on the silicon substrate 1
The common drain region VPPa of Q9 and Q19' is in contact with an aluminum wiring layer VPP to which a high voltage for writing and erasing is applied.

For example, the circuit WAI in FIG. 1 is configured by the MI 5FETs Q15 to QL9, and Q15' to Q1
9' constitutes another circuit WA2.

The unit write circuits shown in FIGS. 22A and 22B and FIGS. 23A and 23B are arranged in correspondence with memory cell rows, similar to the X decoder described above.

FIG. 24 shows the pattern of the Y gate before forming the phosphor glass layer, and FIG. 25 shows the pattern of the portion corresponding to FIG. 24 after forming the aluminum wiring layer.

In the polycrystalline silicon layer CD as a common digit line,
Aluminum wiring layer C for connecting unit gates in parallel
Da is in contact.

The above aluminum wiring layer CDa is MISFETQII
and QL3 are in contact with the common drain region CDb. Polycrystalline silicon layer Yla serves as the gate electrode of MISFET QI 1 and Ql 3.

Aluminum wiring layers Yl and Y2, which receive outputs from Y decoders MDI and YD2 (see FIG. 1), respectively, are in contact with Y2a.

The source region of MI 5FET QI 1 and the drain region of Ql2 are made into a common n+ type region Dlb, and similarly MI
The source region of 5FET QI3 and the drain region of QI4 are a common n+ type region.

A power supply voltage of +5V is supplied to the polycrystalline silicon layer vCC as the gate electrode of the MISFETs QIZ and Ql4.

An aluminum wiring layer Di serving as a digit line is in contact with the source region Dla of MISFETQ12, and an aluminum wiring layer serving as another digit line is similarly in contact with the source region D2a of MI 5FETQI 40.

FIG. 26 and FIG. 26B show the pattern of the write inhibit circuit before forming the phosphor glass layer, and FIG.
Figure 2 and Figure 27B show the patterns of the portions corresponding to Figures 26A and 26B, respectively, after the aluminum wiring layer has been formed. As a pattern, the lower end of the figure 26 is connected to the upper end of FIG. 26B, and similarly the lower end of FIG. 27 is connected to the upper end of FIG. 27B.

As shown in FIG. 6, since the wiring region WIR is arranged between the memory array and the write inhibit circuit, the aluminum wiring layer ED1 as the reference potential line explained in FIGS. 15 and 16 is not particularly limited. , ED2 is each MISFE
The polycrystalline silicon layers ED1a+ED2a formed at the same time as the polycrystalline silicon layer T are brought into contact with each other. In the wiring region WTR, the polycrystalline 7 silicon layer E
Various aluminum wiring layers are formed on Dla and EDla via an oxide film and a phosphorus glass layer.

Note that FIGS. 26A and B and FIGS. 27A and B are shown using the same notation as each of the above figures. Therefore, the second
A description of the structure of the write inhibit circuit in FIGS. 6A and 6B and FIGS. 27A and 27H will be omitted.

According to this invention, as shown in FIG. 6, since the decoder and the readout circuit are placed across the memory array, the operating speed, particularly the read operating speed, can be increased. On the other hand, if the decoder and write circuit are placed on one side of the memory array, for example, the wiring from the decoder to the memory cell becomes long, and since multiple circuits are placed on one side of the memory array, it is difficult to The number of well-known cross-wiring locations will increase. As a result, the signal transmission characteristics of the wiring paths that supply signals to the memory array deteriorate, and the operating speed is limited.

As mentioned above, when placing the decoder and write circuit across the memory array, the pitch between the unit decoder and write circuit can be made relatively small, so the size of the memory array does not have to be limited by these circuits. Become good.

Furthermore, since a write inhibit circuit such as a gate or a decoder is placed across the memory array, high-speed operation can be achieved for the same reason as above.

As mentioned above, the configuration in which a decoder and a write circuit are placed across a memory array, or the configuration in which a gate or a decoder and a write circuit are placed across a memory array, are different from other configurations that use a write circuit or a write-protection circuit. It can be applied to various types of storage devices.

According to the invention, using the well region as described above,
This well region can be effectively used for high voltage circuits.

In the voltage divider circuit in which the enhancement mMIsFETs Q37 to Q39 of FIG. 1 are connected in series, the MI
Since the highest voltage is applied to the drain of MISFETQ37, if this MISFETQ37 is destroyed by high voltage, the Q
A high voltage will be applied to 38. As a result, the MISFETs connected in series are destroyed one after another. However, if MI 5FET Q37, to which the highest voltage is applied, is made to have a structure that utilizes the well region as described above to achieve a high breakdown voltage, even if the other MISFETs Q38 and Q39 have a normal structure, the breakdown as described above will occur. can be prevented. The voltage divider circuit as described above can be used in circuit devices other than the memory circuit device of the embodiment.

Similarly, circuits such as the erase circuit and write inhibit voltage generation circuit shown in FIG. 1 can be used for other purposes.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a semiconductor memory circuit, FIGS. 2, 3, and 4 are operation timing charts of the circuit in FIG.
5 is a block diagram of a semiconductor memory circuit, FIG. 6 is a plan view of a semiconductor memory circuit device, FIG. 7 is a plan view of a semiconductor substrate forming the semiconductor memory circuit device shown in FIG. 6, and FIG. is a cross-sectional view of the AA' part in Fig. 7, and Fig. 9 is a cross-sectional view of the MISFET.
10 is a sectional view of a semiconductor substrate on which a bipolar transistor is formed, FIG. 11 is a sectional view of a semiconductor substrate in each manufacturing process of a semiconductor memory circuit device (A) to 0), Figure 12 is a cross-sectional view of the MNOS, Figure 13 is a characteristic curve diagram of the MNOS in Figure 12,
FIG. 14 is an equivalent circuit diagram of the memory cell, FIG. 15 is a plan view of the memory array before forming the phosphor glass layer, and FIG.
The figure is a plan view of the memory array after forming the aluminum wiring layer, and FIGS. 17, 18, and 19 are the AA', BB', and c-c' sections of FIG. 16, respectively. 20 is a cross-sectional view of X before forming the phosphorus glass layer.
A plan view of the decoder, FIG. 21 is a plan view of the X decoder after forming an aluminum wiring layer, FIGS.
Figure B is a plan view of the write circuit before the phosphor glass layer is formed, Figures 23A and 23B are plan views of the write circuit after the aluminum wiring layer is formed, and Figure 24 is a plan view of the write circuit before the phosphor glass layer is formed. FIG. 25 is a plan view of the Y gate before formation, FIG. 25 is a plan view of the Y gate after forming the aluminum wiring layer, and FIG. 26A and FIG. Plan view of the circuit, Figure 27A and Figure 2
Figure 7B is a plan view of the write inhibit circuit after forming the aluminum wiring layer, Figures 28 and 29 are 5i-3i
FIGS. 30 to 33 and 34 to 36 are state diagrams showing the concentration distributions of phosphorus and boron impurities at the n2 interface, respectively, and are cross-sectional views of the main parts of the semiconductor device for each manufacturing process. MA...Memory array, XDI, XD2...X decoder, YGO...Y gate, YDI, YD2...
・X decoder, WAI, WA2...Writing circuit, I
HAl...Write inhibit circuit, IHA2...Write inhibit voltage generation circuit, ER3...Erase circuit, CI'L
L...Control circuit, IO3...Sense circuit, l0It
...output buffer circuit, IOW...data input circuit, BO~BIO...input buffer circuit. Figure 2 Figure 3 Figure 5 Figure 2 Figure 3 Figure 5 Figure 2 Figure 3 Figure 5

Claims (1)

[Claims] 1. A memory array section formed in a substantially rectangular first region on the main surface of a semiconductor substrate and consisting of a plurality of memory cells arranged in rows and columns, and arranged along each column of the memory array section. a second region located at one end of the pair of wiring groups and adjacent to a first side of the first region; a decoder circuit section for selecting the digit line formed in the digit line; and a decoder circuit section located at the other end of the pair of wiring groups;
a write inhibit circuit unit for controlling a potential of the reference potential line formed in a third region adjacent to a second side opposite to a first side of the first region, the memory A cell is formed of an MNOS element and a MOS element that are electrically connected in series between the pair of wires arranged in each column, and the gate of the memory cell group in each row is connected to a word line extending along the corresponding row. A semiconductor memory circuit device, characterized in that it is electrically connected to a semiconductor memory circuit device.