JPH0231502B2 - - Google Patents

Info

Publication number
JPH0231502B2
JPH0231502B2 JP59054911A JP5491184A JPH0231502B2 JP H0231502 B2 JPH0231502 B2 JP H0231502B2 JP 59054911 A JP59054911 A JP 59054911A JP 5491184 A JP5491184 A JP 5491184A JP H0231502 B2 JPH0231502 B2 JP H0231502B2
Authority
JP
Japan
Prior art keywords
layer
substrate
pin
palladium
gold
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59054911A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60198762A (ja
Inventor
Juzo Shimada
Kazuaki Uchiumi
Hideo Takamizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5491184A priority Critical patent/JPS60198762A/ja
Publication of JPS60198762A publication Critical patent/JPS60198762A/ja
Publication of JPH0231502B2 publication Critical patent/JPH0231502B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49866—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers characterised by the materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H05K3/061—Etching masks
    • H05K3/064—Photoresists

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP5491184A 1984-03-22 1984-03-22 ピン付基板およびその製造方法 Granted JPS60198762A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5491184A JPS60198762A (ja) 1984-03-22 1984-03-22 ピン付基板およびその製造方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5491184A JPS60198762A (ja) 1984-03-22 1984-03-22 ピン付基板およびその製造方法

Publications (2)

Publication Number Publication Date
JPS60198762A JPS60198762A (ja) 1985-10-08
JPH0231502B2 true JPH0231502B2 (enrdf_load_stackoverflow) 1990-07-13

Family

ID=12983780

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5491184A Granted JPS60198762A (ja) 1984-03-22 1984-03-22 ピン付基板およびその製造方法

Country Status (1)

Country Link
JP (1) JPS60198762A (enrdf_load_stackoverflow)

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824009A (en) * 1981-12-31 1989-04-25 International Business Machines Corporation Process for braze attachment of electronic package members

Also Published As

Publication number Publication date
JPS60198762A (ja) 1985-10-08

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Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term