JPH0227817B2 - - Google Patents

Info

Publication number
JPH0227817B2
JPH0227817B2 JP59054910A JP5491084A JPH0227817B2 JP H0227817 B2 JPH0227817 B2 JP H0227817B2 JP 59054910 A JP59054910 A JP 59054910A JP 5491084 A JP5491084 A JP 5491084A JP H0227817 B2 JPH0227817 B2 JP H0227817B2
Authority
JP
Japan
Prior art keywords
brazing
gold
ceramic substrate
layer
film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59054910A
Other languages
English (en)
Japanese (ja)
Other versions
JPS60198761A (ja
Inventor
Juzo Shimada
Kazuaki Uchiumi
Masanori Suzuki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5491084A priority Critical patent/JPS60198761A/ja
Publication of JPS60198761A publication Critical patent/JPS60198761A/ja
Publication of JPH0227817B2 publication Critical patent/JPH0227817B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0306—Inorganic insulating substrates, e.g. ceramic, glass
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/09—Use of materials for the conductive, e.g. metallic pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/30—Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34—Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457—Solder materials or compositions; Methods of application thereof

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Lead Frames For Integrated Circuits (AREA)
JP5491084A 1984-03-22 1984-03-22 ろう付け方法 Granted JPS60198761A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5491084A JPS60198761A (ja) 1984-03-22 1984-03-22 ろう付け方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5491084A JPS60198761A (ja) 1984-03-22 1984-03-22 ろう付け方法

Publications (2)

Publication Number Publication Date
JPS60198761A JPS60198761A (ja) 1985-10-08
JPH0227817B2 true JPH0227817B2 (enrdf_load_stackoverflow) 1990-06-20

Family

ID=12983753

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5491084A Granted JPS60198761A (ja) 1984-03-22 1984-03-22 ろう付け方法

Country Status (1)

Country Link
JP (1) JPS60198761A (enrdf_load_stackoverflow)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2004034450A1 (en) * 2002-10-11 2004-04-22 Tm Tech Co., Ltd. A sputtering apparatus having enhanced adhesivity of particles and a manufacturing method thereof
WO2004055873A1 (en) * 2002-12-14 2004-07-01 Tm Tech Co., Ltd. Thin film forming apparatus
CN113242650B (zh) * 2021-05-20 2022-04-15 上海望友信息科技有限公司 一种喷涂图形生成方法、系统、电子设备及存储介质

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4824009A (en) * 1981-12-31 1989-04-25 International Business Machines Corporation Process for braze attachment of electronic package members

Also Published As

Publication number Publication date
JPS60198761A (ja) 1985-10-08

Similar Documents

Publication Publication Date Title
US4463059A (en) Layered metal film structures for LSI chip carriers adapted for solder bonding and wire bonding
US6159586A (en) Multilayer wiring substrate and method for producing the same
EP0997941B1 (en) Conductive paste and ceramic printed circuit substrate using the same
JPH08306816A (ja) 電極パッド
JPH0227817B2 (enrdf_load_stackoverflow)
JP3086081B2 (ja) 配線基板とその製造方法
JPH0230185B2 (enrdf_load_stackoverflow)
JPH11163522A (ja) 多層配線基板およびその製造方法
JP3210740B2 (ja) 多層回路基板および電子モジュ−ルならびに電子装置
JPS6196754A (ja) ピン付き基板
JPH0227818B2 (enrdf_load_stackoverflow)
JPH0760882B2 (ja) ろう付け方法
JP3723350B2 (ja) 配線基板およびその製造方法
JPH0590761A (ja) 配線基板の製造方法
JPH0231502B2 (enrdf_load_stackoverflow)
JPS6181659A (ja) ピン付き基板
JPH0136998B2 (enrdf_load_stackoverflow)
JPH0136999B2 (enrdf_load_stackoverflow)
JPH05267496A (ja) セラミックス配線基板の製造方法
JP2630303B2 (ja) 多層配線基板
JPH10139559A (ja) ガラスセラミック基板及びその製造方法
JPH11307688A (ja) 配線基板及びその製造方法
JPS60170294A (ja) ピン付き多層配線基板の製造方法
JPS62291153A (ja) セラミツク配線基板
JPH0272696A (ja) セラミックス回路基板

Legal Events

Date Code Title Description
EXPY Cancellation because of completion of term