JPH02310647A - Information processor - Google Patents

Abstract

PURPOSE:To reduce the number of the steps of a microprogram so as to improve a processing speed by converting an address by means of a segment base value which the micro program selects and a generated logical address. CONSTITUTION:When an instruction which is memory-transferred from an operand 1 that is to be address-converted by using a first segment base value to an operand 2 that is to be address-converted by using a second segment base value is executed, a logical address generation circuit 6 generates the logical address of the operand 1 by the control of a program transmitted from a control storage device 5. The logical address of the operand 1 generated in the logical address generation circuit 6 is transmitted to a register 3 and is held in the register 3. The micro program transmitted from the control storage device 5 to the logical address generation circuit 6 at that time address- converts the operand 1 by using the first base segment value.

Description

DETAILED DESCRIPTION OF THE INVENTION TECHNICAL FIELD The present invention relates to an information processing apparatus, and more particularly to address conversion control of an information processing apparatus.

BACKGROUND ART Conventionally, in an information processing device, a logical address of an operand generated by a logical address generation circuit under the control of a microprogram that controls address generation of an operand, and first and second segment bases each held in a register are used. Among the values, address translation is performed by the address translation device based on the segment base value specified by the identifier.

Here, the value of the identifier can be updated by instructions from a microprogram that controls execution of instruction operations.

In such conventional information processing devices, switching of the segment base value sent to the address translation device is controlled by updating the value of the identifier according to instructions from a microprogram that controls the execution of instruction operations. When executing an instruction that performs memory transfer between an operand whose address should be translated using one segment base value and an operand whose address should be translated using a second segment base value, control of the execution of the instruction's operation is performed. The microprogram to be executed must perform control such as memory transfer while performing control to switch the value of the identifier.

However, except for the process of switching the identifier value, the microprogram may use the same processing format as a microprogram that executes an instruction to transfer memory between operands whose addresses should be converted using the same segment base value. Nevertheless, these microprograms are required separately, and the number of microprogram steps for controlling the execution of instruction operations increases.

In addition, before the microprogram that controls the execution of instruction operations performs control to switch the value of the identifier, the state of the identifier is recognized, and the operand whose address should be converted using the first segment base value and the first After executing an instruction that performs memory transfer between the operand whose address is to be translated using the segment base value of 2, the state of the identifier must be restored to the state before the instruction was executed. The disadvantage is that the processing speed is reduced.

OBJECTS OF THE INVENTION The present invention has been made to eliminate the drawbacks of the conventional ones as described above, and provides an information processing device that can reduce the number of microprogram steps and increase processing speed. purpose.

Configuration of the Invention An information processing apparatus according to the present invention reads out a segment base value selected according to an identifier indicating which of a first segment base value and a second segment base value is to be used, and from a control memory. An information processing device that performs address conversion based on a logical address generated by a microprogram, the information processing device comprising: identifier validity information added to the microprogram to indicate validity of the identifier; identification information indicating which segment base value is to be used for address conversion; and selection means for selecting one of the first and second segment base values based on the identifier valid information and the identification information; The present invention is characterized in that address conversion is performed using the segment base value selected by the means and the logical address generated by the microprogram.

Embodiment Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In the figure, register 1 holds the first segment base value consisting of 31 bits, and register 2 holds the 31-bit first segment base value.
A second segment base value consisting of one bit is maintained.

Further, the identifier 4 holds information indicating which of the first and second segment base values held in the register 1.2 is used for address translation of the operand.

If the identifier 4 holds logic "0", the first segment base value is used for address translation of the operand, and if logic "1" is held, the second segment base value is used for address translation of the operand. Segment base values are used.

The control storage device 5 includes a control storage (not shown) that holds a microprogram that controls address generation, and an ni control circuit (not shown) that controls the control storage.

The logical address generation circuit 6 is controlled by a microprogram held in the control storage device 5 and generates a logical address of an operand consisting of 31 bits.

The logical address generated by the logical address generation circuit 6 is temporarily held in the register 3 and then sent from the register 3 to the address translation device 9.

The selector control circuit 7 includes information held in the identifier 4 and is added to the microprogram held in the control storage device 5, and is added to the register 1 .
Information indicating which of the first and second segment base values held in identifier 2 is to be used (hereinafter referred to as the S bit), and information indicating whether the S bit has priority over the information from identifier 4. (hereinafter referred to as V bit) is manually operated,
A control signal to the selector 8 is generated based on this information.

■If the bit is logical 1°, it indicates that the S bit has priority over the information from identifier 4, and in this case, the S bit has the same meaning as the information from identifier 4. '' indicates that the S bit does not take priority over the information from identifier 4.

The selector 8 responds to a control signal from the selector control circuit 7 to
One of the first segment base value held in register 1 and the second segment base value held in register 2 is selected, and the selected segment base value is sent to address translation device 9.

The address translation device 9 performs address translation using the logical address sent from the register 3 and the segment base value sent from the selector 8.

FIG. 2 is a diagram showing the control logic of the selector control circuit 7 of FIG. 1. In the figure, when the v bit sent from the control storage device 5 is a logic “0°,” the selector control circuit 7 does not take priority over the information from the identifier 4, so the S bit is a logic “0” or a logic “No matter which one is 1゛,
The control signal output to the selector 8 is the same as the value of the identifier 4. That is, if the value of identifier 4 is logic "0", the control signal is also logic "0°", and the value of identifier 4 is logic "1".
", the control signal is also logic "1".

When the V bit is a logic "1", the S bit has priority over the information from the identifier 4, so the value of the identifier 4 is a logic "0".
” or logic “1”, the control signal output to the selector 8 is the same as the S bit.
If the bit is a logic "0", the control signal will also be a logic "0", and if the S bit is a logic "1", the control signal will also be a logic "1".

The operation of an embodiment of the present invention will be explained using FIG. 1 and FIG. 2. It is assumed that the identifier 4 holds a logic "0".

When executing an instruction to perform memory transfer from operand 1 whose address should be converted using the first segment base value to operand 2 whose address should be converted using the second segment base value, the logical address generation circuit 6 10
The logical address of operand 1 is generated under the control of a microprogram sent from control storage 5 via 2.

The logical address of operand 1 generated by the logical address generation circuit 6 is sent to the register 3 via the signal line 103 and is temporarily held in the register 3.

At this time, from the control storage device 5 to the logical address generation circuit 6
The microprogram sent via the signal line 102 requires operand 1 to perform address conversion using the first base segment value, so it sets logic "1°" to the V bit and logic "0" to the S bit. Each signal is output to the selector control circuit 7 via the signal line 10B.

The selector control circuit 7 also has a signal line 105 from the identifier 4.
A logic "0" is output through the output.

Therefore, the selector control circuit 7 outputs logic "0" as a control signal to the selector 8 via the signal 11107 based on this information.

As a result, the selector 8 selects the first segment base value sent from the register 1 via the signal line 100, and sends the segment base value to the address translation device 9 via the signal line 10g.

The address translation device 9 uses the logical address sent from the register 3 via the signal line 103 and the first segment base value sent from the selector 8 via the signal line 108 to address the operand 1. Conversion takes place.

Next, the logical address generation circuit 6 generates the logical address of the operand 2 under the control of the microprogram sent from the control storage device 5 via the signal line 102.

The logical address of operand 2 generated by the logical address generation circuit 6 is sent to the register 3 via the signal line 103 and is temporarily held in the register 3.

At this time, from the control storage device 5 to the logical address generation circuit 6
Since operand 2 needs to be address translated using the second base segment value, the microprogram sent via signal line 102 to
and outputs logic "1" to the S bit to the selector control circuit 7 via the signal line 106, respectively.

The selector control circuit 7 also has a signal line 105 from the identifier 4.
Logic "0" is outputted via.

Therefore, the selector control circuit 7 outputs the logic "1°" as a control signal to the selector 8 via the signal line 107 based on this information.

As a result, the selector 8 selects the second segment base value sent from the register 2 via the signal line 101 and sends the segment base value to the address translation device 9 via the signal line 108.

The address conversion device 9 uses the logical address sent from the register 3 via the signal line 103 and the second segment base value sent from the selector 8 via the signal line lO8 to determine the address of the operand 2. Conversion takes place.

As described above, when executing an instruction to perform memory transfer from operand 1 whose address should be translated using the first segment base value to operand 2 whose address should be translated using the second segment base value, the address translation device 9 is $-11all,? c! Address translation of operand 1.2 is performed using the segment base value indicated by the microprogram in storage device 5.

Further, when executing an instruction to perform memory transfer between operands 3 and 4 whose addresses should be converted using the same segment base value, the logical address generation circuit 6 receives the information sent from the control storage device 5 via the signal line 102. The logical address of operand 3 is generated under the control of the microprogram.

The logical address of operand 3 generated by logical address generation circuit 6 is sent to register 3 via signal line 103 and is temporarily held in register 3.

At this time, from the control storage device 5 to the logical address generation circuit 6
The microprogram sent via the signal line 102 sets the V bit to logic “0” because it is necessary to perform address conversion using the same base segment value for operands 3 and 4.
” and logic “0” to the S bit are output to the selector control circuit 7 via the signal line 106, respectively.

The selector control circuit 7 also has a signal line 105 from the identifier 4.
Logic "0" is outputted via.

Therefore, the selector control circuit 7 outputs a logic "O" as a control signal to the selector 8 via the signal line 107 based on this information.

As a result, the selector 8 selects the first segment base value sent from the register 1 via the signal line 100 and sends the segment base value to the address conversion device 9 via the signal line 108.

The address conversion device 9 converts the operand 3 using the logical address sent from the register 3 via the signal line 1 (18) and the first segment base value sent from the selector 8 via the signal line 108. address translation is performed.

Next, in the same way as the above-described process, the address conversion device 9 receives the logical address sent from the register 3 via the signal line direction 3 and the first logical address sent from the selector 8 via the signal line 108. Address translation of operand 4 is performed using the segment base value of .

As mentioned above, when executing an instruction that performs memory transfer between operands 3 and 4 whose addresses should be translated using the same segment base value, the address translation device 9 uses the identifier 4.
Address translation of operands 3 and 4 is performed using the segment base value indicated by the value of .

In this way, the V bit and S bit are added to the microprogram in the control storage device 5, and these V bits and S bits enable the first and second bits held in the register 1.2 to be used for address translation of the operand. Controls which of the first and second segment base values the microprogram in the control store 5 uses for address translation of the operands by indicating which of the segment base values to use. can do.

Therefore, the microprogram that controls the execution of instruction operations does not need to switch the value of identifier 4, and the operand 1 whose address should be converted using the first segment base value and the second segment base value Recognize the state of identifier 4 before executing an instruction that performs memory transfer between operand 2 and address conversion using , and restore the state of identifier 4 to its previous state after executing the instruction. This action is no longer necessary.

Therefore, the microprogram for this instruction can share the processing with the microprogram for executing an instruction for performing memory transfer between operands 3 and 4 whose addresses should be converted using the same segment base value.
The number of steps in a microprogram can be reduced, and the processing speed of its instructions can be increased.

DETAILED DESCRIPTION OF THE INVENTION According to the present invention, as described above, the identifier validity information indicating whether the identifier is valid or invalid indicating which of the first segment base value and the second segment base value is to be used, and address translation. Identification information indicating which segment base value to use is added to the microprogram, and address conversion is performed using the segment base value selected based on these identifier valid information and identification information, and the logical address generated by the microprogram. By doing so, the number of steps in the microprogram can be reduced and the processing speed can be increased.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, and FIG. 2 is a diagram showing the control logic of the selector control circuit of FIG. 1. Explanation of symbols of main parts 1 to 3... Register 4... Identifier 5... Control storage device 6... Logical address generation circuit 7... ...Selector control circuit 8...Selector

Claims (1)

[Claims] (1) A segment base value selected according to an identifier indicating which of the first segment base value and the second segment base value is to be used, and generated by a microprogram read from the control memory. an information processing device that performs address conversion based on a logical address, the information processing device comprising: identifier validity information added to the microprogram to indicate validity of the identifier; and any segment base value added to the microprogram to perform the address conversion; and selection means for selecting one of the first and second segment base values based on the identifier validity information and the identification information,
a segment base value selected by the selection means;
An information processing device characterized in that address conversion is performed using a logical address generated by the microprogram.