JPH0230929Y2 - - Google Patents
Info
- Publication number
- JPH0230929Y2 JPH0230929Y2 JP4435484U JP4435484U JPH0230929Y2 JP H0230929 Y2 JPH0230929 Y2 JP H0230929Y2 JP 4435484 U JP4435484 U JP 4435484U JP 4435484 U JP4435484 U JP 4435484U JP H0230929 Y2 JPH0230929 Y2 JP H0230929Y2
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- terminal
- reset
- level
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 230000001934 delay Effects 0.000 claims description 3
- 238000010586 diagram Methods 0.000 description 3
- 230000003111 delayed effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
Landscapes
- Electronic Switches (AREA)
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4435484U JPS60158332U (ja) | 1984-03-28 | 1984-03-28 | リセツト回路 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4435484U JPS60158332U (ja) | 1984-03-28 | 1984-03-28 | リセツト回路 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS60158332U JPS60158332U (ja) | 1985-10-22 |
JPH0230929Y2 true JPH0230929Y2 (US07223432-20070529-C00017.png) | 1990-08-21 |
Family
ID=30556846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4435484U Granted JPS60158332U (ja) | 1984-03-28 | 1984-03-28 | リセツト回路 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60158332U (US07223432-20070529-C00017.png) |
-
1984
- 1984-03-28 JP JP4435484U patent/JPS60158332U/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS60158332U (ja) | 1985-10-22 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4686386A (en) | Power-down circuits for dynamic MOS integrated circuits | |
JP2556728B2 (ja) | 集積回路 | |
JPH0230929Y2 (US07223432-20070529-C00017.png) | ||
JPH073751B2 (ja) | 電流サージ制御集積回路 | |
JPH11134868A (ja) | メモリチップ | |
JP3727670B2 (ja) | マイクロコントローラ | |
EP1126362A2 (en) | Microcomputer with internal reset signal generator | |
JP2845251B2 (ja) | 集積回路装置 | |
JPH0193928A (ja) | ダイナミック方式プログラマブルロジックアレイ | |
JP3266111B2 (ja) | クロック入力バッファ回路 | |
JPS5951624A (ja) | 初期設定回路 | |
JP2871186B2 (ja) | マイクロコンピュータ | |
JP2745507B2 (ja) | マイクロコンピユータ | |
US5999742A (en) | Dual latch data transfer pacing logic using a timer to maintain a data transfer interval | |
JP2995804B2 (ja) | スイッチングレギュレータのソフトスタート回路 | |
JP2797355B2 (ja) | D形フリップフロップ回路 | |
JPS5921718U (ja) | パルス数監視回路 | |
JPS62118557A (ja) | 半導体集積回路装置のモ−ド切換え回路 | |
JPH04183017A (ja) | フリップフロップ回路 | |
US5648737A (en) | Method of setting the polarity of a digital signal, and integrated circuits implementing the method | |
JPS6043293A (ja) | ラツチ付メモリ | |
JPH0865118A (ja) | 半導体集積回路 | |
JPS6359167B2 (US07223432-20070529-C00017.png) | ||
JPH02297683A (ja) | マイクロコンピュータ | |
JPS62177465A (ja) | 試験信号発生回路 |