JPH0229833Y2

JPH0229833Y2 -

Info

Publication number: JPH0229833Y2
Application number: JP1983097238U
Authority: JP
Priority date: 1983-06-23
Filing date: 1983-06-23
Publication date: 1990-08-10
Also published as: JPS605287U

Description

【考案の詳細な説明】技術分野本考案は、テレビジヨン受像機、ビデオカメラ
等の電源回路に使用するための多倍電圧整流装置
に関するものである。[Detailed Description of the Invention] Technical Field The present invention relates to a multiplier voltage rectifier for use in power supply circuits of television receivers, video cameras, and the like.

従来技術従来の多倍電圧整流装置は、コンデンサを主体
とした構成になつている。従つて、組み立てが比
較的複雑になり且つ小型化が困難であつた。Prior Art A conventional multiplier voltage rectifier has a configuration mainly composed of capacitors. Therefore, assembly is relatively complicated and miniaturization is difficult.

考案の目的そこで、本考案の目的は組み立てが容易で且つ
小型化が可能である多倍電圧整流装置を提供する
ことにある。Purpose of the invention Therefore, the purpose of the present invention is to provide a multiplier voltage rectifier that is easy to assemble and can be downsized.

考案の構成上記目的を達成するための本考案は、実施例を
示す図面の符号を参照して説明すると、複数個の
ダイオードD₁〜D₅と、第１及び第２のコンデン
サブロツクと、絶縁被覆２３とを具備し、前記複
数個のダイオードD₁〜D₅は本体部１〜５とこの
本体部１〜５から同軸方向に導出された一対のリ
ード線１ａ〜５ａ，１ｂ〜５ｂを夫々有し、前記
第１のコンデンサブロツクは第１の誘電誘電体磁
器基板７と複数個のコンデンサC₁，C₂が得られ
るように前記第１の誘電体磁器基板７の表面８及
び裏面１１に形成された複数個の電極９，１０，
１２とから成り、前記第２のコンデンサブロツク
は第２の誘電体磁器基板１３と、複数個のコンデ
ンサC₃，C₄，C₅が得られるように前記第２の誘
電体磁器基板１３の表面１４及び裏面１７に形成
された複数個の電極１５，１６，１８，１９とか
ら成り、前記複数個のダイオードD₁〜D₅の本体
部１〜５は並置され且つ相互に一体化され、前記
複数個のダイオードD₁〜D₅はこれ等の整流方向
が交互に変化するように配置され、前記第１のコ
ンデンサブロツクは前記複数個のダイオードD₁
〜D₅の一方の側のリード線１ａ〜５ａが導出さ
れている側に配置され、前記第２のコンデンサブ
ロツクは前記複数個のダイオードD₁〜D₅の他方
の側のリード線１ｂ〜５ｂが導出されている側に
配置され、前記複数個のダイオードD₁〜D₅の一
方の側に導出されているリード線１ａ〜５ａは前
記第１のコンデンサブロツクの電極９，１０，１
２を介して前記第１の誘電体磁器基板７を弾性変
形を伴つて挟持するように配置され、前記複数個
のダイオードD₁〜D₅の他方側に導出されている
リード線１ｂ〜５ｂは前記第２のコンデンサブロ
ツクの電極１５，１６，１８，１９を介して前記
第２の誘電体磁器基板１３を弾性変形をともなつ
て挟持するように配置されていることを特徴とす
る多倍電圧整流装置に係わるものである。Structure of the Invention To achieve the above object, _the present invention will be described with reference to the reference numerals _in the drawings showing the embodiments. The plurality of diodes D ₁ -D ₅ each have a main body 1 - 5 and a pair of lead wires 1 a - 5 a and 1 b - 5 b coaxially led out from the main body 1 - 5 , respectively. The first capacitor block has a first dielectric ceramic substrate 7 and a plurality of capacitors C ₁ and C ₂ on the front surface 8 and back surface 11 of the first dielectric ceramic substrate 7, respectively. A plurality of electrodes 9, 10,
12, the second capacitor block comprises a second dielectric ceramic substrate 13, and a surface of the second dielectric ceramic substrate 13 such that a plurality of capacitors C ₃ , C ₄ , C ₅ are obtained. 14 and a plurality of electrodes 15, 16, 18, 19 formed on the back surface 17, the main bodies 1 to 5 of the plurality of diodes _D1 to _D5 are arranged side by side and mutually integrated, A plurality of diodes D ₁ to _{D 5} are arranged so that their rectification directions alternately change, and the first capacitor block is connected to the plurality of diodes D ₁ .
The second capacitor block is arranged on the side from which the lead wires 1a to 5a on one side of the plurality of diodes D1 to D5 are led out, and the second capacitor block _is arranged on the side where the lead wires 1a to 5b on the other side of the plurality of diodes _D1 to _D5 are led out. The lead wires 1a to 5a, which are arranged on the side from which the plurality of diodes _D1 to _D5 are led out, are connected to the electrodes 9, 10, 1 of the first capacitor block.
The lead wires 1b to 5b are arranged so as to sandwich the first dielectric ceramic substrate 7 with elastic deformation through the lead wires _{1b to 5b, which are led out to the other side of the plurality of diodes D1} to _D5 . A multiple voltage multiplier characterized in that the second dielectric ceramic substrate 13 is sandwiched between the electrodes 15, 16, 18, and 19 of the second capacitor block with elastic deformation. This relates to a rectifier.

考案の作用効果本考案においては、複数個のコンデンサC₁，
C₅をえるための誘電体磁器基板７，１３を複数
個のダイオードD₁〜D₅のリード線１ａ〜５ａ，
１ｂ〜５ｂで挟持するので、組立てを容易に達成
することができ、小型化が可能になる。Effects of the invention In the invention, a plurality of capacitors C ₁ ,
The dielectric ceramic substrates 7 and 13 for obtaining _C5 are connected to the lead wires 1a to 5a of the plurality of diodes _D1 to _D5 ,
Since it is held between 1b to 5b, assembly can be easily achieved and miniaturization is possible.

実施例次に図面を参照して本考案の実施例に係わる倍
電圧整流装置について述べる。Embodiment Next, a voltage doubler rectifier according to an embodiment of the present invention will be described with reference to the drawings.

第１図〜第４図は実施例に係わる５倍電圧整流
装置を示すものである。第１図〜第３図に示す装
置は、５つの整流ダイオードD₁〜D₅と５つのコ
ンデンサC₁〜C₅とから成る。ダイオードD₁〜D₅
は夫々同軸方向リード型ダイオードであり、円柱
状本体部１〜５を夫々有し、且つ夫々の本体部１
〜５から同軸方向に導出されたリード線１ａ，１
ｂ，２ａ，２ｂ，３ａ，３ｂ，４ａ，４ｂ，５
ａ，５ｂを有し、本体部１〜５において接着材６
で相互に一体化されている。なお、ダイオード
D₁〜D₅は第１図及び第２図から明らかな如く整
流方向が交互に逆になるように配列され、且つ本
体部１〜５が断面形状で一列になるように配列さ
れている。 1 to 4 show a five-fold voltage rectifier according to an embodiment. The device shown in FIGS. 1-3 consists of five rectifier diodes _D1 - _D5 and five capacitors _C1 - _C5 . Diode _D1 ~ _D5
are coaxial lead type diodes, each having cylindrical body parts 1 to 5, and each body part 1
Lead wires 1a, 1 coaxially led from ~5
b, 2a, 2b, 3a, 3b, 4a, 4b, 5
a, 5b, and an adhesive 6 in the main body parts 1 to 5.
are mutually integrated. In addition, the diode
As is clear from FIGS. 1 and 2, D ₁ to _{D 5} are arranged so that the rectifying directions are alternately reversed, and the main bodies 1 to 5 are arranged in a line in cross-sectional shape.

第１〜第５のコンデンサC₁〜C₅の内、第１及
び第２のコンデンサC₁，C₂は、第１の誘電体磁
器基板７の表面８に電極９，１０を設け、裏面１
１に電極１２を設けることによつて構成されてい
る。第３、第４及び第５のコンデンサC₃，C₄，
C₅は、第２の誘電体磁器基板１３の表面１４に
電極１５，１６を設け、裏面１７に電極１８，１
９を設けることによつて構成されている。即ち、
第１のコンデンサC₁は電極９と１２、第２のコ
ンデンサC₂は電極１０と１２、第３のコンデン
サC₃は電極１５と１８、第４のコンデンサC₄は
電極１５と１９、第５のコンデンサC₅は電極１
６と１９との対向によつて夫々構成されている。 Among the first to fifth capacitors C ₁ to C ₅ , the first and second capacitors C ₁ and C ₂ have electrodes 9 and 10 provided on the front surface 8 of the first dielectric ceramic substrate 7 and
1 and provided with an electrode 12. Third, fourth and fifth capacitors C ₃ , C ₄ ,
_C5 has electrodes 15 and 16 provided on the front surface 14 of the second dielectric ceramic substrate 13, and electrodes 18 and 16 provided on the back surface 17.
9. That is,
The first capacitor C ₁ has electrodes 9 and 12, the second capacitor C ₂ has electrodes 10 and 12, the third capacitor C ₃ has electrodes 15 and 18, the fourth capacitor C ₄ has electrodes 15 and 19, the fifth capacitor C ₅ is electrode 1
6 and 19 facing each other.

リード線１ａは電極９に、リード線１ｂは電極
１５に、リード線２ａは電極１５に、リード線２
ｂは電極１２に、リード線３ａは電極１２に、リ
ード線３ｂは電極１９に、リード線４ａは電極１
９に、リード線４ｂは電極１０に、リード線５ａ
は電極１０に、リード線５ｂは電極１６に夫々半
田（図示せず）によつて結合されている。なお、
リード線１ａ，５ｂは折曲されて端子２０，２１
とされている。また接地共通端子２２は電極１８
に接続されている。 The lead wire 1a is connected to the electrode 9, the lead wire 1b is connected to the electrode 15, the lead wire 2a is connected to the electrode 15, and the lead wire 2
b is connected to electrode 12, lead wire 3a is connected to electrode 12, lead wire 3b is connected to electrode 19, lead wire 4a is connected to electrode 1
9, the lead wire 4b is connected to the electrode 10, and the lead wire 5a is connected to the electrode 10.
is connected to the electrode 10, and the lead wire 5b is connected to the electrode 16 by solder (not shown). In addition,
The lead wires 1a and 5b are bent and connected to terminals 20 and 21.
It is said that In addition, the ground common terminal 22 is connected to the electrode 18
It is connected to the.

第１の誘電体磁器基板７の表面側に３本のリー
ド線１ａ，４ｂ，５ａが配置され、その裏面側に
２本のリード線２ｂ，３ａが配置され、且つ夫々
のリード線１ａ，２ｂ，３ａ，４ｂ，５ａがバネ
性を有して変形されている。このため、基板７は
半田付け前の状態でリード線１ａ，２ｂ，３ａ，
４ｂ，５ａで安定的に挾持される。第２の誘電体
磁器基板１３に於いては、その表面側にリード線
１ｂ，２ａ，５ｂが配置され、裏面側にリード線
３ｂ，４ａが配置され、第１の誘電体磁器基板７
と同様にリード線１ｂ，２ａ，３ｂ，４ａ，５ｂ
によつて挾持されている。従つて、組み立の際
に、各リード線を個々にコンデンサ電極に半田接
着しなくともよい。第１図〜第３図に示す如く、
基板７，１３をリード線１ａ〜５ｂで挾持したも
のを半田浴に浸漬することにより、一度に結合す
ることが出来る。 Three lead wires 1a, 4b, 5a are arranged on the front side of the first dielectric ceramic substrate 7, two lead wires 2b, 3a are arranged on the back side thereof, and each lead wire 1a, 2b , 3a, 4b, and 5a are deformed with spring properties. Therefore, before soldering, the board 7 has lead wires 1a, 2b, 3a,
It is stably held between 4b and 5a. In the second dielectric ceramic substrate 13, lead wires 1b, 2a, 5b are arranged on the front side, lead wires 3b, 4a are arranged on the back side, and the first dielectric ceramic substrate 7
Similarly, lead wires 1b, 2a, 3b, 4a, 5b
is held by. Therefore, during assembly, it is not necessary to individually solder each lead wire to the capacitor electrode. As shown in Figures 1 to 3,
By immersing the substrates 7 and 13 held between the lead wires 1a to 5b in a solder bath, they can be bonded all at once.

半田によるリード線の結合が終了したら、鎖線
２３で示すように絶縁被覆を設ける。これによ
り、第４図に示す回路構成の５倍電圧整流装置が
完成する。 After the lead wires are connected by solder, an insulating coating is provided as shown by the chain line 23. As a result, a five-fold voltage rectifier having the circuit configuration shown in FIG. 4 is completed.

上述から明らかな如く本実施例によれば次の作
用効果が得られる。 As is clear from the above, according to this embodiment, the following effects can be obtained.

(イ) 複数のダイオードD₁〜D₅を接着材６で一体
化し、この一体化されたダイオードブロツクの
左右に導出されるリード線によつて誘電体磁器
基板７，１３を支持する構成であるので、ダイ
オードD₁〜D₅とコンデンサC₁〜C₅との結合が
簡略化される。(a) A plurality of diodes D ₁ to D ₅ are integrated with adhesive 6, and dielectric ceramic substrates 7 and 13 are supported by lead wires led out to the left and right of this integrated diode block. Therefore, the coupling between the diodes D ₁ to _{D 5} and the capacitors C ₁ to _{C 5} is simplified.

(ロ) リード線１ａ〜５ｂのバネを利用して基板
７，１３を支持し、これを半田デツプすること
によりダイオードD₁〜D₅とコンデンサC₁〜C₅
との結合が達成されるので、製作が容易にな
る。(b) By supporting the boards 7 and 13 using the springs of the lead wires 1a to 5b and soldering them, the diodes D ₁ to D ₅ and the capacitors C ₁ to _{C 5} are connected.
This facilitates manufacturing.

(ハ) コンデンサC₁〜C₅が、第１及び第２のコン
デンサC₁，C₂を含む第１のブロツクと、第３
〜第５のコンデンサC₃〜C₅を含む第２のブロ
ツクとから成る２つのブロツクで構成されてい
るので、ダイオードD₁〜D₅に対する結合が容
易になる。(c) The capacitors C ₁ to _{C 5} are connected to a first block including first and second capacitors C ₁ and C ₂ and a third block.
- the second block containing the fifth capacitors _C3 to _C5 , and thus the coupling to the diodes _D1 to _D5 is facilitated.

(ニ) ダイオードD₁〜D₅の相互間の接続を基板７，
１３上の電極１２，１５，１９を利用して行つ
ているので、構成が簡略化されている。(d) The connections between the diodes D ₁ to _{D 5} are connected to the substrate 7,
Since this is carried out using the electrodes 12, 15, and 19 on 13, the configuration is simplified.

(ホ) 端子２０，２１がリード線１ａ，５ｂで構成
されているので、部品点数が低減し、コストの
低減が可能になる。(E) Since the terminals 20 and 21 are composed of the lead wires 1a and 5b, the number of parts is reduced and costs can be reduced.

(ヘ) ２つの基板７，１３に分割されているので、
コンデンサC₁，C₂と、コンデンサC₃〜C₅との
間の浮遊容量が低減され、目標に近い５倍電圧
を得ることが可能になる。(F) Since it is divided into two boards 7 and 13,
The stray capacitance between the capacitors C ₁ and C ₂ and the capacitors C ₃ to _{C 5} is reduced, making it possible to obtain a voltage 5 times closer to the target.

[Brief explanation of the drawing]

第１図は本考案の実施例に係わる５倍電圧整流
装置を示す平面図、第２図は第１図の装置の底面
図、第３図は第１図の装置の正面図、第４図は第
１図の装置の回路図である。 D₁〜D₅……ダイオード、C₁〜C₅……コンデン
サ、１ａ〜５ｂ……リード線、６……接着材、７
……磁器基板、１３……磁器基板。 FIG. 1 is a plan view showing a five-fold voltage rectifier according to an embodiment of the present invention, FIG. 2 is a bottom view of the device shown in FIG. 1, FIG. 3 is a front view of the device shown in FIG. 1, and FIG. 2 is a circuit diagram of the apparatus of FIG. 1; FIG. _D1 to _D5 ...Diode, _C1 to _C5 ...Capacitor, 1a to 5b...Lead wire, 6...Adhesive, 7
...Porcelain board, 13...Porcelain board.

Claims

[Claims for Utility Model Registration] A plurality of diodes D ₁ to _{D 5} and a first and second
a capacitor block, and an insulating coating 23, and the plurality of diodes D ₁ to D ₅ are connected to the main body portions 1 to 1.
5 and a pair of lead wires 1a to 5a, 1b to 5b coaxially led out from the main body parts 1 to 5, respectively, and the first capacitor block has a first dielectric dielectric ceramic substrate 7 and a plurality of lead wires 1a to 5a, 1b to 5b. A plurality of electrodes 9 are formed on the front surface 8 and the back surface 11 of the first dielectric ceramic substrate 7 so as to obtain capacitors C ₁ and C ₂ of
10, 12, and the second capacitor block includes a second dielectric ceramic substrate 13 and a plurality of capacitors C ₃ , C ₄ ,
It consists of a plurality of electrodes 15, 16, 18, 19 formed on the front surface 14 and back surface 17 of the second dielectric ceramic substrate 13 so as to obtain C ₅ , and the plurality of diodes D ₁ to D ₅ body part 1~
5 are juxtaposed and integrated with each other, the plurality of diodes _D1 to _D5 are arranged so that their rectification directions alternately change, and the first capacitor block is connected to the plurality of diodes D1 to D5. ₁ ~ Lead wire 1a on one side of D _{5 ~}
5a is led out, and the second capacitor block is connected to the plurality of diodes.
The lead wires _1a to _5a are arranged on the side from which the lead wires 1b to 5b on the other side of D1 to D5 are led out, and the lead wires _1a to _5a led out to one side of the plurality of diodes D1 to D5 are It is arranged so as to sandwich the first dielectric ceramic substrate 7 with elastic deformation via the electrodes 9, 10, 12 of the first capacitor block, and is the other of the plurality of diodes _D1 to _D5 . The lead wires 1b to 5b led out to the side are connected to the electrodes 15, 16, 18, 19 of the second capacitor block.
A multi-voltage rectifier characterized in that it is arranged so as to sandwich the second dielectric ceramic substrate 13 with elastic deformation.