JPH0228327A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To contrive the characteristic improvement of a reverse operation transistor as the voltage proof of a forward operation transistor is ensured by providing a first bipolar transistor having one specific area in a first conductive type semiconductor substrate and a second bipolar transistor having the other specific area in the semiconductor substrate. CONSTITUTION:A first bipolar transistor having a second conductive type first area, a first conductive type second area and a second conductive type third area successively arranged from the surface thereof are provided in a first conductive semiconductor substrate 1 and a second bipolar transistor having a second conductive type fourth area, a first conductive type fifth area and a second conductive type sixth area successively arranged from the surface side thereof are set in the semiconductor substrate 1. The deepest position in the boundary of the first area and the second area is deeper than that of the fourth area and the boundary is determined by the diffusion position of impurities constituting the first area. Thereby a semiconductor device in which high performance reverse operation transistor is arranged as the performance is maintained in the same substrate as the forward operation transistor can be obtained.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a semiconductor device having a bipolar transistor and a method for manufacturing the same, and particularly relates to a semiconductor device having a forward operating transistor and a reverse operating transistor on the same substrate. This invention relates to a device and its manufacturing method.

[Conventional technology]

A typical example of a conventional bipolar transistor is shown in FIG. Figure 2 (,) shows the cross-sectional view, Figure 2 (b) shows the second
This figure shows the distribution of impurities along line 1-1' in Figure (a). The vertical axis of FIG. 2(b) is the impurity amount logIND−
It represents N^1.

Here, ND is donor density and N^ is acceptor density. Below, I will briefly describe the manufacturing method of the 1 helangister shown in Figure 2.
Each area will be explained. N-type layer 2 on the surface of P-type substrate 1
is formed by impurity diffusion, and an epitaxial layer 3 having a certain degree of N-type impurity is grown thereon. After the element isolation region 4 and the collector extraction layer 5 are formed by diffusion of impurities from the surface, the base layer 6 and the N-type layer 7 are formed by the ion implantation method. The surface is insulated with an oxide film 8, a contact hole is opened, and wiring is performed using an All electrode 9.

A normal bipolar transistor uses an N-type layer 7 near the surface as an emitter and an epitaxial layer 3 deep in the substrate as a collector.

This is referred to as being used for forward operation, but in order to improve the characteristics of this forward operation, it is necessary to form the base layer 6 on the surface side as shallowly as possible. The epitaxial layer 3, which is a low concentration N-type layer, has a collector breakdown voltage (B VCEO, B Vc
ao). That is, the collector breakdown voltage is proportional to the thickness of the lightly doped N-type layer.

The bipolar transistor shown in FIG. 2 has a structure suitable for forward operation, but has an N-type layer 7 as the collector.

This is not a good structure for reverse operation using the epitaxial layer 3 as an emitter. The main characteristic problems are (1) collector breakdown voltage is low because the N-type layer 7, which is the collector, and the base layer 6 are in contact with each other in a high concentration; (2) the concentration of the base layer 6 is the N-type collector, which is the (3) Electrons and holes are accumulated in the epitaxial layer 3, which is a low concentration N-type layer, and the charging/discharging time becomes longer, resulting in significantly worse high frequency characteristics. It is what happens. In particular, problem (3) is serious and will be discussed in detail below, as it is the main factor that has hitherto limited the use of reverse direction operation. FIG. 3 shows the hole density distribution during normal operation for forward direction operation (a) and reverse direction operation (b).

The hatched area represents the amount of accumulated holes. Points A and B correspond to approximately the same density, and it can be seen that the epitaxial layer 3, which is a low concentration N-type layer, increases hole accumulation during reverse direction operation. The cutoff frequency, which represents the high-frequency operation limit of a transistor, is inversely proportional to the amount of accumulated holes, so the cutoff frequency for reverse direction operation is 1/10 of that for forward direction operation.
~1/100 smaller.

The benefits of using transistors in reverse operation are discussed in H.H. Berger et al., I.E.E., Journal of Solid State Circuits, No. 5.
Volume C-7, page 340, 1972 (H, H, Berge
r et al, IEEE J, 5solid-5tat
eCircuits vol, SC-7, P, 34
0.1972) and the integrated injection logic (IIL) circuit with features of high integration and low power consumption as shown in JP-A-61-10
A memory resistant to alpha rays, such as that shown in No. 4655, is known. To improve the characteristics of these integrated circuits, it is necessary to improve the characteristics of reverse operation. Furthermore, these reverse-operation transistors are usually used simultaneously with forward-operation transistors, and it is necessary to improve the reverse-operation characteristics without lowering the withstand voltage of the forward-operation transistors.

FIG. 4 shows one conventional method for improving reverse operation characteristics. A specific example is Watanabe et al., Japanese Journal of Applied Physics Sublument 16-1, p. 143, 1977 (T
, Watanabe at al, JJAP, 16
(1977) Supplement 16-1. p
, 143). Figure 4(a) shows the cross-sectional structure of a reverse operation transistor, and Figure 4(b) shows the cross-sectional structure of a reverse-operation transistor.
The distribution of impurities along ■-■' in a) is shown. Before growing the epitaxial layer 3, an impurity having a large diffusion coefficient, such as phosphorus, is added to the N-type layer 2 of the transistor used in reverse direction operation. Thereafter, the impurities are boiled up by heat treatment during epitaxial growth and after the growth to form a highly doped N-type layer 10. This moves point A toward the surface and reduces the amount of accumulated charge.

Figure 5 shows another conventional method for improving reverse operating characteristics, as described by Hirao et al.
Journal of Applied Physics Supplement 20-1, p. 161, 1981 (T, Hir
ao et al., JJAP, 20 (1981)
Supplement 20-1. p, 161). FIG. 5(a) shows a cross-sectional structure of a reverse operation transistor, and FIG. 5(b) shows an impurity distribution along the line m-m' in FIG. 5(a). Before growing the epitaxial layer 3, a P-type impurity, such as boron, is added to the N-type layer 2 of the transistor used in reverse direction operation. after that,
During and after epitaxial growth, heat treatment is performed to boil up these impurities and form the base layer 11. As a result, the impurity distribution of the forward-operating transistor is shown in Figure 2 (
Create an impurity distribution that is the inverse of b). In this method, it is necessary to form a P-type layer 12 in order to establish a base contact. This is typically done at the same time as forming the base of the forward operating transistor.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, since impurities are added before epitaxial growth, there are problems described below.

(1) Due to the heat treatment during epitaxial growth and when forming the element isolation region 4, the added impurities are diffused and the N-type region 1
0 to the base region 11 become thicker. For this reason, it is not possible to respond to higher speeds due to miniaturization and shallower junctions of transistors.

(2) An auto-doping effect occurs in which impurities added during epitaxial growth escape from the substrate surface and adhere to undesired regions, resulting in changes in the impurity distribution in forward-operating transistors and resistance regions, making their characteristics unstable. Become.

(3) The added impurity spreads laterally, lowering the element isolation breakdown voltage. Alternatively, if an attempt is made to ensure element isolation withstand voltage, the degree of integration will deteriorate.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide a semiconductor device in which a high-performance reverse operation transistor is disposed in the same substrate as a forward operation transistor while maintaining its performance, and a method for manufacturing the same.

[Means to solve the problem]

The above object is as follows: (1) a first region of the second conductivity type, a second region of the first conductivity type, and a third region of the second conductivity type, which are sequentially arranged from the first surface side in a semiconductor substrate of the first conductivity type; and a first bipolar transistor having a fourth region of the second conductivity type, a fifth region of the first conductivity type, and a sixth region of the second conductivity type arranged in order from the surface side in the semiconductor substrate. 2
a bipolar transistor, the deepest position of the boundary between the first region and the second region is deeper than the fourth region, and the boundary is determined by the diffusion position of the impurity constituting the first region. (2) a first region of a second conductivity type, a second region of the first conductivity type, and a second region of the first conductivity type, which are arranged in order from the surface side in a semiconductor substrate of the first conductivity type; A first bipolar transistor having a third region of the conductivity type, and a fourth region of the second conductivity type, a fifth region of the first conductivity type, and a fifth region of the second conductivity type arranged in order from the surface side in the semiconductor substrate. In the method of manufacturing a semiconductor device having a second bipolar transistor having a sixth region, the first region is doped with impurities from the surface, and the deepest position of the boundary between the first region and the second region is added to the first region. This is achieved by at least - of a method of manufacturing a semiconductor device characterized in that the semiconductor device is formed at a position deeper than four regions.

The present invention will be explained using the drawings. FIG. 6(a) is a cross-sectional view of a reverse operation transistor of a semiconductor device according to an embodiment of the present invention, and FIG. 6(b) shows the impurity distribution along IV-IV' in FIG. 6(a). This is what is shown. The transistor shown in FIG. 2 is used as the transistor operated in the forward direction. The transistor used for reverse direction operation is formed by ion implanting the base layer 13 and the N-type layer 14 from the surface with high energy. Therefore, the junction position between the N-type layer 14 and the base layer 13, which is a P-type layer, is formed at a deeper position than in a forward operation transistor. Therefore, the volume of electrons and holes during reverse direction operation can be reduced, and high frequency characteristics can be improved. Furthermore, the impurity concentration of the N-type layer 14 is made lower than that of the N-type layer 7 (FIG. 2) of the forward operation transistor, and by forming the concentration peak position of the P-type impurity of the base layer 13 deep, It is possible to improve the collector breakdown voltage (BVceo, BVCEO) and the earth voltage during operation.

[For production]

In order to clarify these effects, the results of characteristic calculations using computer simulation are shown in FIGS. 7 and 8. The details of the conditions for prototyping the transistor will be described later using the process flow shown in FIG. FIG. 7 is a graph in which the horizontal axis represents the energy of the ion implant forming the base layer 13 of the reverse operation transistor, and the vertical axis represents the reverse cutoff frequency. 150ke V, 3 by Lin
Figure 1 (
Two cases were calculated: one in which the N-type layer 14 of the reverse direction transistor b) was formed, and the other in which it was not formed. The dose of boron was determined so that the common emitter current gain in reverse direction operation was 100. By increasing the energy of the boron implant and forming the base layer 13 deeply, the cutoff frequency increases. This is because point B in FIG. 3(b) approaches point A and the accumulation of holes decreases. The presence of the deeper N-type layer 14 reduces the base width and improves the cutoff frequency. However, ion implantation of boron with high energy has the following limitations. After forming the highly doped N-type layer 2, the epitaxial layer 3 is grown, so due to thickness variations during epitaxial layer growth,
The depth of the N-type layer 2 changes. Therefore, the base layer 13 and N
The concentration at the bonding position of the mold layer 2 changes, and the characteristics vary. Figure 8 shows the common emitter current gain hFE and base-emitter potential VB for boron implant energy.
This is the result of calculating the fluctuation of H.

Assuming that the thickness variation of the epitaxial layer is 6%, ΔhFp/hpE is 2 at boron energy of 180keV.
5%, ΔVBE will be 6 mV. Furthermore, if the energy is increased above this level, the characteristic fluctuations will become significantly large.

As described above, there is an upper limit to the characteristic variation in boron implant energy, and in order to stabilize the characteristics, the peak position of the P-type impurity concentration in the base layer 13 and the N-type layer 2
It is preferable to form it at a position shallower than the boundary. Furthermore, it can be seen from FIG. 7 that in order to improve the reverse cutoff frequency, it is necessary to form the N-type layer 14 deeply.

〔Example〕

An embodiment of the present invention will be described below with reference to FIG. This embodiment uses the sidewall base electrode type structure (SI COS: SMei+al
This is an example in which the present invention is applied to 1Base Contact 5structure). FIG. 1(a) shows a sectional structural diagram of a forward operating transistor, and FIG. 1(b) shows a sectional structural diagram of a reverse operating transistor. Both are made on the same substrate. Figure 1(c) shows the impurity distribution along ■-■' in Figure 1(a), and Figure 1(d) shows the impurity distribution along VI-VI' in Figure 1(b). shows. In this embodiment, the base electrode is made of polycrystalline 5i18 from the substantially vertical sidewall of single crystal Si. The polycrystal 5i18 is insulated from the substrate by an oxide film 16.

In this structure, the emitter base junction and the collector base junction have approximately the same area, so the forward and reverse operations are structurally symmetrical. Therefore, the impurity distribution improvement effect described herein can be clearly achieved.

FIG. 9 shows the manufacturing method of this example.

(a) By oxidizing the surface of the high-resistance P-type substrate 1, S
After depositing the io2 film 20, the SL and N4 films 21 are deposited. In this example, a 30Ω・1 P-type substrate is used,
500 Sio2 membranes 20 total 20400 Si, N4
A film 21 was formed. Thereafter, the Si and N4 films 21 are selectively dry etched using ordinary photolithography technology. By oxidizing the substrate using the 513N4 film 21 as a mask, a total of 4,500 SiO2 films 22 are formed.

(b) S xs N 4 film 21 and thin SiO□ film 2
After removing 0, deposit sb and O3 and apply s to the substrate.
Diffuse element b. At this time, the 5in2 film 22 serves as a mask, and the high concentration N-type layer 2 is formed to a thickness of 2 caps only in all 22 regions of the Si○2 film 22. After this, the SiO2 film was completely removed, and the thickness was 0.7. The epitaxial layer 3 was grown at low pressure. After this, the surface is oxidized to form a 500-layer SiO2 film 23, and then a 1000-layer SiO2 film 25 is deposited over the entire surface.

(c) Using photolithography technology, Sio2 film 25,
The Si3N4 film 24 and the SiO□ film 23 are dry etched. After this, epitaxial layer 3 is formed using the 3-layer film as a mask.
0.4-dry etching almost vertically.

Furthermore, the side walls of the epitaxial layer 3 are coated with 0, l by fluoronitric acid solution.
IIm isotropically wet etched 6(d)Si
After oxidizing the surface and forming a SOO SiO2 film 26, a 1400 513N4 film 27 is deposited on the entire surface. After this, S
The i3N4 film 27 is left only on the side walls. Thereafter, boron is ion-implanted to form a P-type layer 15 for ensuring element isolation breakdown voltage. This method is used, for example, in JP-A-58-3
0155.

(e) Using the 513N4 film 27 on the sidewall as a mask, the surface of the single crystal Si is oxidized to form a 4,500-layer SiO2 oxide film.

After this, the 513N4 film 27 is removed. The SiO2 film is selectively wet-etched using a 26-film type 6 lithography technique only in the portion where the base contact of the transistor is to be made. Thereafter, the side walls of the Si, N4 film 24 are etched and retreated.

(f) Deposit 7000 impurity-free polycrystalline 5i18 over the entire surface. Boron is ion-implanted over the entire surface to make the polycrystalline 5i18 highly concentrated P type. Thereafter, a photoresist 28 is applied to the surface, the photoresist 28 in the vicinity of the convex portion of the polycrystal 511g is removed, and another photoresist 29 is applied to the entire surface to make the surface flat. The photoresist 29 is etched back by dry etching to expose only the surface of the convex portion of the polycrystal 5i18.

(g) Using the photoresist 28 and 29 as a mask, the polycrystal 5i18 on the convex portion is removed by dry etching.

Thereafter, the photoresists 28 and 29 are removed, and the SjO film 25 is removed by wet etching.

(h) Dry etching the polycrystalline 5i18 selectively using photolithography.

(i) Using the SL, N, and film 24 as a mask, the surface of the polycrystal 5i18 is oxidized to form an oxide film 19 of 2,500 layers. At this time, boron diffuses from the polycrystal 5i18 and a P-type head region 30 is formed. After this, 5L3N and the film 24 are removed.

(j) Diffuse phosphorus into the collector extraction layer 5 by a conventional method to make it a high concentration N-type layer. Thereafter, boron is ion-implanted to form a P-type base layer 6 only for the forward operation transistor. In this example, the energy is 20 ke.
B+ ions were implanted at a dose of V and a dose of 7 x 10"cxn-2. After this, boron and phosphorus were ion-implanted only for the reverse operation transistor to form a P-type base layer 13 and an N-type layer 14. In this example, B1 ions were generated at an energy of 180 keV and a dose of 8 x 10"an-", and at an energy of 150 keV and a dose of 3 x
P+ ions were implanted with 1013C111-''.

After this, in order to create the structure shown in Figure 1, 9008010
Perform a minute annealing and deposit the zoooo polycrystalline 5i34. Arsenic 80ke V, 2X101
Ion implantation is performed using G(!11-2), annealing is performed at 950° C. for 20 minutes, and arsenic is diffused from the polycrystalline SL into both forward and reverse transistors to form an N-type layer 7.

This N-type layer 7 acts as an emitter for a forward-direction operating transistor, and is effective in reducing contact resistance for a reverse-direction operating transistor. However, there is no problem even if the N-type layer 7 is not included in the reverse direction operation transistor, and the impurity distribution in this case is as shown in FIG. 6(b). Also, for the same reason, polycrystalline 5i34 is placed on the collector extraction layer 5.
It is not necessary to provide

Thereafter, the structure shown in FIG. 1 is obtained by forming contact holes and wiring.

FIG. 10 shows the measurement results of the reverse cutoff frequency according to this example. The dose of boron implant that determines the base layer 13 of the reverse operation transistor is varied. Figure 11 shows the measurement results of the reverse current gain (grounded emitter) at a boron dose of 8X10” (!m-”).
In the reverse direction, the new station wave number is 5 GHz or more, and the reverse direction current gain is 1.
00 or more was obtained. FIG. 12 shows the dependence of the reverse cutoff frequency on the collector current under this condition.

The conventional value is a measurement result of the forward operation transistor of this example, and shows that the reverse cutoff frequency is about four times higher due to the improvement of the impurity distribution. Additionally, the collector breakdown voltage for reverse operation has been improved from 2v to 4v, and the earth voltage has been improved from 2v to 5V compared to the conventional product.

In addition to the 5ICO8 structure described here, the present invention can be applied to the planar structures shown in FIGS. 2 and 6, and the iso-planar structures shown in FIGS. 13 and 14. In these structures, when viewed in reverse direction operation, the collector base junction is 1/2 to 1/10 smaller than the emitter base junction, making the structure structurally unsuitable for reverse direction operation. For this reason, although it is not possible to obtain the above-mentioned cutoff frequency and current gain, by applying the present invention, it is possible to improve the reverse operation characteristics by 2 to 3 times compared to the conventional one.

Further, in forming the N-type layer 14, elements other than phosphorus mentioned here can be used. Other examples include arsenic at 160
A bonding position between the N-type layer 14 and the base layer 13 is formed at a position 0.4 um from the surface by implanting with keV, 5X10"a++-". In this case, the N-type layer 14
The impurity distribution monotonically decreases in the depth direction as shown in FIG. Other embodiments further include an N-type layer 14 and a base layer 13.
1000mm after arsenic implantation to deepen the bonding position.
Annealing was performed for 20 minutes at °C, and a bond was formed at a position 0.6 - from the surface. In this case, implantation to form the base layer 13 is performed after the heat treatment so that the P-type base layer 13 is not affected by the annealing.

An embodiment of an integrated circuit using the transistor of the present invention is shown in FIG. In this embodiment, a reverse operation transistor is used in the memory cell, and a memory with excellent resistance to alpha rays is constructed. Regarding this memory cell, see Digest of Symposium on BJ Technology, p. 37, 1987 (N, Homm
a et al, Djgest ofSyIIIpo
sium on VLSI Technology,
p, 37.1987). Additionally, forward operating transistors are used in peripheral circuits other than memory cells to increase speed.

FIG. 17 is an embodiment of another integrated circuit in which the emitters of two or more reverse-operating transistors are wired together for use with forward-operating transistors. The emitter, which operates in the opposite direction, is on the substrate side and can be connected through the N-type layer 2, eliminating the need for an element isolation region and increasing the integration density. A specific example of this integrated circuit is given by Hotta et al., Digest of Technical Papers, p. 100 (1
987) (M, Hotta et al, l5SC
CDigest of Technical Paper
S, Ploo (1987)).

In addition, forward operating transistors are used in the analog section,
The present invention can be applied to a linear circuit using an IIL circuit in the logic section.

FIG. 18 shows another embodiment in which a Schottky diode is formed on the collector of the reverse operation transistor described herein. FIG. 18(a) shows the cross-sectional structure, and FIG. 18(b) shows its equivalent circuit. Schottky electrode (metal) 3
A Schottky diode is formed at the interface between 5 and N-type layer 14. In this example, element isolation is formed by Sio film 37 formed by oxidizing Si trenches and polycrystalline 5i 36 filling the trenches. This may be the structure shown in FIG. Figure 19 shows a memory using this embodiment, which allows the memory cells to be significantly reduced, and by using the forward-operating transistors shown in Figure 1(a) in the peripheral circuitry, ultra-high speed and high integration can be achieved. A memory LSI can be realized.

Note that in the embodiments of the present invention, it is clear that N-type and P-type can be used oppositely, or semiconductors other than Si can be used.

〔Effect of the invention〕

According to the present invention, it is possible to improve the characteristics of a reverse operation transistor while ensuring the breakdown voltage of a forward operation transistor. In one embodiment of the present invention, the cutoff frequency is increased from the conventional 1.5 GHz to 5 GH2, and the collector breakdown voltage is increased to 2 V.
The earth voltage improved from 2v to 5v. Reverse-direction transistors are excellent in alpha radiation resistance, high integration, low power consumption, and low-temperature operation, while forward-direction transistors are excellent in high-speed performance and high-voltage operation. A wide range of LSI application fields can be covered by using a high-performance reverse-direction transistor at the same time as a forward-direction transistor.

[Brief explanation of the drawing]

FIG. 1 is a cross-sectional view of forward and reverse operating transistors according to an embodiment of the present invention, and their ■-V' and VI-V
Figure 2 is a cross-sectional view of a conventional transistor and its impurity distribution along r -1'; Figure 3 is a diagram showing the hole distribution during operation; 4 and 5 are a cross-sectional view of a conventional transistor and its impurity distribution, FIG. 6 is a cross-sectional view of a transistor according to another embodiment of the present invention and its impurity distribution, and FIG. 8 is a diagram showing the effects of the present invention, FIG. 9 is a process diagram showing a method of manufacturing the transistor shown in FIG. 1, and FIGS. 10, 11, and 12 are characteristic diagrams of the transistor shown in FIG. 1. 13 and 14 are cross-sectional views of transistors according to still other embodiments of the present invention, FIG. 15 is a diagram showing other impurity distributions, and FIG. 16 is an explanatory diagram of a memory cell using the present invention, ′
$17 Figure is an explanatory diagram of a linear circuit using the present invention, No. 18
19 is a cross-sectional view of an element including a Schottky barrier diode and a reverse transistor, and FIG. 19 is a circuit diagram of a memory cell using FIG. 18. DESCRIPTION OF SYMBOLS 1... P-type substrate 2... N-type layer 3... Epitaxial layer 4... Element isolation region 5... Collector extraction layer 6... Base layer 7... N-type layer 8...・Oxide film 9...M electrode 10...High concentration N type layer 11...Base layer 12...P type layer
13...Base layer 14...N-type layer
15...P type layer 16...Oxide film 17.
...S i O2 film 18 ... polycrystalline 5i19 ... oxide film 20.22.23.25.26.31.33,37
...S LO, film 21.24.27...Si, N,
Film 28.29...Photoresist 30...P type region 3
2.34.36... Polycrystalline 5i 35... Schottky electrode 41... Forward direction operation transistor 42... Reverse direction operation transistor

Claims (1)

[Scope of Claims] 1. A first region of a second conductivity type, a second region of the first conductivity type, and a third region of the second conductivity type, which are arranged sequentially from the surface side in a semiconductor substrate of the first conductivity type. A first bipolar transistor having a region and a fourth region of a second conductivity type, a fifth region of a first conductivity type, and a sixth region of a second conductivity type arranged in order from the surface side in the semiconductor substrate. a second bipolar transistor, the deepest position of the boundary between the first region and the second region is deeper than the fourth region;
A semiconductor device, wherein the boundary is determined by a diffusion position of an impurity constituting the first region. 2. A first semiconductor substrate having a first region of a second conductivity type, a second region of the first conductivity type, and a third region of the second conductivity type arranged sequentially from the surface side in a semiconductor substrate of the first conductivity type. A bipolar transistor and a second bipolar transistor having a fourth region of the second conductivity type, a fifth region of the first conductivity type, and a sixth region of the second conductivity type arranged in order from the surface side in the semiconductor substrate. In the method of manufacturing a semiconductor device, the first region is doped with impurities from the surface, and the deepest position of the boundary between the first region and the second region is formed at a deeper position than the fourth region. A method for manufacturing a featured semiconductor device.