JPH0228252B2 - - Google Patents
Info
- Publication number
- JPH0228252B2 JPH0228252B2 JP58081733A JP8173383A JPH0228252B2 JP H0228252 B2 JPH0228252 B2 JP H0228252B2 JP 58081733 A JP58081733 A JP 58081733A JP 8173383 A JP8173383 A JP 8173383A JP H0228252 B2 JPH0228252 B2 JP H0228252B2
- Authority
- JP
- Japan
- Prior art keywords
- glass
- film
- pbo
- melting point
- manufacturing
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011521 glass Substances 0.000 claims description 60
- 238000000034 method Methods 0.000 claims description 20
- 238000002844 melting Methods 0.000 claims description 18
- 238000004519 manufacturing process Methods 0.000 claims description 13
- 230000008018 melting Effects 0.000 claims description 13
- 238000001962 electrophoresis Methods 0.000 claims description 12
- 239000004065 semiconductor Substances 0.000 claims description 11
- 230000001681 protective effect Effects 0.000 claims description 9
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 6
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 6
- 238000010304 firing Methods 0.000 claims description 4
- 238000000151 deposition Methods 0.000 claims 1
- 230000007547 defect Effects 0.000 description 15
- 239000005360 phosphosilicate glass Substances 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- 239000000843 powder Substances 0.000 description 9
- 239000000758 substrate Substances 0.000 description 8
- XEKOWRVHYACXOJ-UHFFFAOYSA-N Ethyl acetate Chemical compound CCOC(C)=O XEKOWRVHYACXOJ-UHFFFAOYSA-N 0.000 description 6
- 238000005530 etching Methods 0.000 description 5
- 238000005192 partition Methods 0.000 description 5
- 238000002161 passivation Methods 0.000 description 5
- 238000010306 acid treatment Methods 0.000 description 4
- 238000004806 packaging method and process Methods 0.000 description 4
- QTBSBXVTEAMEQO-UHFFFAOYSA-N Acetic acid Chemical compound CC(O)=O QTBSBXVTEAMEQO-UHFFFAOYSA-N 0.000 description 3
- 239000002253 acid Substances 0.000 description 3
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 3
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- 230000002159 abnormal effect Effects 0.000 description 2
- 239000007788 liquid Substances 0.000 description 2
- 238000009527 percussion Methods 0.000 description 2
- -1 H 2 SO 4 Substances 0.000 description 1
- 229910017855 NH 4 F Inorganic materials 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 150000007513 acids Chemical class 0.000 description 1
- 239000000654 additive Substances 0.000 description 1
- 230000000996 additive effect Effects 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 230000002950 deficient Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000004070 electrodeposition Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 230000000873 masking effect Effects 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 238000012536 packaging technology Methods 0.000 description 1
- 239000002245 particle Substances 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02107—Forming insulating materials on a substrate
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Local Oxidation Of Silicon (AREA)
- Formation Of Insulating Films (AREA)
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、半導体装置の製造方法に係り、特に
PbO系低融点ガラスで素子所定部分にパツシベー
シヨンを施したパワートランジスタ等の半導体装
置の製造方法に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a semiconductor device.
This invention relates to a method for manufacturing semiconductor devices such as power transistors in which predetermined portions of the device are passivated with PbO-based low melting point glass.
パワートランジスタ等の半導体装置には低融点
ガラスのパツシベーシヨンが多用されているが、
低融点ガラスパツシベーシヨンの形成には、一般
にガラス粉末を電気泳動法により付着させこれを
焼成するという方法が採用されている。一方低融
点ガラスパツシベーシヨン以外の素子表面は、通
常酸化ケイ素（SiO2）膜によつて保護されてお
り、SiO2膜の上方をリンガラス化したPSG（ホス
ホシリケートガラス）パツシベーシヨン技術が多
用されている。
Low melting point glass passivation is often used in semiconductor devices such as power transistors.
In order to form a low-melting-point glass packaging, a method is generally employed in which glass powder is deposited by electrophoresis and then fired. On the other hand, the surface of the device other than the low-melting-point glass packaging is usually protected by a silicon oxide (SiO 2 ) film, and PSG (phosphosilicate glass) packaging technology, in which the upper part of the SiO 2 film is made into phosphor glass, is often used. has been done.
ところで低融点ガラスパツシベーシヨン用のガ
ラス種類としては、Zn系ガラスとPbO系ガラス
が使用されている。Zn系ガラスパツシベーシヨ
ンは、酸によつて侵され易いので、パツシベーシ
ヨン形成工程以後の製造工程でH2SO4、HCl、
HNO3等の酸処理が行われる場合には、パツシベ
ーシヨン部分をレジストやPSG膜でマスクをし
て酸処理をする必要があり、それだけ工程が繁雑
となつていた。また、マスクにピンホールがあり
完全でない場合には、ピンホールから酸が入り込
み、その結果素子に耐圧不良が多発していた。 By the way, Zn-based glass and PbO-based glass are used as types of glass for low-melting point glass partitions. Since Zn-based glass patties are easily attacked by acids, H 2 SO 4 , HCl,
When acid treatment such as HNO 3 is performed, it is necessary to mask the passivation area with a resist or PSG film before performing the acid treatment, making the process that much more complicated. Furthermore, if the mask had pinholes and was not perfect, acid would enter through the pinholes, resulting in frequent breakdown voltage failures in the device.
一方、PbO系低融点ガラスはZn系ガラスに比
較して酸によつて侵され難く、半導体製造の通常
酸処理工程では特別にマスクをして保護する必要
がないので、工程の短縮及び歩留向上を期待する
ことができるが、PbO系ガラスパツシベーシヨン
には下記のような問題点があり歩留の大幅な向上
は実現されていなかつたのである。 On the other hand, PbO-based low-melting glass is less susceptible to acid attack than Zn-based glass, and does not require special protection with a mask during the normal acid treatment process of semiconductor manufacturing, which shortens the process and improves yield. Although improvements can be expected, PbO-based glass percussion has the following problems, and a significant improvement in yield has not been achieved.
従来、電気泳動法によるPbO系低融点ガラスの
パツシベーシヨンは、第１図ａ〜ｄに示す工程で
行われていた。第１図ａ〜ｄはトランジスタの素
子断面で表されている。
Conventionally, the passivation of PbO-based low melting point glass by electrophoresis has been carried out in the steps shown in FIGS. 1a to 1d. 1A to 1D are cross-sectional views of transistor elements.
第１図ａにおいて、素子１はコレクタN+層１
１、コレクタN-層１２、ベース層１３、エミツ
タ領域１４からなり、その表面にSiO2膜２、
SiO2膜２の最上層にPSG膜３が形成されている。
そして基板はコレクタN-層１２とベース層１３
との間のPN接合に達する溝４が図示のごとくに
掘り込まれた状態で用意される。このようにガラ
スパツシベーシヨンする溝部４以外の素子表面が
SiO2膜２とPSG膜３でマスクした基板を、電気
泳動装置の電極と対向させてガラス粉末をアルコ
ール等の媒体に分散させたガラス液中に沈め、ガ
ラス粉末がプラスに帯電しているときは基板側に
マイナスの電圧を加えることにより、第１図ｂに
示すように、溝部４にガラス粉末４１を泳動付着
させる。このときSiO2膜２、PSG膜３のマスク
にはピンホール等の欠陥が皆無というわけではな
いので、マスク欠陥部分にもボツ状のガラス５が
かならず付着してしまう。その後酢酸エチル等で
リンスして、溝部３以外に付着したガラスボツ５
を洗い流すが、ピンホール中に入つたガラス粉末
まで完全に除去することはできない。このような
状態で、O2雰囲気中800℃前後で数十分間熱処理
をしてガラス粉末を焼成すると、ガラスボツ５中
のPbとPSG膜３中のＰとは異常反応を起こし、
焼成後第２図ｃに図示するように、溝部ガラス４
１をレジスト４２でマスクしガラスボツ５をエツ
チング除去しても、PSG膜３のガラスボツ５が
異常反応した部分３１は十分な絶縁性を保持する
ことができない。その後、第１図ｄのごとく電極
配線６を行つて素子を完成するが、ガラスボツ５
と異常反応３１したPSG膜３は完成した素子に
特性上種々の不良を発生させる。 In FIG. 1a, element 1 has a collector N + layer 1
1. Consists of a collector N - layer 12, a base layer 13, and an emitter region 14, with a SiO 2 film 2 on its surface,
A PSG film 3 is formed on the top layer of the SiO 2 film 2.
And the substrate is collector N - layer 12 and base layer 13
A groove 4 reaching the PN junction between the two is prepared by being dug as shown in the figure. In this way, the surface of the element other than the groove 4 that undergoes glass percussion is
A substrate masked with SiO 2 film 2 and PSG film 3 is placed opposite the electrode of an electrophoresis device and immersed in a glass solution in which glass powder is dispersed in a medium such as alcohol, and when the glass powder is positively charged. By applying a negative voltage to the substrate side, the glass powder 41 is electrophoretically deposited in the groove 4, as shown in FIG. 1b. At this time, since the masks of the SiO 2 film 2 and the PSG film 3 are not completely free of defects such as pinholes, the glass spots 5 are inevitably attached to the defective portions of the masks. After that, rinse with ethyl acetate etc. to remove any glass bottles 5 that have adhered to areas other than the groove 3.
However, it is not possible to completely remove the glass powder that has entered the pinhole. When the glass powder is fired under such conditions by heat treatment at around 800°C for several tens of minutes in an O 2 atmosphere, an abnormal reaction occurs between Pb in the glass bottle 5 and P in the PSG film 3.
After firing, as shown in FIG. 2c, the groove glass 4
Even if the glass pots 5 are removed by etching while masking the PSG film 3 with the resist 42, the portion 31 of the PSG film 3 where the glass pots 5 have reacted abnormally cannot maintain sufficient insulation. Thereafter, as shown in FIG. 1d, the electrode wiring 6 is performed to complete the device.
The PSG film 3 that has undergone an abnormal reaction 31 causes various defects in characteristics in the completed device.
素子不良の例として、第２図素子平面図に示す
ように、エミツタ電極配線６１直下にPSG膜の
異常反応部分３１があると、エミツタ領域１４と
ベース層１３とが導通状態となり、IEBO（VEBO）シ
ヨート不良が発生する。 As an example of a device failure, as shown in the plan view of the device in FIG. 2, if there is an abnormally reactive portion 31 of the PSG film directly under the emitter electrode wiring 61, the emitter region 14 and the base layer 13 become electrically conductive, resulting in I EBO ( V EBO ) A shot defect occurs.
以上のように、従来の電気泳動法によるPbO系
低融点ガラスパツシベーシヨンの形成法では、素
子表面の絶縁膜上にもガラスが付着し、焼成時に
絶縁膜欠陥の発生を避けることができず、その結
果素子にとつてIEBOシヨート不良など、致命的な
不良原因となるという問題点があつた。 As described above, in the conventional electrophoresis method for forming PbO-based low-melting glass partitions, glass also adheres to the insulating film on the element surface, making it possible to avoid defects in the insulating film during firing. First, there was a problem in that this resulted in fatal defects such as IEBO shot defects for the device.
本発明の目的は、半導体素子のPbO系低融点ガ
ラスパツシベーシヨンを形成するにあたり、素子
表面の絶縁膜に欠陥を生ぜしめない半導体装置の
製造方法を提供することである。
An object of the present invention is to provide a method for manufacturing a semiconductor device that does not cause defects in the insulating film on the surface of the device when forming a PbO-based low melting point glass partition for the semiconductor device.
本発明は、電気泳動法によるPbO系低融点ガラ
スパツシベーシヨン形成の場合に生ずる素子表面
の絶縁膜欠陥が、低融点ガラスに含有されるPbO
と絶縁膜に含有されるＰとの反応によるものとの
知見を得てなされたものである。すなわち、本発
明の製造方法は、素子の所定部分に、PbOを含有
する低融点ガラスを電気泳動法により付着させた
後焼成したガラスパツシベーシヨンを有する半導
体装置を製造するにあたり、上記ガラスパツシベ
ーシヨン部分以外の素子表面保護膜の最上層に膜
厚2000Åを越えない窒化ケイ素膜を形成した後
に、上記PbOを含有する低融点ガラスの付着を行
うことを特徴とする。
The present invention aims to eliminate defects in the insulating film on the element surface that occur when forming a PbO-based low melting point glass partition by electrophoresis.
This was made based on the knowledge that this is due to a reaction between the P and P contained in the insulating film. In other words, the manufacturing method of the present invention provides a method for manufacturing a semiconductor device having a glass packaging in which a low-melting glass containing PbO is deposited on a predetermined portion of an element by electrophoresis and then fired. The method is characterized in that after a silicon nitride film with a thickness not exceeding 2000 Å is formed on the top layer of the element surface protection film other than the civation portion, the low melting point glass containing PbO is deposited.
電気泳動法によりガラス粉末を付着させるとき
は、所定部分以外にもガラスボツが付着するが、
本発明方法においては保護膜最上層に窒化ケイ素
膜が形成済みであるので、ガラス融点以上（例え
ば800℃）の焼成時にもガラスに含有される（例
えば50％程度）PbOと保護膜内層に含有されるＰ
との接触がなく異常反応を起こさず、その結果素
子表面保護膜の欠陥が防止できシヨート不良など
の製品の歩留りが改善できる。 When applying glass powder using electrophoresis, glass particles may adhere to areas other than the designated areas.
In the method of the present invention, a silicon nitride film has already been formed on the top layer of the protective film, so even during firing at temperatures above the glass melting point (e.g., 800°C), PbO, which is contained in the glass (for example, about 50%), is contained in the inner layer of the protective film. P to be
As a result, defects in the element surface protection film can be prevented and product yields such as shot defects can be improved.
本発明に適用できる窒化ケイ素膜は低圧CVD
（Chemical Vapor Deposition）法であつてもプ
ラズマCVD法であつてもよいことが確認されて
いる。窒化ケイ素膜の内層にはＰを含有する
PSG膜が形成されていてもよいが、Ｐを含有し
ない保護膜とすることが望ましい。また泳動付着
したガラスボツをリンスする工程、さらに焼成し
たガラスボツをエツチング除去する工程を所望に
より付加することができる。 The silicon nitride film that can be applied to the present invention is produced by low-pressure CVD.
It has been confirmed that either the (Chemical Vapor Deposition) method or the plasma CVD method may be used. The inner layer of the silicon nitride film contains P.
Although a PSG film may be formed, it is preferable to use a protective film that does not contain P. Further, a step of rinsing the glass pots that have migrated thereon and a step of removing the fired glass pots by etching can be added as desired.
以下本発明製造方法の一実施例を第３図ａ〜ｇ
の工程図に従つて説明する。第３図ａ〜ｇにおい
て第１図ａ〜ｄと同一符号で表示した部分は第１
図における部分と同じであるのでその説明を省略
する。
An example of the manufacturing method of the present invention is shown below in Figures 3a to 3g.
This will be explained according to the process diagram. In Figures 3a to 3g, parts indicated by the same symbols as in Figures 1a to d are
Since the parts are the same as those in the figure, their explanation will be omitted.
第３図ａにおいて、ベース層１３、SiO2膜２
およびエミツタ領域１４を形成済みのトランジス
タ１が用意される。 In FIG. 3a, the base layer 13, the SiO 2 film 2
A transistor 1 with an emitter region 14 already formed is prepared.
第３図ｂにおいて、トランジスタ１の表面全体
にSi3N4膜７を低圧CVD（LP−CVD）法で1500〜
2000Åの膜厚で均一に形成する。 In Fig. 3b, a Si 3 N 4 film 7 is deposited over the entire surface of the transistor 1 using a low pressure CVD (LP-CVD) method.
Form a uniform film with a thickness of 2000 Å.
次に第３図ｃにおいて、コレクタN-層１２と
ベース層１３間のPN接合をガラスパツシベーシ
ヨンするために、先ず溝部４のSi3N4膜７とSiO2
２の一部をプラズマエツチング又はリン酸煮沸・
NH4Fエツチングにより除去する。この場合溝部
４以外の部分はレジストでマスクしておく。 Next, in FIG. 3c, in order to glass bond the PN junction between the collector N - layer 12 and the base layer 13, the Si 3 N 4 film 7 in the groove 4 and the SiO 2
A part of 2 is plasma etched or boiled in phosphoric acid.
Remove by NH 4 F etching. In this case, portions other than the groove portion 4 are masked with resist.
次に第３図ｄにおいて、基板１はHF：HAc
（酢酸）：HNO3：＝１：２：３のエツチング液等
によりコレクタベース接合に達する溝部４を形成
する。 Next, in FIG. 3d, the substrate 1 is HF:HAc
A groove 4 reaching the collector-base junction is formed using an etching solution of (acetic acid):HNO 3 :=1:2:3.
次に第３図ｅにおいて、例えばPbOガラス100
ｇ、アルコール600c.c.、泳動浴用添加液20c.c.を混
合して十分均一にした電気泳動装置の電着液中に
基板を沈め、泳動装置の電極と基板との間に
100Vの電圧を２分間印加し、溝部４へガラス粉
末４１を付着させる。付着させた基板は酢酸エチ
ル等のリンス液でリンスし、溝部４以外に付着し
たガラス粉末を洗い流す。しかし完全に洗浄する
ことはできず、素子表面にはガラスボツ５がかな
らず残る。そしてO2雰囲気中800℃で30分間ガラ
スの焼成を行う。 Next, in Figure 3e, for example, PbO glass 100
Submerge the substrate in the electrodeposition solution of the electrophoresis device, which has been made sufficiently uniform by mixing 600 c.c. of alcohol, and 20 c.c. of the additive liquid for the electrophoresis device, and place it between the electrode of the electrophoresis device and the substrate.
A voltage of 100 V is applied for 2 minutes to adhere the glass powder 41 to the groove 4. The adhered substrate is rinsed with a rinsing liquid such as ethyl acetate to wash away glass powder adhered to areas other than the grooves 4. However, it cannot be completely cleaned, and glass pots 5 always remain on the surface of the element. Then, the glass is fired at 800 °C for 30 minutes in an O2 atmosphere.
次に第３図ｆにおいて、焼成した溝部ガラス４
１の表面をレジスト４２で保護し、HF：HCl＝
１：９のエツチング液に基板を浸漬し、ガラスボ
ツ５をエツチング除去する。除去したあとの
Si3N4膜７には欠陥がみられなかつた。 Next, in FIG. 3 f, the fired groove glass 4
The surface of 1 was protected with resist 42, and HF:HCl=
The substrate is immersed in a 1:9 etching solution, and the glass pots 5 are etched away. after removing
No defects were observed in the Si 3 N 4 film 7.
次に第３図ｇにおいて周知の方法により電極穴
をあけ、電極６を形成し、PbO系低融点ガラスパ
ツシベーシヨンのパワートランジスタのペレツト
が完成する。 Next, as shown in FIG. 3g, electrode holes are made by a well-known method to form electrodes 6, thereby completing a power transistor pellet made of PbO-based low melting point glass packaging.
本発明の製造方法によれば、素子表面の保護膜
最上層に窒化ケイ素膜を形成した後に、電気泳動
法によりPbOを含有する低融点ガラスを付着させ
次いで焼成するから、保護膜がPbOと異常反応す
ることがなく、その結果シヨート不良などの製品
特性不良を生じない。そのため、PbO系低融点ガ
ラスパツシベーシヨンの本来の利点（すなわちパ
ツシベーシヨン形成後の酸処理工程において低融
点ガラスをマスクして保護する必要がない）をも
ち、半導体装置製造工程の短縮及び歩留りの向上
が実現される。
According to the manufacturing method of the present invention, after forming a silicon nitride film on the top layer of the protective film on the element surface, low-melting glass containing PbO is attached by electrophoresis and then baked, so that the protective film is abnormally contaminated with PbO. There is no reaction, and as a result, there are no defects in product characteristics such as shot defects. Therefore, it has the inherent advantage of PbO-based low melting point glass passivation (that is, there is no need to mask and protect the low melting point glass in the acid treatment process after forming the passivation), shortens the semiconductor device manufacturing process, and improves yield. Improvements are realized.
第１図ａ〜ｄは従来のPbO系ガラスパツシベー
シヨン形成工程を説明するための素子断面図、第
２図は第１図ａ〜ｄの工程で製造された素子の製
品不良を説明するための素子平面図、第３図ａ〜
ｇは本発明製造方法の工程を説明するための素子
断面図である。
１……素子、２……保護膜（SiO2膜）、３……
保護膜（PSG膜）、３１……保護膜欠陥、４……
溝部、４１……PbO系低融点ガラス、５……ガラ
スボツ、６，６１……電極配線、７……Si3N4
膜。
Figures 1 a to d are cross-sectional views of the device to explain the conventional PbO-based glass partition formation process, and Figure 2 illustrates product defects of the element manufactured by the process of Figures 1 a to d. Element plan view for Figure 3 a~
g is a cross-sectional view of an element for explaining the steps of the manufacturing method of the present invention. 1...Element, 2...Protective film (SiO 2 film), 3...
Protective film (PSG film), 31... Protective film defect, 4...
Groove, 41... PbO-based low melting point glass, 5... Glass pot, 6, 61... Electrode wiring, 7... Si 3 N 4
film.
Claims (1)
ラスを電気泳動法により付着させた後焼成したガ
ラスパツシベーシヨンを有する半導体装置を製造
するにあたり、上記ガラスパツシベーシヨン部分
以外の素子表面保護膜の最上層に膜厚2000Åを超
えない窒化ケイ素膜を形成した後に、上記PbOを
含有する低融点ガラスの付着を行うことを特徴と
する半導体装置の製造方法。1. When manufacturing a semiconductor device having a glass patency, which is obtained by attaching a low melting point glass containing PbO to a predetermined portion of the device by electrophoresis and then firing it, the surface of the device other than the glass patties is 1. A method for manufacturing a semiconductor device, comprising forming a silicon nitride film with a thickness not exceeding 2000 Å as the uppermost layer of a protective film, and then depositing the low melting point glass containing PbO.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58081733A JPS59208729A (en) | 1983-05-12 | 1983-05-12 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP58081733A JPS59208729A (en) | 1983-05-12 | 1983-05-12 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS59208729A JPS59208729A (en) | 1984-11-27 |
| JPH0228252B2 true JPH0228252B2 (en) | 1990-06-22 |
Family
ID=13754623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP58081733A Granted JPS59208729A (en) | 1983-05-12 | 1983-05-12 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS59208729A (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5453395A (en) * | 1994-03-21 | 1995-09-26 | United Microelectronics Corp. | Isolation technology using liquid phase deposition |
| US5445989A (en) * | 1994-08-23 | 1995-08-29 | United Microelectronics Corp. | Method of forming device isolation regions |
| CN1302523C (en) * | 2004-12-21 | 2007-02-28 | 天津中环半导体股份有限公司 | Glass deactivating forming process for table top rectifier |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632735A (en) * | 1979-08-27 | 1981-04-02 | Toshiba Corp | Manufacture of mesa type semiconductor device |
-
1983
- 1983-05-12 JP JP58081733A patent/JPS59208729A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5632735A (en) * | 1979-08-27 | 1981-04-02 | Toshiba Corp | Manufacture of mesa type semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS59208729A (en) | 1984-11-27 |
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