JPS6081833A - Semiconductor device - Google Patents

Abstract

PURPOSE:To flatten the step difference part only of the surface of a semiconductor making it feasible to form a highly reliable wiring by a method wherein silicon oxide films respectively containing specific quantity of phosphorus and boron are formed on the step difference part only of insulating films. CONSTITUTION:Silicon oxide films respectively containing 1-8wt% of phosphorus and boron are formed into step difference part only of insulating films. For example, a semiconductor element comprising field oxide films 22, a gate oxide film 23, a polysilicon gate 24 and N type impurity regions 25 is formed on a P type semiconductor substrate 21 and then PSG films 26 are formed as interlayer insulating films to form a large step difference part on the surface. This surface is coated with silicon compound solution containing respectively 4wt% of phosphorus and boron and baked to form a BPSG film 27 and then the BPSG films 28 other than the BPSG film 27 formed in the step difference part may be removed by means of e.g. plasma etching process.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field to which the Invention Pertains] The present invention relates to a semiconductor device, and particularly to a semiconductor device in which a semiconductor surface has a reduced level difference.

[Prior art]

BACKGROUND ART As semiconductor elements become smaller and more densely packed, steep steps are occurring on semiconductor surfaces due to oxidation isolation films, wiring, protective films, and the like. This step difference causes incomplete exposure of the photoresist, making it difficult to form a fine pattern, and also causes problems such as chemicals remaining in the step portion. In particular, when forming wiring such as KA on an insulating film with a large step, the wire may break at the step, or even if it does not break, the wiring may be incompletely formed, causing trouble during the operation of the semiconductor device and reducing reliability. This was the cause of the decline.

As a countermeasure against this, generally speaking, as shown in FIG.
After covering the insulating film 3 with an insulating film 3, a solution containing phosphorus and a silicon compound was applied to the surface of the insulating film 3 and baked to form a silicon compound.

However, in this method of forming the silicon oxide film 4 by applying and baking a silicon compound solution, the coating state of the stepped portions is poor, and the coating solution does not penetrate into the grooves where the constricted portions 5 are formed, for example. Therefore, a cavity is formed. Furthermore, even if the coating liquid were to enter the groove A, the silicon oxide film formed would be thick and the firing would be incomplete.
A silicon oxide film having a high etching rate is formed, and when an opening is formed in a later process, it is easily etched, resulting in a cavity in the trench A. Furthermore, this silicon oxide film 4 shrinks as it is fired, and stress accumulates within the film, so that cracks occur particularly in the thick portions A and B of the silicon oxide film 4. The occurrence of cracks increases as the silicon oxide film 4 becomes thicker, so it is extremely difficult to thicken the silicon oxide film and flatten it so that it is suitable for forming A7 wiring on the semiconductor surface.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device having a silicon oxide film, which can eliminate the above-mentioned drawbacks, fill only the stepped portions of the semiconductor surface and flatten it, and form highly reliable wiring.

[Structure of the invention]

The semiconductor device of the present invention includes a semiconductor element formed on a semiconductor substrate and an insulating film formed on the surface of the semiconductor element, in which phosphorus and boron are each added from 1 to 1.
A silicon oxide film containing 8 wt % is formed only on the stepped portion of the insulating film to form a 'C' structure.

[Explanation of Examples]

The silicon oxide film formed to fill in the steps of the insulating film formed on the semiconductor substrate has a thickness of several percent to lower the flow temperature and to function as a passivation film.
Usually, it contains phosphorus. The concentration of phosphorus is 1wt
% or less, there is a possibility that, for example, sodium ions, which affect properties, may not be sufficiently fixed. It is also known that as the concentration of phosphorus increases, its hygroscopicity increases, and phosphoric acid formed by reacting with moisture dissolves the M electrode and the like. Therefore, when used as a protective film, it generally contains 2 to 3 wt%.
7 to 8 wt when used as an interlayer insulating film.
% of phosphorus (hereinafter referred to as psc+ti) is used. If such a PSG film is formed in the step portion between the insulating film and the insulating film, as described above, the step cannot be filled sufficiently, and the sintering is incomplete, resulting in a P2O film with a high etching rate.

The inventor paid attention to the fact that the etching distance of boric acid glass with HF solution R was small, and conducted various studies on a silicon oxide film containing phosphorus and boron (referred to as BP8G film). As a result, it was possible to obtain a BPSG film that has superior properties in flattening stepped portions compared to conventional PSG films. The characteristics were investigated by mixing boron and phosphorus oxides in a silicon compound solution and coating it on a silicon wafer with a 5-hot striped film with a thickness of about 1° and 5 μm using a spin coating method, and then heating it at 1000°C. This was carried out using a BP8G film formed by baking for 1 to 2 hours.

FIG. 2 is a graph showing the relationship between the boron content and the etching rate with respect to the )-IF solution when the phosphorus concentration is constant (4, □wt%). As shown in FIG. 2, the etch rate decreases as the amount of boron increases.

Therefore, the content of phosphorus and boron must be appropriately combined.
A BPSG film having a more desired etching rate can be formed.

5- In particular, if there is a risk that the baking of the BP8G film applied to the stepped portion may be incomplete, increasing the boron content compared to phosphorus will form a BP8G film with a slower etching rate than K. It is possible to do so.

The flow temperature of BP8G film is 4 to 5 for phosphorus and boron, respectively.
800° C. to 850° C.), which was about 200° C. lower than the conventional P2O film containing 4 to 5 wt % phosphorus. This reduction in flow temperature is very effective in filling steep steps with the flow of the BPSG film.

It is known that the occurrence of cracks when firing a PSG film decreases as the phosphorus content increases, but as mentioned above, as the phosphorus content increases, the hygroscopicity increases. When boron was added to StO! hard instead of phosphorus, the occurrence of cracks decreased as the boron content increased.Therefore, in order to prevent the occurrence of cracks, BP8G The concentration of phosphorus in the membrane should be 3 to 4 wt %, for example, as necessary to fix sodium ions, and the same amount of boron should be included.The concentration of boron should be in the range of 1 to 8 wt %. If it is less than 1 wt %, the effect on suppressing cracks is small, and if it is more than 1 wt %, the etching rate becomes slow, making it impractical.

As described above, the BPSG film containing boron and phosphorus has the advantage of lower flow temperature, less occurrence of cracks, and slower etching rate than the conventional P2O film. However, the BPS formed to fill the level difference
When forming an AJ deposited film on a G film, the steps shown in FIG. 3(a),
A break occurs as shown in (b).

That is, as shown in FIG. 3(a), an uneven structure 2 such as polysilicon or AI wiring formed on a semiconductor substrate 1
When an opening 15 is provided in a semiconductor device in which the step formed on the surface is covered with a PEG film 13 and the number of holes is 4 BPSG films, the BP8G film 14 pores 4 PSG film 13 has a higher resistance to HF solutions. P8 due to high etching speed
The BP8G film 14 forms a canopy just as the pores of the G film 13 are narrow. For this reason, when depositing A, the step coverage of the A1 layer around the holes of the P8G film 13 cannot be formed in a sufficiently good condition, as shown in FIG. 3(b).
A break occurs in the vapor deposited film 16. In order to prevent this step breakage, it is necessary to remove four layers of the BPSG film 14 from the portion where the opening is to be formed. In other words, it is necessary to remove the BP8G film other than the BPSG film filling the 4 step portion of the 14 BPSG films formed on the 1 PEG film.

FIG. 4 is a sectional view of one embodiment of the present invention.

After forming a semiconductor element having a field oxide film 22, a gate oxide film 23, a polysilicon gate 24, and an n-type impurity region 25 on a P-type semiconductor substrate 21, a PSG film 26 is formed as an interlayer insulating film. 0.5～
A large step of about 1.0 μm is formed. A silicon compound solution containing 4wt% each of phosphorus and boron was applied and fired to form a BPSG film 27'' on this surface, and then the BP8G film 27 formed on the stepped portion except for the outside 7 of the BPSG film was formed.
For example, plasma etching is performed until the SG film is removed.

This etching operation flattens the stepped portion. Subsequently, an opening is formed in the PSG film 26 on the n-type impurity region 25 to form an AI wiring 28, and a nitrogen silicon gate M is formed.
O8FFtT is completed.

In a semiconductor device in which a silicon oxide film containing phosphorus and boron is formed only on the step portions, the step portions are flattened without cracking, making it easy to form the KL wiring and improving the semiconductor device. reliability will be improved.

FIG. 5 is a cross-sectional view of another embodiment of the present invention, except for the other P8G29 formed on the BPSG film 27 formed only on the upper level difference part of the PSG film 2 film 6. They are configured almost the same way. The other PSG film 29 is the BP8G film 27
It is formed by applying and baking a silicon compound solution containing phosphorus between the films 7, but since its composition is the same as that of the P8G film 26, the etching speed is also the same, which is particularly inconvenient when providing openings. does not occur. Moreover, other PSG film 2
As shown in FIG. 9, the stepped portion is more flattened than in the case of FIG. 4, so that the reliability of the semiconductor device is further improved.

In the above embodiment, the case of MOSFET was described, but
It is clear that the present invention can be applied to all types of sitting conductor devices having a large step on the surface, such as floating game (FFL) EPROMs and semiconductor devices having multilayer wiring.

(Effects of the Invention) As described above in detail, according to the present invention, it is possible to obtain a semiconductor device having a silicon oxide film that can fill and flatten only the stepped portions of the semiconductor surface and form highly reliable wiring. The effect is great.

[Brief explanation of drawings]

FIG. 1 is a cross-sectional view of a conventional semiconductor device, FIG. 2 is a diagram showing the relationship between boron content and etching rate of a UP8G film used in an embodiment of the present invention, and FIG.
b) is a cross-sectional view of a semiconductor device for explaining step breaks in the aluminum film when the etching rate of the silicon oxide film filling the step portion is slow; FIG. 4 is a cross-sectional view of an embodiment of the present invention;
FIG. 5 is a sectional view of another tenth embodiment of the present invention. 1... Semiconductor substrate, 2... Uneven structure, 3... Insulating film, 4... Silicon oxide film, 5... Constriction, 13... PSG
Film, 14...BP8G film, 15...Opening, 16...AJ vapor deposition film, 21...
pm semiconductor substrate, 22...field oxide film,
23...Gate oxide film, 24...Polysilicon gate, 25...N-type impurity region, 2
6...I'SG film, 27...BPSG
Film, 28... Al wiring, 29... PE
G membrane. 11- Pigeon l Kuhou type #Kanmu and Tsutomori Figure 5 N ≧

Claims (1)

[Claims] In a semiconductor device having a semiconductor element formed on a semiconductor substrate and an insulating film formed on the surface of the semiconductor element, a silicon oxide film containing 1 to 8 wt% each of phosphorus and boron is formed only on the stepped portion of the insulating film. A semiconductor device whose formation is called fF mold.