JPS5897834A - Manufacture of semicondutor device - Google Patents

Manufacture of semicondutor device

Info

Publication number
JPS5897834A
JPS5897834A JP56196460A JP19646081A JPS5897834A JP S5897834 A JPS5897834 A JP S5897834A JP 56196460 A JP56196460 A JP 56196460A JP 19646081 A JP19646081 A JP 19646081A JP S5897834 A JPS5897834 A JP S5897834A
Authority
JP
Japan
Prior art keywords
glass
mask
thereafter
substrate
mesa groove
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56196460A
Other languages
Japanese (ja)
Inventor
Shigeru Honjo
茂 本庄
Tsuneo Atsumi
厚見 恒夫
Kenichi Goto
研一 後藤
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56196460A priority Critical patent/JPS5897834A/en
Publication of JPS5897834A publication Critical patent/JPS5897834A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104Forming layers
    • H01L21/02107Forming insulating materials on a substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

PURPOSE:To eliminate the deposite of glass on an excess part, even when glass passivation is performed, and give no bad influences to later processes by a method wherein an electrodeposition mask is formed by applying a liquid Si compound on the substrate surface, and next heat treatment is performed. CONSTITUTION:Using the N type substrate, a base diffused layer 1 and an emitter diffused layer 2 are formed on the main surface side of the N<->-ON-N<+> substrate. Next, the electrodeposition mask is formed by a spin application method. Thereafter, a heat treatment is performed in N2+O2 atmosphere at 800 deg.C for 30min rsulting in the formation of the electrodepsotion mask 3 1.2mu thick. Succeedingly, the mesa groove part of the electrodeposition mask 3 is removed by a PEP i.e. photoetching process. Then, in a state of resist deposite, a mesa groove is formed by a blade, the crush layer of the mesa groove is removed by a chemical etching, etc., and accordingly a mesa groove 4 is formed. Thereafter, the P-N junction is exposed by exfoliating the resist. Glass powder is electrodeposited and rinced, and thereafter a heat treatment is performed resulting in glass calcination. Thereafter, an electrode formation, etc. are performed, and thus the pellet of a glass passivation power transistor is completed.

Description

【発明の詳細な説明】 本発明は半導体装置の製造法に係り、特にガラスバッシ
ペイシlンパワートランジスタの製造法に関する。
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a glass-bashy power transistor.

との種トランジスタのβラス付着法としては一般に電気
泳動法が用いられている.これは、ガラスを付着する部
分以外1’ 810m勢の絶縁被膜でマスクした基板を
電極と対向させてガラス粉末をアルコール醇の溶媒に溶
かしたガラス液中に沈め、、ガラス粉末がプラスに帯電
している場合は基板一へiイナスの電圧を加えることに
より基板上の810。
Electrophoresis is generally used as a β-lase attachment method for seed transistors. This is done by placing a substrate masked with a 1'810 m thick insulating film, excluding the part to which the glass is to be attached, facing an electrode, and submerging it in a glass liquid containing glass powder dissolved in an alcoholic solvent, so that the glass powder becomes positively charged. 810 on the substrate by applying a negative voltage to the substrate.

マスクのない部分にガラス粉末を泳動付着させるもので
ある。
Glass powder is electrophoretically deposited on areas where there is no mask.

しかしながら、この電気泳動法によると電着マスタの8
10!膜にビンホール尋があるとその部分にもガラスが
付着することになる。
However, according to this electrophoresis method, 8
10! If there are bottle holes in the membrane, glass will also adhere to those areas.

これと同様のことが810,膜の段差がある場合にも生
じる.第7図はこれを示したもので、基板の主表面側に
ペース拡散層Iおよびエミツタ拡散鳩Jt’形成し,ベ
ースとエミッタとの接合表面には基板の主表面に対し段
差を有する保S膜Jが設けられる(同図体))、との保
験膜Jが設けられた半導体基板の主表面にOVD岬の低
温気相成長により810を等の電着iスタILv形成す
ると保瞳膜3と基板主表面との段差部分で段切れjを生
じる(同図(bり。この状態の基板に、同図(C)、同
図(d)に示すようなメサ陶4形成のための1程の彼に
グラシベイシ■ンを施すと、本来ガラスが付着してはな
らない段差亭の部分にもガラス付着物7が形成される。
A similar thing occurs when there is a step 810 in the membrane. Figure 7 shows this, in which a pace diffusion layer I and an emitter diffusion layer Jt' are formed on the main surface side of the substrate, and the bonding surface between the base and emitter has a step difference with respect to the main surface of the substrate. 810 is electrodeposited on the main surface of the semiconductor substrate on which the protective film J is provided (see the same figure) by low-temperature vapor phase growth of the OVD cape, the pupillary protective film 3 is formed. A step break J occurs at the step part between the main surface of the substrate and the main surface of the substrate (see figure (b). When glass basing is applied to this part, glass deposits 7 are formed even in the part of the stepped roof where glass should not be attached.

このガラス付着物7はメサ崗部カラスに比べ付着!0積
が小さく、電界集中が起るためメサ溝部カラスの盛上り
に比べ遥かに高いものとなり100μ前後に運する。
This glass deposit 7 is more attached than the crow on the mesa! Since the zero product is small and electric field concentration occurs, it is much higher than the swell of the crow in the mesa groove, reaching around 100μ.

このようなガラス突起は後に行うPIFマスクアライン
メント工程で間勉となる。つまり、ガラスの高さがカラ
スマスクと基板との空隙長より大であるときはガラスマ
スクを損−してその寿命を短くする原因となっており、
接電な場合は基板が全く動かずマスクアラインメント不
能な基板も発生している。
Such glass protrusions cause trouble in the PIF mask alignment process to be performed later. In other words, if the height of the glass is greater than the gap length between the glass mask and the substrate, it will damage the glass mask and shorten its lifespan.
When connected, the board does not move at all, making mask alignment impossible for some boards.

本溌明は上述の点に鑑みてなされたもので、電着マスク
をスピン塗布法によるマスク剤塗布に続き熱処理を行う
ことによって形成してグラシベイシ冒ンを良好に行い得
る半導体装置の製造法な提供するものである。
The present invention was developed in view of the above-mentioned points, and is a method for manufacturing semiconductor devices that can achieve good glassy cleaning by forming an electrodeposition mask by applying a masking agent using a spin coating method and then performing heat treatment. This is what we provide.

以下第2図を参照して本発明の一実施例を験明する。An embodiment of the present invention will be explained below with reference to FIG.

IJJ図は本発明におけるグラシベイシ謬ン工程を第1
図と対応させて示したものである。
The IJJ diagram shows the glassy basis error process in the present invention as the first
It is shown in correspondence with the figure.

いま例えばN型基板を用いるとしNオンN基板の主表面
側に周知の技術によりペース拡散層lおよびエギッタ拡
散層コを形成する。この段陽で基板表面には/、jμ前
後の段差が形成されている(同図(a) )、次いでス
ピン塗布法により電春マスクを形成する。これには例え
ば810.$%度g、tチの液状シリカな、スピンナを
300Orpmで〃秒間作動させることにより塗布し、
その後yt + O**W!l気中で100℃、30分
間熱処理を行って厚さ1.2μの電着マスクJを形成す
る(同図(b) )、続いてPEPつまり写真食刻技術
により電着マスクJのメサ溝部分を取除く(同図(0)
 ’) 。
For example, assuming that an N-type substrate is used, a pace diffusion layer l and an emitter diffusion layer are formed on the main surface side of the N-on-N substrate by a well-known technique. With this step, a step of about /jμ is formed on the surface of the substrate (FIG. 6(a)). Next, an electrospring mask is formed by spin coating. For example, 810. Liquid silica of $% g, t is applied by operating a spinner at 300 rpm for 〃 seconds,
After that yt + O**W! An electrodeposition mask J having a thickness of 1.2μ is formed by heat treatment at 100°C for 30 minutes in 1 atmosphere (see figure (b)).The mesa grooves of the electrodeposition mask J are then formed using PEP, that is, photolithography. Remove the part ((0) in the same figure)
').

次にレジス)1−付着した状態でブレードによりメサ溝
の形成を行い、メサ溝の破砕層!ケミカルエツチング等
により除去しメサ情事を形成する。
Next, Regis) 1 - Form a mesa groove with a blade in the adhered state, and create a fractured layer of the mesa groove! It is removed by chemical etching etc. to form a mesa.

この稜レジストを剥離しPM接合な無比させる(同一釦
)、そして例えばZnO系ガラス液中で300V、−分
間電圧を印加してガラス粉末を電着し、リンスの發bo
o〜り00℃の炉中で熱処理を行いガラス焼成する。
This ridge resist is peeled off to make a PM bond (same button), and a voltage of 300 V is applied for -minutes in a ZnO-based glass liquid to electrodeposit glass powder, and the rinse process is completed.
The glass is fired by heat treatment in a furnace at 0 to 00°C.

しかる稜、11極形成咎な行いガラスパッシベイシ曹ン
バワートランジスタのペレットが完成する。
After forming 11 electrodes, a pellet of a glass passive bass power transistor is completed.

本発明は上述のように、液状シリコン化合物を基板表面
に塗布し次いで熱処理することによって!着マスクを形
成しているため、ガラスパッシペイシ璽ンを行っても余
分な個所にガラスが付着することがなく、後の工程に悪
影譬を及ぼすことがない、こ9は、エイツタ形成以降熱
処理温度が制限されるため蒸気酸化膜を電着マスクとし
て適用し難点を考慮するとき本発明方法が極めて優れた
ものであることを意味する。
The present invention, as described above, involves applying a liquid silicon compound to the surface of a substrate and then heat-treating it! Because it forms an adhesive mask, even if glass is applied, glass will not adhere to unnecessary areas and will not cause any negative effects on subsequent processes. This means that the method of the present invention is extremely superior when considering the drawbacks of applying a steam oxide film as an electrodeposition mask since the heat treatment temperature is limited.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は従来のガラスバッシペイシ曽ン工程を示す図、
W&コ図は本発明方法における同工程な示す図である。 l・・・ベース拡散層、J・・・エミッタ虻散層、3・
・・保静膜、亭・・・電着マスク、I・・・電着マスク
の段切れ、ト・・メサ溝、γ・・・ガ)ラス付着物。 出願人代理人  猪  股     清躬2 図 3 ↓
Fig. 1 is a diagram showing the conventional glass bathing process.
W&C diagrams are diagrams showing the same steps in the method of the present invention. l...Base diffusion layer, J...Emitter diffusion layer, 3.
...Retentive film, Tei...electrodeposition mask, I...step break in electrodeposition mask, T...mesa groove, γ...glass deposits. Applicant's agent Kiyomi Inomata 2 Figure 3 ↓

Claims (1)

【特許請求の範囲】 1、@状電着マスク剤をスビy1111布法により半導
体基板の主表面に塗布した後熱処理して電着マスクの所
定部分へ大明けする工程と、前記基板に対し前記マスク
l介して電気泳動法によりガラス粉末を付着させて焼成
する工程とをそなえた半導体!jl’の製造法。 コ、特許請求の範aIJ/xj4記載の方法において、
前記液状電着マスク剤はシリコン化合物をアルコールに
溶解してなるもので、ある半導体装置の製造法。
[Claims] 1. A step of applying an @-shaped electrodeposition masking agent to the main surface of a semiconductor substrate by the Subi Y1111 cloth method and then heat-treating it to a predetermined portion of the electrodeposition mask; A semiconductor with a process of attaching glass powder by electrophoresis through a mask and firing it! jl' manufacturing method. In the method described in claim aIJ/xj4,
The liquid electrodeposition masking agent is made by dissolving a silicon compound in alcohol, and is used in a certain semiconductor device manufacturing method.
JP56196460A 1981-12-07 1981-12-07 Manufacture of semicondutor device Pending JPS5897834A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56196460A JPS5897834A (en) 1981-12-07 1981-12-07 Manufacture of semicondutor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56196460A JPS5897834A (en) 1981-12-07 1981-12-07 Manufacture of semicondutor device

Publications (1)

Publication Number Publication Date
JPS5897834A true JPS5897834A (en) 1983-06-10

Family

ID=16358170

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56196460A Pending JPS5897834A (en) 1981-12-07 1981-12-07 Manufacture of semicondutor device

Country Status (1)

Country Link
JP (1) JPS5897834A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112017007406T5 (en) 2017-04-06 2019-12-19 Mitsubishi Electric Corporation SiC epitaxial wafer, method for manufacturing an SiC epitaxial wafer, SiC device and power conversion device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE112017007406T5 (en) 2017-04-06 2019-12-19 Mitsubishi Electric Corporation SiC epitaxial wafer, method for manufacturing an SiC epitaxial wafer, SiC device and power conversion device

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