JPH02277314A - Mos output circuit device - Google Patents

Abstract

PURPOSE:To reduce radiation noise by increasing a time constant of a leading and a trailing of a gate signal given to a MOS transistor(TR) when the cut-off state of the MOS TR is changed to the conductive state. CONSTITUTION:The time constant of the trailing of an output signal of a logic gate circuit 4a is determined by setting the ON-resistance of an N-channel MOS TR to be 42a larger than the ON-resistance of a P-channel MOS TR 41a. Moreover, the time constant of the trailing is increased sufficiently larger than the leading and trailing time constants of an input signal I4 with the effect of charge/discharge of a capacitor C4a. Moreover, the leading time constant of an output signal of a logic gate circuit 4b is increased sufficiently larger than the leading and trailing of the input signal I4. Thus, radiation noise is suppressed lower.

Description

Detailed Description of the Invention [Industrial Field of Application] The present invention is directed to an M-type circuit that is used as an output circuit of a semiconductor integrated circuit in a device such as a receiver that requires a low noise level.
The present invention relates to an OS output circuit device.

(Prior Art) Fig. 10 shows a circuit diagram of a conventional C-MOS output circuit device. In Fig. 10, 10 is a signal input terminal, 11 is a logic gate circuit, and 12 is a source for the voltage Hv. This is a P-channel MOS transistor in the output stage whose terminals are connected. 13 is a channel MOS transistor 12
The drain terminal is connected to the train terminal of the P-channel MOSI transistor I2, the gate terminal is commonly connected to the data terminal of the P-channel MOSI transistor I2, and the source terminal is grounded.
It is an OS transistor. I4 is O3 between P channels
Train terminal of transistor 12 and N-channel M
This is a signal input terminal provided at the connection point of the drain terminal of the OS transistor 13.

C1 represents the capacitance actually connected as a circuit element and the capacitance existing floatingly between the connection point of the drain terminal of the P-channel O3 transistor 12 and the drain terminal of the N-channel MOS transistor 13 and the ground. Combined capacity not shown.

In this C-MOS output circuit device, a binary input signal 11 is input from the signal input terminal 0 to a logic gate circuit 11, and the output signal of the logic gate circuit 11 is used as a gate signal to output a P-channel MOS+- transistor. 12 and N
It is applied to the commonly connected gate terminals of channel MOS transistors 13. As a result, P channel MO5)
Drain terminal of Ranjisk 12 and N-channel MO
An output signal 01 appears at the signal output terminal 14 provided at the connection point of the drain terminal of the S transistor 13.

Now, by applying the input signal 11 from the signal input terminal 10 to the logic gate circuit 11, the logic gate circuit 11
Assuming that the waveform of the output signal of , that is, the gate signal applied to P-channel MOS transistor 12 and N-channel MOS transistor 13 becomes as shown in FIG. M.O.
Since the S gate circuit constitutes an inverter circuit, the waveform of the output signal O1 appearing at the signal output terminal 14 is the inverted waveform of FIG. 11, as shown in FIG. 12.

[Problem to be solved by the invention]

However, in the C-MOS output circuit device shown in FIG. 10, when the output signal 01 changes due to the inversion of the gate signal,
That is, when the on/off states of P-channel MOS+- transistor 12 and N-channel MOS transistor 13 are reversed, the drain terminal of P-channel MOS transistor 12 and the N-channel MOS transistor 1
The capacitor CI present at the connection point of the drain terminal No. 3 is charged or discharged.

At this time, the charging current or discharging current flows steeply through whichever of the P-channel MOS+ transistor 12 and the N-channel MOS transistor 13 is turned on. As a result, a large amount of radiation noise is induced due to the flow of this steep charging/discharging current, which becomes a major problem in devices that require low noise.

On the other hand, the output stage P-channel MOSI transistor 12
If the on-resistance of the N-channel MOS transistor 13 is set high, the P-channel MOS transistor 1
When the second and N-channel MOS transistors 13 are on, the peak values of the charging current and discharging current of the capacitor C1 flowing through the P-channel MOS transistor 12 and the N-channel MOS transistor 13, respectively, can be suppressed to a low level.

However, P channel MOS transistor 12 and N
Setting the on-resistance of the channel MOSI transistor 13 high means that the P-channel MOS transistor 12
This also leads to a decrease in the drive ability of the N-channel MOS transistor 13, which is not preferable.

Therefore, an object of the present invention is to provide a MOS output circuit device that can suppress radiation noise to a low level without reducing the drive ability of a MOS transistor.

[Means to solve the problem]

In the MOS output circuit device of the present invention, a logic gate circuit provided between the gate terminal of an output stage MOS transistor and a signal input terminal is configured as follows. In other words, this logic gate circuit handles M out of the rising and falling edges of the gate signal applied to the MOS transistor.
The time constant for changing the OS l-transistor from the cutoff state to the conduction state is made sufficiently larger than the time constant for the rise and fall of the input signal applied to the signal input terminal.

[For production]

According to the configuration of the present invention, when the input signal is inverted and the MOS transistor in the output stage changes from the cut-off state to the conduction state, the MOS transistor is turned off at the moment when the cut-off state changes to the conduction state and immediately after that. The on-resistance is high, and then gradually decreases over time, and the on-resistance of the MOS transistor in a steady state becomes sufficiently low.

As a result, immediately after the M'O3 transistor becomes conductive, M
When charging or discharging current flows through the OS transistor to the capacitor connected to the MOS+- transistor, the peak value of the charging or discharging current can be suppressed to a low level. Therefore, radiation noise due to charging current or discharging current flowing through the MOS transistor can be suppressed to a sufficiently low level.

Moreover, if a certain amount of time has passed after the reversal of the human signal,
The output signal of the logic gate circuit is also stable, and in this stable state, the on-resistance of the MOS transistor is sufficiently low, so that a sufficient drive capability of the MOS transistor in the output stage can be ensured.

Increasing the time constant of the rise or fall of a gate signal applied to a MOS transistor can be achieved by setting a large on-resistance of the MOSI transistor when the logic gate circuit is composed of, for example, a MOS transistor.

This is because when the on-resistance of the MOS transistor in the logic gate circuit is increased, it takes time to charge and discharge the capacitor connected to the MOS+- transistor, which delays the rise or fall of the output signal of the logic gate circuit. It is.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit diagram of a C-MOS output circuit device according to an embodiment of the present invention. In FIG. 1, 40 is a signal input terminal, and 4a and 4b are logic gate circuits each having a C-MOS gate circuit configuration and forming an inverter for signal inversion.

41a is a P-channel O3 transistor whose source terminal is connected to the power supply VDD. 42a has a drain terminal connected to the drain terminal of the P-channel MOS transistor 41a, and the P-channel MOS transistor 41
This is an N-channel MOS transistor whose gate terminal is commonly connected to the gate terminal of a, and whose source terminal is grounded.

Between these P-channel O3 transistors 41a and N
The channel MOS transistor 42a constitutes the logic gate circuit 4a. In this case, by setting the on-resistance of the N-channel MOS + - transistor 42a larger than the on-resistance of the P-channel inter-O3 transistor 41a, the fall of the output signal of the logic gate circuit 4a (the P-channel MOS transistor 43 is turned on from the cut-off state). The time constant of the input signal I4 applied to the signal input terminal 4° is made sufficiently larger than the time constant of the rise and fall of the input signal I4 applied to the signal input terminal 4°.

41b is a P-channel MOS transistor whose source terminal is connected to the power supply VDD. 42b is an N-channel MOSI transistor whose drain terminal is connected to the drain terminal of the P-channel O3 transistor 41b, whose gate terminal is commonly connected to the gate terminal of the P-channel O3 transistor 41b, and whose source terminal is grounded. These P-channel inter-O3 transistor 41b and N-channel MOS transistor 42b constitute the logic gate circuit 4b. In this case, by setting the on-resistance of the P-channel inter-O3 transistor 41b to be larger than the on-resistance of the N-channel MOS transistor 42b, the output signal of the logic gate circuit 4b rises (the N-channel MOS transistor 44 changes from the cutoff state to the conduction state). The time constant of the input signal I4 applied to the signal input terminal 40 is made sufficiently larger than the time constant of the rising edge and the falling edge of the input signal I4 applied to the signal input terminal 40.

C4fi is the output terminal of the logic gate circuit 4a, that is, P
C1 is the capacitance existing between the connection point of the drain terminal of the channel MOSI transistor 4.1a and the train terminal of the N-channel MOS transistor 42a and the ground, and C1 is the capacitance existing between the output terminal of the logic gate circuit 4b, that is, the P channel Z , is the capacitance existing between the ground and the connection point of the drain terminal of MOSI transistor 41b and the drain terminal of N-channel MOS transistor 42b. These capacitances C, . . . , C4 each represent a combination of stray capacitances such as wiring capacitances and capacitances actually connected to the circuit.

43 is P of the output stage whose source terminal is connected to the power supply vna.
Channel Mos+ Ranjisk. 44 connects the drain terminal to the drain terminal of the P-channel inter-O3 transistor 43, and connects the P-channel MOS transistor 4
It is an N-channel MOSI-transistor whose gate terminal is commonly connected to the gate terminal of the transistor No. 3 and whose source terminal is grounded. These P channel MOS transistors 43 and N
The channel MOS transistor 44 constitutes a C-MOS gate circuit that functions as an impark for signal inversion.

Reference numeral 45 denotes a signal output terminal provided at the connection point between the drain terminal of the P-channel MOS transistor 43 and the drain terminal of the N-channel MOS transistor 44.

C4 is a capacitance that is a combination of a capacitance actually connected as a circuit element and a floating capacitance between the connection point of the drain terminal of the P-channel MOS transistor 43 and the drain terminal of the N-channel O3 transistor 44 and the ground. shows.

The operation of the C-MOS output circuit device configured as described above will be explained below.

In this C-MOS output circuit device, a binary input signal I4 is input from a signal input terminal 40 to logic gate circuits 4a and 4.
The output signal of the logic gate circuit 4a is applied as a gate signal to the gate terminal of the P-channel MOS transistor 43 in the output stage, and the output signal of the logic gate circuit 4b is applied as a gate signal between the N channels of the output stage. It is applied to the gate terminal of O3 transistor 44.

As a result, the drain terminal of the P-channel MOS+- transistor 43 and the N-channel MOS transistor 44
A signal output terminal 45 provided at the connection point of the drain terminal of
Output signal 04 will appear at .

In this case, the input signal 4 is first applied as a gate signal to the commonly connected gate terminals of the P-channel MOS+ transistor 41a and the N-channel O3 transistor 42a of the logic gate circuit 4a, and simultaneously the P-channel MOS+ transistor 41a of the logic gate circuit 4b. It is applied as a gate signal to the commonly connected gate terminals of transistor 41b and N-channel MOS transistor 42b, and an inverted version of input signal I4 is obtained as the output signal of logic gate circuits 4a and 4b.

By the way, the time constant of the fall of the output signal of the logic gate circuit 4a is determined by the fact that the on-resistance of the N-channel O3 transistor 42a is set larger than the on-resistance of the P-channel MOS transistor 41a, and the influence of charging and discharging of the capacitor C4a. Therefore, the falling time constant of the input signal I4
is sufficiently larger than the rise and fall time constants of . On the other hand, the time constant of the rise of the output signal of the logic gate circuit 4a is approximately the same as the time constant of the rise and fall of the input signal I4.

In addition, the time constant for the rise of the output signal of the logic gate circuit 4b is determined by the fact that the on-resistance of the P-channel MOS transistor 41b is set to be thicker than the on-resistance of the N-channel O3 transistor 42b, and that the charging and discharging of the capacitor cab is Due to this influence, the rising time constant is sufficiently larger than the rising and falling time constants of input signal 4.

On the other hand, the time constant of the fall of the output signal of the logic gate circuit 4b is approximately the same as the time constant of the rise and fall of the human input signal I4.

Here, the operation of the C-MOS output circuit device will be explained in detail with reference to FIGS. 2 to 9.

First, the input signal I4 applied to the signal input terminal 40 changes from zero to ■, as shown in FIG. Consider the case of standing up to -L. If the input signal I4 as shown in FIG. 2 is applied to the logic gate circuit 4a, the logic gate circuit 4a
The output horn signal is from the N-channel O3 transistor 42.
Since the on-resistance of a is set large and the falling time constant is set large, as shown in Figure 3, VIII
The voltage falls from + to zero much later than the rise in Figure 2. Note that in FIG. 3, VTP is the dark value voltage of the P-channel MOS transistor 43.

In response to the gate signal changing as shown in FIG. 3, the resistance value of the P-channel MOS transistor 43, which receives the output signal of the logic gate circuit 4a as a gate signal, increases to infinity as shown in FIG. The on-resistance RPT gradually decreases from (oO) to a sufficiently small on-resistance RPT during steady state.

Therefore, when the P-channel MOS transistor 43 transitions from the cutoff state to the conduction state, the P-channel MOS transistor 43
A charging current flows into the capacitor C4 through the S transistor 43 when the on-resistance of the P-channel MOS1-randisk 43 is larger than the on-resistance RPT in the steady state. Therefore, the waveform of the charging current flowing through the P-channel MOS transistor 43 becomes as shown in FIG. 5, and its peak value I peak is kept sufficiently low. When the charging current to the capacitor C4 has finished flowing sufficiently and the P-channel MOS transistor 43 is in a steady state, the on-resistance of the P-channel MOS transistor 43 has become sufficiently small, so the drive capability is the same as that of the conventional example. You can secure the same amount.

Note that at this time, the input signal ■4 is input to the logic gate circuit 4b.
It is also applied to the N-channel MOS transistor 44 via. As a result, the output signal of the logic gate circuit 4b falls with a fast time constant, and therefore the N-channel Mo3
The +- transistor 44 shifts from the conductive state to the cut-off state without delay.

Next, consider the case where the input signal I4 applied to the signal input terminal 40 falls from VD to zero as shown in FIG. If the input signal I4 as shown in FIG. 6 is applied to the logic gate circuit 4b, the logic gate circuit 4b
The output signal of P channel MOS transistor 41b
Since the on-resistance is set large and the time constant of rising and falling is set large, as shown in Figure 7, the voltage from zero to V
The rise up to DD will be much later than the fall in Fig. 6. Note that in FIG. 3, VTN is the dark value voltage of the N-channel Mo3 transistor 44.

In response to the gate signal changing as shown in FIG. 7, the resistance value of the N-channel Mo3 transistor 44, which receives the output signal of the logic gate circuit 4b as a gate signal, increases to infinity as shown in FIG. The on-resistance RNT gradually decreases from (oo) to a sufficiently small on-resistance RNT in steady state.

Therefore, when the N-channel MOS transistor 44 transitions from the cutoff state to the conduction state, the discharge current flowing into the N-channel MOS transistor 44 from the capacitor C4 is larger than the on-resistance RNT in the steady state. It will flow when it is in a large state. Therefore, the waveform of the charging current flowing through the N-channel MOS transistor 44 becomes as shown in the 9th M, and its peak value 1 pcak' is kept sufficiently low. When the discharge current to the capacitor C4 has finished flowing sufficiently and the N-channel MOS transistor 44 is in a steady state, the N-channel Mo3 transistor 44
Since the on-resistance of is sufficiently small, the drive capacity can be maintained at the same level as the conventional example.

Note that at this time, the input signal I4 is input to the logic gate circuit 4a.
It is also applied to P-channel MOS transistor 43 via. As a result, the output signal of the logic gate circuit 4a falls with a fast time constant, so that the P-channel Mos
The +- run disk 43 shifts from the conductive state to the cut-off state without delay.

In the above embodiment, a C-MOS output circuit device was explained, but a P-MOS output circuit device consisting of only P-channel MOS+- transistors and an N-channel Mo
Even in an N-MOS output circuit device consisting of only 3+- transistors, the C-MOS
The same effect as in the case of the S output circuit device can be obtained.

〔Effect of the invention〕

According to the MOS output circuit device of the present invention, by waveform processing by the logic gate circuit, M out of the rising and falling edges of the gate signal applied to the Mo3+ transistor is
Since the configuration is such that the time constant for changing the OS transistor from a cutoff state to a conduction state is sufficiently large, Mo3
Immediately after the transistor becomes conductive, there is a charging current in the capacitor connected to the MOS transistor through the Mo3+- transistor. The radiation noise caused by the charging current or discharging current flowing through can be suppressed to a sufficiently low level.

Moreover, if a certain amount of time passes after the input signal is inverted,
The output signal of the logic gate circuit is also stable, and in this stable state, the on-resistance of the MOS transistor is sufficiently low, so that a sufficient drive capability of the MOS transistor in the output stage can be ensured.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing the configuration of a C-MOS output circuit device according to an embodiment of the present invention, FIG. 2 is a time chart showing the rising edge of an input signal, and FIG. 3 is a P of the output stage in FIG. Figure 4 is a time chart of the gate signal applied to the gate terminal of the channel MOS transistor.
Figure 5 is a time chart showing changes in the resistance value of the P-channel MOS transistor in the output stage in Figure 1. The figure is a time chart showing the falling part of the input signal, Figure 7 is the time chart I of the gate signal applied to the gate terminal of the N-channel MOSI-transistor in the output stage in Figure 1, and Figure 8 is the time chart of the gate signal I. Figure 9 is a time chart 1 showing changes in the resistance value of the N-channel MOS+- transistor in the output stage in the figure. Figure 10 is a circuit diagram showing the configuration of a conventional C-MOS output circuit device, and Figure 11 is the MOS shown in Figure 10.
FIG. 12 is a time chart of the output signal of the logic gate circuit going to the output circuit device. FIG. 12 is a time chart of the output signal of the MOS output circuit device of FIG. 40... Signal input terminal, 4a, 4b... Logic gate circuit, 43... P channel MOSI-transistor,
44...N-channel MOS transistor, 45...
・Signal output terminal, C4... Capacity diagram 4- diagram

Claims (1)

[Claims] A gate signal provided between an output stage MOS transistor, a gate terminal of the MOS transistor, and a signal input terminal, and changes the MOS transistor from a cutoff state to a conduction state during the rising and falling edges of a gate signal applied to the MOS transistor. a logic gate circuit whose time constant is sufficiently larger than the time constants of rising and falling edges of an input signal applied to the signal input terminal.