JPH079457Y2 - Break-before-make control circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a break-before-make control circuit used in a circuit for generating a channel switching signal of an analog multiplexer, and more specifically, to a break-before-make control circuit. The present invention relates to improvement in area reduction suitable for integrated circuits (ICs).

<Prior Art> When a channel of an analog multiplexer is switched by a select signal (digital signal input in parallel in a multi-bit configuration), the select signal is first decoded, and each of the channel switching switches is turned on by the decode signal. Turn off.

In addition, when switching a switch, make sure that two or more switches are not turned on at the same time, and when you turn on one switch, be sure to turn off the other switch before that.
In other words, it is necessary to control so that the break-before-make will occur.

FIG. 5 shows an example of a conventional break-before-make control circuit for such a purpose. FIG. 6 shows the operation waveform diagram. The output A of the decoder is input to the NAND gate 3 via the inverter 1 and the inverter 2 and directly to the other input terminal of the NAND gate 3. Further, a capacitor 4 is connected between the connection point of the inverters 1 and 2 and the common line.

In such a configuration, when the input signal A changes from LOW to HIGH as shown in FIG. 6, the output of the inverter 1 has a certain time constant because the capacitor 4 is connected to the output of FIG. 6 (b). It changes as shown in. Therefore, the rising of the output C of the inverter 2 is delayed with respect to the input signal A as shown in FIG. As a result, the fall of the output D of the gate 3, which is the NAND of the input signal A and the output C of the inverter 2, causes a delay of t _{off with} respect to the signal A as shown in FIG. The rising edge of the signal D is synchronized with the rising edge of the input signal A.

Therefore, when a certain switch is turned on (when the input signal A is switched to HIGH), it is delayed by t _off after the other switches are turned off (in FIG. 6, after the signal A rises). The signal D becomes active (becomes LOW). This realizes break-before-make.

By the way, in order to realize high-speed switch switching, the inverter has a complementary MOS structure (CMOS structure) using a metal oxide film type field effect transistor (MOSFET) as shown in FIG. That is, the drain of PMOSFET 31 and the drain of NMOSFET 32 are connected, and
A power supply voltage V _DD is applied to the source of 31, and the source of the NMOSFET 32 is connected to the common line. The substrate of the PMOSFET 31 is connected to the source, and the substrate of the NMOSFET 32 is connected to the source.

If you connect both gates in common and add an input signal to them,
An output obtained by inverting the input signal is obtained from the connection point between the drain of the PMOSFET 31 and the drain of the NMOSFET 32.

In this case, the delay when the switch turns on, t _off
To 100 nS (normal delay time for high-speed switch switching), set the capacitance C _{0 of the} capacitor 4 to
With 1.5pF, the inverter size is as follows.

The channel length of PMOSFET 31 is 12 μm, and the channel width is
3.6 μm.

NMOSFET 32 has a channel length of 24 μm and a channel width of
3.6 μm.

<Problems to be solved by the invention> However, the size of the MOSFET and the capacitance of 1.5 pF are very large in a miniaturized CMOS, and there is a problem that the chip size becomes large when integrated into an IC. It was

An object of the present invention is to provide a break-before-make control circuit capable of realizing a circuit that realizes a break-before-make in a smaller chip area than the conventional one, which has been made in view of the above points. Is what you are trying to do.

<Means for Solving the Problems> In order to achieve such an object, the present invention provides a PMOSFET in which a gate receives an input signal, a source is applied with a power supply voltage, and a substrate is connected to the source side. The gate receives the bias signal, and the drain is the PMOSFET.
An NMOSFET connected to the drain of and a source and substrate connected to a common line; a common connection point between the PMOSFET and the NMOSFET and a capacitor connected between the power supply or the common line; and a common connection point between the PMOSFET and the NMOSFET. An inverter that inverts the signal appearing at the NAND gate, a NAND gate that takes the NAND of the output of this inverter and the signal that is input to the gate of the PMOSFET, and a power supply voltage is applied to the drain commonly connected to the gate through a resistor. The source and the substrate are connected to a common line, and the bias circuit is configured to generate a bias signal to be applied to the gate of the NMOSFET from the drain.

<Operation> In the present invention, the delay circuit is composed of the constant current load inverter and the capacitor, and when the signal input to the gate of the PMOSFET becomes active, the output of the break-before-make control circuit is the time determined by the delay circuit. It becomes active only after a delay.

The value of the constant current flowing through the constant current load inverter can be determined by the resistance of the bias circuit and the size of the NMOSFET and the size of the NMOSFET of the constant current source load inverter. Therefore, it is easy to make a small current value. The smaller the current value, the smaller the capacitor value. Therefore, a small chip area can be realized.

<Embodiment> An embodiment of the present invention will be described in detail below with reference to the drawings.
FIG. 1 is a block diagram showing an embodiment of a break-before-make control circuit according to the present invention. In the figure, 11 is
PMOSFETs 12 are NMOSFETs that are cascade-connected to the PMOSFET 11. The power supply voltage V _DD is applied to the source of PMOSFET 11
The source of OSFET12 is connected to the common line. 13
Is a capacitor, which is connected in parallel with the PMOSFET 11. 1
An inverter 4 inverts and outputs a signal appearing at a common connection point of PMOSFET 11 and NMOSFET 12. A NAND gate 15 receives the output of the inverter 14 and an input signal (output signal from a decoder (not shown)), and NANDs the two signals.
The input signal is also input to the gate of PMOSFET 11.

The above-mentioned components are called a break-before-make circuit.

A bias voltage is supplied to the gate of the NMOSFET 12 from a circuit called a bias circuit. Bias circuit is resistor 16 and NMOS
It consists of a series connection circuit of FET17, NMOSFET17
The source is connected to the common line, and the drain to which the gate is connected is supplied with the power supply voltage V _DD via the resistor 16. Drain voltage V _BIAS in such a configuration
(Constant voltage) Break-before-make circuit NMOS
By applying to the gate of the FET 12, a constant current flows through the NMOSFET 12.

The break-before-make control circuit having such a structure is used in the structure shown in FIG. In FIG. 2, the break-before-make control circuits 10a, 10b, having the same configuration,
Decode signals y0 to y7 are applied to the ..., And the switches 41a, 41b ,.

Note that the switch used here requires two signals that are active for turning on and off, respectively.

The operation will be described below with reference to FIG. The select signals (x ₀ , x ₁ , x ₂ ) of the switches 41a, 41b, ... Of the analog multiplexer 40 are decoded by the decoder 20. Since this circuit is an example of an 8-channel analog multiplexer, there are 3 select signals and 8 decode signals (y ₀ ~
y ₇ ). Break-before-make circuits y _{0 to} y ₇
Input to 10a, 10b, ... In the break-before-make circuit 10a, the gate potential is applied from the bias circuit 18 so that the NMOSFET 12a operates as a constant current source. That is, this MOSFET circuit operates as an inverter for a constant current source load. The output of this inverter enters the inverter 14a, and its output becomes the input of the NAND gate 15a. The output y ₀ from the decoder 20 is directly input to the other input of the NAND gate 15a.

The output of the NAND gate 15a is used as a control signal for the analog multiplexer.

Decode signals are also input to the other break-before-make circuits. However, the output of the bias circuit 18 is commonly used for all break-before-make circuits.

Now, assume that the switch select signals (x ₀ , x ₁ , x ₂ ) change, as shown in FIG. here,
Take x ₀ as LOW → HIGH → LOW as an example (x ₁ , x ₂
Is always LOW). The switch to be turned on is in the case of changing from 41a to 41b to 41a.

The decoder output y ₀ changes from HIGH to LOW at the timing of T ₁ . The PMOS 11a is turned on, and the charge of the capacitor 13a is PMOS
It discharges through FET11a (A ₀ waveform). A ₀ is an inverter
The waveform is shaped by 14a (B ₀ waveform). Since the input of the NAND gate 15a is B ₀ and y ₀ , the change of LOW → HIGH of the output Z0 thereof hardly delays from the change of HIGH → LOW of y0 (only the delay of the NAND gate 15a). Therefore, the switch 41a is immediately turned off.

Similarly, at the timing of T ₁ , y ₁ goes from LOW to HIGH. At this time, the PMOSFET 11b is turned off, and A ₁ changes from HIGH to LOW. However, since the capacitor 13b is charged through the NMOSFET 12b operating as a constant current source, the voltage changes slowly (the slope of the change of A ₁ is I _C / C ₁ when the constant current is I _C. C ₁ is the capacity of the capacitor 13b).

The waveform of A ₁ is shaped by the inverter 14b (waveform of B ₁ ). The output Z _{1 of the} NAND gate 15b is t _off due to the change of y ₁ from LOW to HIGH.
Just delayed. Therefore, the switch 41b is turned on after t _off has passed since the switch 41a was turned _off .

The time t _off is determined by the constant current I _C and the value of the capacitor 13b.

The capacitor in the break-before-make circuit may be placed between the output of the constant current load inverter and the common line as shown in FIG.

The size and value of each element in such a break-before-make circuit are as follows.

The channel length of PMOSFET 11 is 1.2 μm, and the channel width is 9 μm.

NMOSFET 12 has a channel length of 5 μm and a channel width of 1
0 μm.

NMOSFET 17 has a channel length of 5 μm and a channel width of 4
0 μm.

The resistance 16 is 65 KΩ.

Capacitor 13 is 0.5pF.

<Effects of the Invention> As described in detail above, the present invention has the following effects.

By setting the value of the constant current source to about 14 μA, the value of the capacitor could be reduced to 0.5 pF (in this case t
_off is almost 100nS).

Also, the MOSFET of the inverter has become smaller.

Area increase due to bias circuit (and capacitor
Considering 3pF), the chip area could be reduced significantly.

[Brief description of drawings]

1 is a block diagram showing an embodiment of a break-before-make control circuit according to the present invention, FIG. 2 is a block diagram showing an example of use of the present invention, and FIG. 3 is a break-before-make circuit of the present invention.
FIG. 4 is a diagram showing an operation waveform of each part for explaining the operation of the make control circuit, FIG. 4 is a diagram showing another embodiment of the present invention, and FIG. 5 is a configuration diagram showing an example of a conventional break-before-make control circuit. FIG. 6 is an operation waveform diagram in the conventional example, and FIG. 7 is a diagram showing a configuration example of an inverter in the conventional break-before-make control circuit. 11,11a, 11b ... PMOSFET, 12,12a, 12b ... NMOSFET, 13,13a, 1
3b ... capacitor, 14,14a, 14b ... inverter, 15,15a, 15b
… Nand gate, 16… resistor, 17… NMOSFET.

Claims (1)

[Scope of utility model registration request] 1. A PMOS in which a gate receives an input signal, a source is applied with a power supply voltage, and a substrate is connected to a source side.
Bias signal is received at the FET and the gate, and the drain is the PMOSFET.
An NMOSFET connected to the drain of the source and the substrate to a common line, a common connection point between the PMOSFET and the NMOSFET and a power supply or a common line, and a common connection point between the PMOSFET and the NMOSFET. An inverter that inverts the signal appearing at the NAND gate, a NAND gate that takes the NAND of the output of this inverter and the signal that is input to the gate of the PMOSFET, and a power supply voltage is applied to the drain commonly connected to the gate through a resistor. The source and substrate are connected to a common line, and it consists of a bias circuit that generates a bias signal from the drain to the gate of the NMOSFET. When the input signal is applied to the gate of the PMOSFET, the switch control becomes break-before-make. Breakbiff characterized in that the signal is obtained from the NAND gate Or make control circuit.