JP2008198033A - Adjusting circuit - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an adjusting circuit for supplying a stable output voltage to a power supply circuit. <P>SOLUTION: The adjusting circuit that is inserted into the front of a power supply circuit of which upper limit of the input voltage is limited is constituted of a voltage control element, a voltage detection means, a capacitor, etc., and, when a high input voltage is input, operates as a voltage limiter. Thereby, when an input voltage is low, a voltage drop is small, and when a high voltage is input, the adjusting circuit operates as a voltage limiter. An increase in the output ripple due to the repetition of the on/off state of the voltage control element can be suppressed by eliminating the rapid repetition of the on/off state of the voltage control element. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

    The present invention relates to an adjustment circuit for stably supplying power from a power supply to a power supply circuit of an electronic device.

  In general, when the voltage from the power supply is supplied to the power supply circuit and the range of the power supply input value of the power supply circuit is limited, when the input voltage is applied to the power supply circuit at a voltage higher than specified, the power supply circuit The circuit may be destroyed. As a countermeasure, the voltage value supplied to the power supply circuit is lowered to a voltage value that can ensure reliability, so that the input voltage value exceeding the maximum voltage input value that can be applied to the power supply circuit is not supplied to the power supply circuit. It is desirable to provide a pre-regulator circuit that is applied to the power supply circuit at a normal voltage value, that is, an adjustment circuit between the power supply and the power supply circuit.

  A conventional preregulator circuit is shown in FIGS.

  The pre-regulator circuit 2 shown in FIG. 2 is provided between the power supply 23 and the power supply circuit 21 and includes a resistor R8, a PNP transistor Q8a, an NPN transistor Q8b, and a control circuit 22. Transistor Q8a and transistor Q8b are Darlington connected. Resistor R8 is connected between the emitter terminal of transistor Q8a and the base terminal of transistor Q8b. The control circuit 22 is grounded and connected in parallel with the resistor R8, that is, connected to the emitter terminal of the transistor Q8a and the base terminal of the transistor Q8b.

  When the input voltage Vin is applied to the preregulator circuit 2 from the power supply 23, a current is conducted to the transistors Q8a and Q8b, and a voltage is applied to the power supply circuit 21. When the input voltage Vin becomes higher than the specified value, the control circuit 22 controls the currents of the transistors Q8a and Q8b, suppresses the output voltage applied to the power supply circuit 21, and lowers the voltage.

  The pre-regulator circuit 2 can cope with a large current, but the difference between the input voltage Vin and the output voltage Vout is the sum of the base-emitter voltage Vbe of the transistor Q8a and the collector-base voltage Vcb of the transistor Q8b. 7v.

  The preregulator circuit 3 of FIG. 3 includes a PNP transistor Q9, a resistor R9, and a control circuit 32 in order to reduce the input / output difference of the preregulator circuit 2 described above. The base terminal of the transistor Q9 and the resistor R9 are connected, the control circuit 32 is grounded, one end is connected to the resistor R9, and the other end is connected to the emitter terminal of the transistor Q9.

  When the input voltage Vin is applied to the preregulator circuit 3 from the power supply 33, a current is conducted to the transistor Q9, and a voltage is applied to the power supply circuit 31. When the input voltage Vin becomes higher than the specified value, the control circuit 32 controls the current of the transistor Q9, suppresses the output voltage applied to the power supply circuit 31, and lowers the voltage.

  In the case of the pre-regulator circuit 3, the input / output voltage difference is determined by the characteristics of the collector-base voltage Vcb and the base current of the transistor Q9. In order to reduce the voltage Vcb, a large base current must be passed. Therefore, heat loss at the resistor R9 becomes a problem.

Therefore, it can be considered that the pre-regulator circuit is changed from the control based on the current causing the loss such as the heat loss to the control based on the voltage. An example of a circuit having a configuration based on such voltage control is disclosed in the prior art of Patent Document 1.
Japanese Patent Laid-Open No. 7-281772 [G05F 1/56, H02M 1/15, 3/28, H03K 17/16]

  In order to more simply describe the semiconductor switch circuit of the prior art, reference is made to the preregulator circuit 4 shown in FIG. In the pre-regulator circuit 4 shown in FIG. 4, the control by the current of the circuit shown in FIG. 2 and FIG. 3 is changed to the control by voltage, and the junction transistor which is the control element used in the pre-regulator circuits 2 and 3 described above. Thus, the field effect transistor (FET) is changed as in the prior art. Further, a P-channel type MOSFET (metal oxide semiconductor field effect transistor) is used in order to make the FET conduct current at a voltage lower than the input voltage.

  Specifically, the pre-regulator circuit 4 includes resistors R10a, R10b, R10c, R10d, a P-channel type MOSFET Q10a (hereinafter referred to as “transistor Q10a”), an npn-type transistor Q10b, and an on / off signal circuit 42. .

  The resistor R10a is connected to the source terminal of the transistor Q10a, and the other end of the resistor R10a is connected to the gate terminal of the transistor Q10a and the resistor R10b. The other end of resistor R10b is connected to the collector terminal of npn-type transistor Q10b. The emitter terminal of the transistor Q10b is grounded, and the base terminal is connected to the resistors R10b and R10c. The other end of the resistor R10b is grounded, and the other end of the resistor R10c is connected to the on / off signal circuit 42.

  Hereinafter, the operation of the pre-regulator circuit 4 will be described.

  Transistor Q10a conducts current when the gate voltage falls below the threshold value, and turns on. Further, the gate voltage value is divided by the resistors R10a and R10b so that the maximum gate voltage value at which the operation is compensated is not exceeded when the maximum voltage of the input voltage Vin is applied.

  When a current is output from the on / off signal circuit 42, the transistor Q10b becomes conductive and turns on. Therefore, current flows through the resistors R10a and R10b, the gate voltage of the transistor Q10a decreases, the transistor Q10a becomes conductive, and is turned on. At this time, the difference between the input voltage Vin and the output voltage Vout is a value obtained by multiplying the resistance in the ON state of the transistor Q10a by the drain current. Therefore, the preregulator circuit 4 with a very small voltage drop can be realized.

  When no current is output from the on / off signal circuit 42, no current flows to the transistor 10b and the transistor 10b is turned off. Therefore, no current flows through the resistors R10a and R10b, the gate voltage of the transistor Q10a rises, no current flows through the transistor Q10a, and the transistor is turned off. In this case, no voltage is supplied to the power supply circuit 41.

  Here, as described above, the preregulator circuit 4 performs control to apply a voltage that does not always exceed the set voltage value to the power supply circuit 41. More specifically, the on / off signal circuit 42 outputs current when the output voltage value does not satisfy the set voltage value, and outputs reverse current when the output voltage value satisfies the set voltage value. In the prior art, the on / off signal circuit 42 is constituted by a Zener diode and an npn transistor.

  The operation of the above configuration will be described. When the input voltage Vin is input from the power supply 43 to the pre-regulator circuit 4 and the current is output from the on / off signal circuit 42, the transistor Q10a is turned on. When the input voltage Vin is increased and the output voltage of the transistor Q10a becomes equal to or higher than the set voltage, a reverse current is output from the on / off signal circuit 42, the transistor Q10b is turned off, and the transistor Q10a is turned off. Then, since the output voltage value does not satisfy the set voltage value, a current is output again from the on / off signal circuit 42, the transistor Q10b is turned on, and the transistor Q10a is turned on.

  Therefore, when the input voltage Vin is amplified, the transistor Q10a repeatedly turns on and off, and as a result, the voltage applied to the power supply circuit 41 becomes unstable.

  The present invention solves the above problem and provides an adjustment circuit that supplies a stable output voltage to a power supply circuit.

The adjustment circuit of the first invention is arranged between an input terminal connected to a power source, an output terminal, an input terminal and an output terminal, a voltage control element for controlling the output terminal voltage, and the output terminal voltage is predetermined. When the output terminal voltage reaches a predetermined level, the voltage drop between the input and output at the voltage control element is larger than when the voltage does not reach the predetermined level. As described above, the control means for controlling the voltage control element is provided.

  According to the adjustment circuit of the first invention, the input voltage input from the power supply is applied to the voltage control element, and the output terminal voltage is controlled by the voltage control element. When the input voltage increases and the output terminal voltage from the voltage control element reaches a predetermined level, the voltage drop at the voltage control element is controlled to be greater than when the output terminal voltage does not reach the predetermined level. The output terminal voltage is a voltage that does not always reach a predetermined level, and a stable output terminal voltage can be output.

  The adjustment circuit of the second invention includes an input terminal connected to a power supply, an output terminal, a field effect transistor having a source and drain terminals connected between the input terminal and the output terminal, and an output terminal connected to the output terminal. A Zener diode that conducts when the voltage reaches a predetermined level, a gate control means that is connected to the gate terminal of the field effect transistor and controls the gate voltage of the gate terminal according to the output of the Zener diode, and is arranged between the gate terminal and ground. And a capacitor having a charge / discharge state switched according to the output of the Zener diode.

  According to the adjustment circuit of the second invention, the input voltage input from the power source is applied to the field effect transistor, and the output terminal voltage is controlled by the field effect transistor. When the output terminal voltage reaches a predetermined level, the Zener diode becomes conductive, the gate voltage is controlled according to the output of the Zener diode, and the capacitor switches between charge and discharge. Therefore, the output terminal voltage is always a voltage that does not reach a predetermined level, and a stable output terminal voltage can be output.

  According to a third aspect of the invention, an adjustment circuit includes an input terminal connected to a power source, an output terminal, a field effect transistor having a source and drain terminals connected between the input terminal and the output terminal, and an output terminal connected to the output terminal. A Zener diode that conducts when the voltage reaches a predetermined level and a voltage dividing point are connected to the gate terminal of the field effect transistor, creating a voltage to be applied between the source and gate of the field effect transistor by dividing the input terminal voltage A voltage dividing resistor arranged between the source and gate and a capacitor arranged between the gate terminal and the ground, and the capacitor is charged when the Zener diode is turned on, and the capacitor is discharged when the Zener diode is turned off. It is characterized by.

  According to the adjustment circuit of the third aspect of the invention, the output terminal voltage does not always reach a predetermined level, and a stable output terminal voltage can be output.

  The preregulator circuit 1 will be described with reference to FIG.

  The preregulator circuit 1 of this embodiment includes a P-channel MOSFET (hereinafter referred to as “transistor Q1”), an npn transistor Q2 whose emitter terminal is grounded, a voltage input terminal T1, and a collector of the transistor Q2. Voltage-dividing resistors R1 and R2 provided between the terminals, one end of which is connected to the gate terminal of the transistor Q1, and the other end of which is a grounded capacitor C1 and a Zener connected to the drain terminal of the transistor Q1. Npn, a diode ZD1, a voltage dividing resistor R6, R7 provided between the cathode terminal of the Zener diode ZD1 and the ground GND, and a voltage dividing point of the voltage dividing resistor R6 is connected to the base terminal and the emitter terminal is grounded Type transistor Q3 and between the voltage input terminal T1 and the collector terminal of transistor Q3. A resistor R5 provided between the base terminal of the transistor Q2 and the ground GND, a resistor R3 provided between the base terminal of the transistor Q2 and the collector terminal of the transistor Q3, and a voltage output terminal T2. The capacitor C2 is provided between the ground GND.

  When the input voltage Vin is applied from the power source Vcc to the preregulator circuit 1, a current flows through the base resistor R3 of the transistor Q2 via the resistor R5, the current is conducted to the transistor Q2, and the transistor is turned on. When the transistor Q2 is turned on, that is, when a current flows through the voltage dividing resistors R1 and R2, the voltage divided by the voltage dividing resistors R1 and R2 is applied to the source-gate voltage Vsg of the transistor Q1, and the current is The transistor Q1 is turned on and turned on.

  Further, the detection voltage at which the current due to the reverse voltage application of the Zener diode ZD1 is conducted is set by an input voltage that compensates for the power supply circuit 11. When the output voltage Vq from the transistor Q1 does not satisfy the detection voltage of the Zener diode ZD1, no current is conducted to the Zener diode ZD1, so the input voltage Vin is increased and the output voltage Vq from the transistor Q1 is increased to the detection voltage. However, a stable output voltage Vout is applied to the power supply circuit 11.

  As a result of increasing the input voltage Vin, when the output voltage Vq of the transistor Q1 reaches the detection voltage, a reverse current flows through the Zener diode ZD1. Then, when the emitter-base voltage Veb of the transistor Q3 exceeds the threshold value for conducting current to the transistor Q3, the transistor Q3 is turned on.

  Then, since a current flows through the collector terminal of the transistor Q3, no current flows through the base terminal of the transistor Q2, and the transistor Q2 is turned off. Then, charging of the capacitor C1 connected to the input terminal T1 via the resistor R1 is started, and the charging voltage of the capacitor C1 is applied to the source-gate voltage Vsg of the transistor Q1.

  Then, the drain-source voltage Vds of the transistor Q1 increases, and the output voltage Vq of the transistor Q1 decreases. Then, the output voltage Vq becomes a voltage less than the detection voltage of the Zener diode ZD1, and the Zener diode ZD1 becomes non-conductive. Then, no collector current flows through the transistor Q3, and the transistor Q3 is turned off.

  When the transistor Q3 is turned off, the base current of the transistor Q2 flows, the transistor Q2 is turned on, and the capacitor C1 starts discharging. The voltage divided by the voltage dividing resistors R1 and R2 is applied to the source-gate voltage Vsg of the transistor Q1. When the output voltage Vq reaches the detection voltage of the Zener diode ZD1, the Zener diode ZD1 is turned on, and the above operation is performed.

  Here, the above-described operation will be described in detail with reference to FIGS. In particular, FIG. 5 shows an operation in a circuit different from the pre-regulator circuit 1 of the present embodiment, and more specifically shows an operation when the capacitor C1 provided in the pre-regulator circuit 1 is removed. The description of the operation of the pre-regulator circuit 1 of the present embodiment, which will be described later, is described in comparison with this.

  FIGS. 5A and 5B show (a) the output voltage Vout output to the power supply circuit 11 and (b) the gate voltage Vgg of the transistor Q1 when the capacitor C1 is not provided. (B) shows (a) the output voltage Vout output to the power supply circuit 11 and (b) the gate voltage Vgg of the transistor Q1 when the capacitor C1 is provided.

  First, the case where the capacitor C1 is not provided will be described with reference to FIGS. 5 (a) and 5 (b). As shown in FIG. 5B, the gate voltage Vgg of the transistor Q1 repeats High and Low. The high state in the gate voltage Vgg is a state caused in the preregulator circuit 1 when the output voltage Vq reaches the detection voltage at which the Zener diode ZD1 becomes conductive, the transistor Q3 is turned on, and the transistor Q2 is turned off. is there. The low state is a state caused by the output voltage Vq being less than the detection voltage at which the Zener diode ZD1 becomes conductive, the transistor Q3 being turned off, and the transistor Q2 being turned on.

  In such an operation, the output voltage Vout becomes unstable as the transistor Q1 repeatedly turns on and off. Therefore, as a countermeasure for preventing an unstable voltage from being output, the capacitor C2 is provided and discharged when the transistor Q1 is in an off state, that is, when the output voltage Vq becomes 0, to compensate for the output voltage Vout. The greater the capacitance of the capacitor C2, the more stable the output voltage Vout. However, if the capacitance of the capacitor C2 is increased, the size of the components also increases, which may increase the size of the entire circuit. Alternatively, when it is desired to store the circuit in a limited space, it is necessary to make the parts as small as possible.

  When the component is reduced, that is, the capacitance of the capacitor C2 is reduced, the ripple of the output voltage Vout increases as shown in FIG. The reason why the ripple of the output voltage Vout increases is that the source-gate voltage Vsg of the transistor Q1 greatly increases and decreases as shown in FIG. As a result, the drain-source voltage Vds depending on the source-gate voltage Vsg also becomes unstable, and the ripple of the output voltage Vout increases.

  Therefore, in this embodiment, the capacitor C1 is provided between the gate terminal of the transistor Q1 and the ground GND.

  Next, a case where the capacitor C1 is provided will be described with reference to FIGS. 6 (a) and 6 (b). As shown in FIG. 6B, the gate voltage Vgg of the transistor Q1 repeats the transition from the level A to the level B and the transition from the level B to the level A. At level A, the output voltage Vq reaches the detection voltage at which the Zener diode ZD1 becomes conductive, the transistor Q3 is turned on, the transistor Q2 is turned off, and charging of the capacitor C1 starts. The state of transition from level A to level B will be described. A state in which the gate voltage Vgg increases as the capacitor C1 is charged, and charging of the capacitor C1 is completed at level B. Therefore, as the gate voltage Vgg increases, that is, as the source-gate voltage Vsg decreases, the output voltage Vq drops. At level B, the output voltage Vq does not reach the detection voltage at which the Zener diode ZD1 becomes conductive. Zener diode ZD1 becomes non-conductive.

  Therefore, at level B, the transistor Q3 is turned off, the transistor Q2 is turned on, and the capacitor C1 starts discharging. The transition state from level B to level A will be described. A state in which the gate voltage Vgg decreases as the capacitor C1 is discharged, and the discharge of the capacitor C1 is completed at the level A, and the source-gate of the transistor Q1 is shown. The voltage divided by the voltage dividing resistors R1 and R2 is applied to the voltage Vsg. If the gate of the transistor Q1 is controlled by the voltage generated by the voltage dividing resistors R1 and R2 through the charge / discharge delay by the capacitor C1 according to the conduction / non-conduction state of the Zener diode ZD1, the capacitor C1 shown in FIG. 5 is provided. The source-gate voltage Vsg of the transistor Q1 does not greatly increase or decrease compared to the case where the transistor Q1 is not.

  As described above, when the source-gate voltage Vsg is stabilized, the drain-source voltage Vds is stabilized. As shown in FIG. 6A, the ripple of the output voltage Vout is reduced, and the stable output voltage Vout is supplied to the power supply circuit. Can be applied.

  Therefore, the pre-regulator circuit 1 of this embodiment is inserted in the front part of the power supply circuit where the upper limit of the input voltage is limited, and when the input voltage is low, it acts as a switch without a voltage drop, and a high voltage is input. Sometimes it can work as a voltage limiter.

  That is, when the input voltage is low, loss loss and drive current loss can be reduced, and when the overvoltage is input, the power supply circuit is not supplied, so there is no possibility of damage to the power supply circuit. Further, the voltage value can be lowered to a voltage value that can ensure reliability, and a stable input voltage can be supplied to the power supply.

  Further, although a capacitor is used as a component used for obtaining a stable output, it can be realized with a small-capacitance capacitor. And overall loss loss can be reduced and power saving can be realized.

  For the sake of easy explanation, the above-described embodiment is described using a P-channel type MOSFET which is a semiconductor switching element that is turned on when the gate voltage Vgg falls below a threshold value. However, the present invention is not limited to this as long as the semiconductor switch operates in the same manner.

It is a circuit diagram which shows the form of the adjustment circuit which is one Example of this invention. It is a circuit diagram which shows an example of the conventional adjustment circuit. It is another circuit diagram which shows an example of the conventional adjustment circuit. It is another circuit diagram which shows an example of the conventional adjustment circuit. It is an illustration figure which shows the relationship between time detected when the capacitor | condenser C1 is not used from the circuit diagram of FIG. 1, and a voltage. (A) shows the waveform of the voltage output to the power supply circuit, and (b) shows the waveform of the voltage of the source-gate voltage Vsg of the transistor Q1. It is an illustration figure which shows the relationship between time detected when using the circuit diagram of FIG. 1, and a voltage. (A) shows the waveform of the voltage output to the power supply circuit, and (b) shows the waveform of the voltage of the source-gate voltage Vsg of the transistor Q1.

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 ... Preregulator circuit R1, R2 ... Voltage-dividing resistor Q1 ... P channel type MOSFET
C1, C2 ... capacitors Q2, Q3 ... npn junction transistor ZD1 ... Zener diode T1 ... input terminal T2 ... output terminal

Claims (3)

An input terminal connected to the power source;
An output terminal;
A voltage control element that is arranged between the input terminal and the output terminal and controls an output terminal voltage;
Voltage detecting means for detecting whether or not the output terminal voltage has reached a predetermined level;
Control means for controlling the voltage control element such that when the output terminal voltage reaches a predetermined level, a voltage drop between the input and output of the voltage control element becomes larger than when the voltage does not reach the predetermined level. , Adjustment circuit. An input terminal connected to the power source;
An output terminal;
A field effect transistor having a source and a drain terminal connected between the input terminal and the output terminal;
A Zener diode connected to the output terminal and conducting when the output terminal voltage reaches a predetermined level;
Gate control means connected to the gate terminal of the field effect transistor and controlling the gate voltage of the gate terminal according to the output of the Zener diode;
An adjustment circuit comprising a capacitor that is arranged between the gate terminal and ground and that switches a charge / discharge state according to an output of the Zener diode. An input terminal connected to the power source;
An output terminal;
A field effect transistor having a source and a drain terminal connected between the input terminal and the output terminal;
A Zener diode connected to the output terminal and conducting when the output terminal voltage reaches a predetermined level;
A voltage dividing point is connected to the gate terminal of the field effect transistor, and a voltage divided between the source and gate for dividing the input terminal voltage to create a voltage to be applied between the source and gate of the field effect transistor. Resistance,
A capacitor disposed between the gate terminal and ground,
An adjustment circuit, wherein the capacitor is charged when the Zener diode is turned on, and the capacitor is discharged when the Zener diode is turned off.