JPH0227729A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce resistance, and to avoid a problem of improper contact by covering the upper and side faces of other upper layer except the contact region with a wiring material. CONSTITUTION:A first wiring material 109 is formed in a structure that the upper and side walls of polycrystalline silicon 109' doped with an N-type impurity 1000-2000Angstrom except part (contact with the wiring material of the upper layer). The material 109 is connected to source, drain 107 through a first contact hole 110 formed at part of a first interlayer insulating oxide film 108. Thus, its resistance is reduced to avoid a problem of improper contact.

Description

DETAILED DESCRIPTION OF THE INVENTION (Industrial Application Field 1) The present invention relates to the structure of a semiconductor device, and more particularly to the structure of wiring.

[Conventional technology l Conventional semiconductor devices, especially SRAM 1' with an integration degree higher than IM bit, are described in Hitachi Review VOL, 7ON No. 1.
(1988-2) IM bit static RAM
A three-layer polycrystalline silicon structure is used as introduced in HM628128. The 1st and 2nd layers are polycide (laminated structure of polycrystalline silicon and silicide), the 1st layer is a gate electrode, word line, wiring, the 2nd layer is a double word line, cell GND wiring, wiring, and the 3rd layer is a layered structure of polycrystalline silicon and silicide. is for high resistance loads.

[Problems to be Solved by the Invention] However, the above-mentioned conventional techniques still have major problems to solve. It is the material selection for the second layer of polycide. The second layer of polycide is desired to have low resistance as a wiring material, and is also desired to be thin from the viewpoint of flatness of the multilayer structure. Titanium silicide is attracting attention as a low-resistance material, but this titanium silicide is easily dissolved in hydrofluoric acid, and the purpose is to remove the natural oxide film on the 5 surface when forming other wiring materials on titanium silicide. It is not possible to perform pre-cleaning with hydrofluoric acid, which causes poor contact. In order to solve this problem, for example, a hydrofluoric acid-resistant silicide such as molybdenum silicide may be used.

Now, in order to obtain low resistance, the film thickness must be increased, which, as mentioned above, is undesirable from the perspective of a multilayer structure.

Therefore, the present invention attempts to solve such problems, and its purpose is to maintain low resistance and,
An object of the present invention is to provide a semiconductor device having a wiring structure that is stable against hydrofluoric acid pre-cleaning.

[Means to solve the problem]

The semiconductor device of the present invention has a polycrystalline silicon wiring, and the polycrystalline silicon is characterized in that its upper surface and side surfaces are covered with titanium silicide except for the contact area with other upper layer wiring materials.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings. FIGS. 1(a) and 1(b) are cross-sectional views of a semiconductor device according to the present invention, in which lot is a P-type silicon substrate,
102 is an oxide film for element isolation, 103 is a gate oxide film, 1
04 is a gate electrode (laminated polycide of polycrystalline silicon 104' and molybdenum silicide 104''), 105 is a low concentration n-type impurity diffusion layer, 106 is an insulating film sidewall, and 107 is a high concentration n-type impurity diffusion layer (source/drain). ), 108 is the first interlayer insulating oxide film. 109 is the first wiring material, and in detail, as shown in FIG. Part of the top surface and sidewalls of the polycrystalline silicon 109'
The structure is covered with titanium silicide 109' except for the contact area with the upper layer wiring material, and the contact hole 110 is formed in a part of the first glabella insulating oxide film 108. Connected to the source/drain 107. Reference numeral 111 denotes high-resistance polycrystalline silicon, which is connected to the first wiring material 109 through a second contact hole 113 provided in a part of the second interlayer insulating oxide film 112.
connected to. Reference numeral 114 denotes a second wiring material, which has a laminated structure of a lower layer titanium nitride l14' and an upper layer A114-, and is continuous with the third glabellar insulating oxide 111115 and a part of the second glabellar insulating oxide film 112. The third glabellar insulating oxide film 115, the second glabellar insulating oxide 111112,
And it is connected to the source and drain 107 through a fourth contact hole 117 formed continuously in a part of the third interlayer insulating oxide film 115.

Next, a method for manufacturing a semiconductor device according to the present invention, particularly a method for forming the first wiring material 109, will be described in detail. After forming the first contact hole 110, 1000-2000 polycrystalline silicon 109 is deposited on the entire surface by chemical vapor deposition.
Then, using the resist pattern as a mask, the oxide film is removed by etching so as to leave a portion of the oxide film (the area in contact with the upper wiring material). Next, an n-type impurity such as arsenic or phosphorus is ion-implanted into the entire surface.
Annealing is performed at 1000°C.

The polycrystalline silicon 109 is etched using a resist pattern.

After removing the resist pattern, 600-1000 pieces of titanium were formed using a sputtering method, and 700-1000 pieces of titanium were formed using a halogen lamp.
By performing annealing at 00-800°C, the titanium reacts only with the top surface and sidewalls of the polycrystalline silicon 109' except for a part (the contact area with the upper layer wiring material), and (a part of the top surface is No reaction occurs due to the presence of an oxide film)
Titanium silicide 109'' is formed. Unreacted titanium is removed by etching with a mixed solution of ammonia and hydrogen peroxide.

Although the present invention has been specifically explained based on the embodiments above, it goes without saying that the present invention is not limited to the above embodiments, and can be modified in various ways without departing from the gist thereof.

[Effects of the Invention] As described above, according to the present invention, resistance can be reduced by the titanium silicide layer provided on the top surface and sidewalls, and connections with other wiring materials can be made using polycrystalline silicon itself. This has the great effect of avoiding the problem of poor contact as in the prior art.

[Brief explanation of the drawing]

FIG. 1 is a sectional view showing the structure of FIGS. 1(a) and 1(b). Semiconductor device of the present invention 101 ・ 102 ・ 103 ・ 104 ・ 104'104'' 105 ・ 106 ・ 107 ・ l O8 ・ 109'109'' 110 ・ ill ・ ... p-type silicon substrate ・ oxide film for element isolation ・・Gate oxide film・Gate electrode・Polycrystalline silicon・Molybdenum silicide・Low concentration n-type impurity diffusion layer・Insulating film sidewall・High concentration n-type impurity diffusion layer (source/drain)・・First Oxide film for interlayer insulation...First wiring material...Polycrystalline silicon...Titanium silicide...First contact hole...Polycrystalline silicon for high resistance 12 ・ l 3 ・ 14 ・ 14'14'' l 5 ・ 16 ・ 17 ・ ・Second interlayer insulation oxide film・Second contact hole・Second wiring material・Titanium nitride・AL・Third eyebrow insulation oxide film・Third contact hole・No. Contact hole 4 Applicant Seiko Epson Co., Ltd. agent Masataka Kamiyanagi (1 other person, patent attorney) Engraving of drawings (no change in content) Procedural amendment (method) Indication of case 1988 Name of patented invention Semiconductor Equipment No. 177907 3゜Relationship with the Amended Person Case Patent Applicant ■ 163 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (236)
Seiko Epson Corporation Representative Director Nakamura
Tsuneya 4, agent 5゜Contact information! 34B-8531 Extensions 300-302 Date of correction order September 27, 1988 Figure

Claims (1)

[Claims] 1. A semiconductor device comprising a polycrystalline silicon wiring, wherein the polycrystalline silicon has a top surface and side surfaces covered with titanium silicide except for a contact area with another upper layer wiring material.