JPH02270047A - Memory bank control system for microprocessor - Google Patents

Abstract

PURPOSE:To attain a writing operation to a TAM area of a memory bank from a ROM area of another memory bank without carrying out a bank switching process of a program by carrying out the writing operation after switching the memory banks when the writing operation is detected by a ROM write detecting circuit. CONSTITUTION:For instance, a microprocessor 1 performs a writing operation in a ROM area of a #1 memory bank 8. In this case, a ROM write detecting circuit 2 detects a ROM write access and a memory bank control circuit 3 changes temporarily a memory bank control signal 6. Thus a #2 memory bank 9 is temporarily selected. Thus a writing operation is carried out to an address equal to that of the ROM area of the bank 8, i.e., a RAM area of the bank 9. As a result, a writing operation is attained to a RAM area of a memory bank from another memory bank without carrying out a bank switching process of a program.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory bank control method for a microprocessor, and particularly to a memory bank control method for a microprocessor in which a microprocessor controls a memory bank having a ROM area and a RAM area. Regarding control method.

[Conventional technology]

Conventionally, in the memory bank control method of this type of microprocessor, when data is transferred between memory banks, a common memory buffer area that can be referenced from either memory bank is provided, and the common memory buffer area is The method used was to write data once to the memory bank, then switch to the memory bank, transfer the processing to the memory bank, and then write data from the common memory buffer area to the target RAM address of the memory bank.

Therefore, without switching memory banks in the program,
R from one memory bank to the other memory bank
The configuration was impossible when writing to the AM area.

[Problem to be solved by the invention]

In the conventional microprocessor memory bank control method described above, it is necessary to provide a common memory buffer area for the purpose of transferring data between memory banks. The disadvantage is that the address space is reduced, and the memory
If the amount of data transferred between banks is large and a large common memory buffer area must be taken, measures such as increasing the number of memory banks will be required.

On the other hand, even if the common memory buffer area is made small and the address space in the memory bank is suppressed from decreasing, the RA in the other memory bank is
Since the configuration is such that it is impossible to write to the M area, if there is a large amount of data transferred between memory banks,
Since it is necessary to frequently switch memory banks in a program, there is a drawback that processing time for switching memory banks increases.

[Means to solve the problem]

The microprocessor memory bank control method of the present invention provides first and second memory banks divided into banks for program read operations processed by the microprocessor.
Each of the banks has a ROM area as a read-only storage area and a RAM area as a read-writable storage area, and the microprocessor has a ROM area in one of the first and second memory banks. A ROM write detection circuit detects a write operation to the area, and when this ROM write detection circuit detects a write operation to the ROM area of one memory bank, it detects a write operation to the ROM area of the other memory bank.
and a memory bank control circuit for controlling the microprocessor to perform a write operation in the RAM area of the bank.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

In FIG. 1, this embodiment includes a microprocessor 1 that executes program processing, a memory bank control circuit 3 connected to the microprocessor 1 via an address bus and a bus control signal line 4, and a data bus 5. #1 memory panchromatic, #2 memory bank 9, address
The ROM write detection circuit 2 is configured to include a ROM write detection circuit 2 connected via a bus and a bus control signal line 4. The memory bank control circuit 3 detects the write operation to the ROM area of the memory bank 9 and sends out the ROM write detection signal 7. When the memory bank control circuit 3 receives the ROM write detection signal 7, the memory bank control circuit 3 outputs the signal # by the memory bank control signal 6. 1 memory bank 8 or #2 memory bank 9.

Next, the operation of this embodiment will be explained.

Normally, the memory bank control circuit 3 outputs the memory bank control signal 6 under the control of the address bus and bus control signal line 4 from the microprocessor 1 and the data busler, and the memory bank control circuit 3 outputs the memory bank control signal 6, 2 memory
Select one of the memory banks in bank 9.

The microprocessor 1 accesses the selected one memory bank by the address bus, bus control signal 4 and data busler.

The ROM write detection circuit 2 monitors the address bus and bus control signal line 4 and the memory bank control signal 6, and when it detects a write access from the microprocessor 1 to the ROM area of the memory bank, it outputs a ROM write detection signal 7. is output to the memory bank control circuit 3.

When the memory bank control circuit 3 receives the ROM write detection signal 7, it temporarily changes the memory bank control signal 6 and controls the memory bank to select the other memory and bank that is not currently selected. Therefore, this write access will be performed to the opposite memory bank.

Figures 2(a) and (b) are #1 in Figure 2, respectively. #
FIG. 2 is a diagram showing an example of an address map of an R, 0M area and an R, AM area of two memory banks.

Next, the operation of this embodiment will be explained based on the address maps shown in FIGS. 2(a> and 2(b)).

#1 memory bank 8 is address 0OOOH~7FFF
H is the ROM area, 80008 to FFFFH are the RAM area, and #2 memory bank 9 is the ROM area and R
The configuration is such that the address of the AM area is swapped with #memory bank 8.

Here, for example, when the microprocessor 1 performs a write operation on the ROM area of #1 memory panchromatic, the ROM write detection circuit 2 detects the ROM area as described above.
M write access is detected and the memory bank control circuit 3 temporarily changes the memory bank control signal 6;
#2 memory bank 9 is temporarily selected.

Therefore, writing is performed to the same address as the ROM area of #memory bank 8, that is, the RAM area of #2 memory bank 9.

Conversely, when the microprocessor 1 performs a write operation on the ROM area of the #2 memory bank 9, the memory bank control signal 6 temporarily changes as described above, and the memory bank #1 8 is temporarily selected, #1
Writing is performed to the RAM area of memory bank 8.

In this embodiment, #1 memory bank 8 and #2 memory bank
This is an example in which the address map is symmetrical to bank 9, but even if it is not the target, memory bank control circuit 3 can control the address decoding of the memory bank in the same way as in this embodiment. It can be carried out.

〔Effect of the invention〕

As explained above, the present invention includes a ROM write detection circuit that detects when a microprocessor performs a write operation on the ROM area of one of two memory banks, and a ROM write detection circuit that detects when a microprocessor performs a write operation on the ROM area of one of two memory banks. By having a memory bank control circuit that controls switching to the RAM area in the switched memory bank and writing operations to the RAM area in the switched memory bank, the ROM area of one memory bank can be written without performing bank switching processing in the program. from the RAM area in the other memory bank, and
This has the effect of making it possible to transfer data between memory banks without providing a common memory buffer area or the like as in the prior art.

[Brief explanation of drawings]

Fig. 1 is a functional block diagram showing one embodiment of the present invention;
Figures (a) and (b) are #1 in Figure 2, respectively. 7 is a diagram showing an example of an address map of the ROM area and RAM area of memory bank #2. FIG. DESCRIPTION OF SYMBOLS 1... Microprocessor, 2... ROM write detection circuit, 3... Memory bank control circuit, 4... Address bus and bus control signal line, 5... Data bus, 6... Memory bank control signal, 7... ROM write detection signal, 8... #1 memory bank, 9...
#2 Memory bank.

Claims (1)

[Claims] Each of the first and second memory banks divided into banks for program read operations processed by the microprocessor has a ROM area as a read-only storage area and a RAM area as a read/writable storage area; a ROM write detection circuit for detecting that a microprocessor performs a write operation on the ROM area of one of the first and second memory banks;
The OM write detection circuit is connected to the RO of the one memory bank.
a memory bank control circuit that controls the microprocessor to perform a write operation to the RAM area of the other memory bank when a write operation to the M area is detected, and memory bank switching processing within the program; R of the first or second memory bank without performing
A memory bank control method for a microprocessor, characterized in that the microprocessor writes data in an AM area.