JPH0475160A - Data processor - Google Patents

Abstract

PURPOSE:To realize a data processor which accelerates data transfer between plural kinds of computing elements and suitable for fuzzy information processing by dividing memory into banks corresponding to data type handled by the computing element, and connecting each computing element to a memory bank with a bus dedicated to the data type. CONSTITUTION:A bus switching means 50 switches the connection of the bus according to signals from switching means 31-34 so as to perform write or readout from the computing elements 11-18 on the memory bank decided in accordance with the data type handled by the computing elements 11-18. Therefore, when the computing elements 11-18 make access the memory bank 70 with the same data type as that of its own, access can be performed only by arbitration between the computing elements 11-18 of the same type. Thereby, when a various kinds of data processing are performed by using several kinds of computing elements 11-18, the computing elements 11-18 can be efficiently operated in parallel, and large volume of data processing such as fuzzy information can be executed at high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing device that processes a large amount of data using a plurality of types of arithmetic units.

[Conventional technology]

In recent years, fuzzy theory has attracted attention as a method for handling human ambiguity, and fuzzy computers that perform information processing based on this theory have been studied. This fuzzy computer is required to process a large amount of data expressed in fuzzy sets at high speed, which is an order of magnitude larger than that of normal digital operations. To achieve this, it is necessary to use a plurality of different types of arithmetic units and operate them in parallel in order to process fuzzy set operations at high speed.

On the other hand, when performing various data processing using a plurality of arithmetic units, the following method is used.

One is, as shown in Figure 3. M number of computing units 1 to n
and prepare multiple buses 1 to m for one memory,
This is a method in which writing or successive output from each arithmetic unit to memory is controlled by a common bus controller. The other method, as shown in Figure 4, is to prepare a single bus for multiple arithmetic units 1-n and one memory, and share this bus to write data from each arithmetic unit to the memory. Alternatively, there is a method of reading data.

[Problems to be Solved by the Invention] However, according to the above conventional method, when multiple arithmetic units access one memory, the operations are performed in parallel by the multiple arithmetic units, but the access to the memory is is limited to the number of arithmetic units equal to the number of buses. Therefore, data transfer using such a bus becomes an obstacle, and data processing performance is not improved. Particularly, there is a problem in that it is difficult to adopt fuzzy information processing, which requires high-speed processing of a large amount of data as described above.

Furthermore, when using a plurality of buses as shown in FIG. 4, there is a problem in that complicated bus control is required.

An object of the present invention is to provide a device that can efficiently process a large amount of data, such as fuzzy information, in parallel by efficiently operating each computing unit in parallel when performing various data processing using multiple types of computing units. It is to be.

[Means to solve the problem]

The present invention provides a plurality of types of arithmetic units each classified according to the type of data handled, a memory divided into a plurality of banks corresponding to the types of these arithmetic units, and data transfer between the arithmetic units and the memory. a bus for performing the above operations, a bus switching means interposed between the arithmetic unit and the memory and switching the connection of the bus, and a switching control means for controlling the bus switching means in response to an access request from the arithmetic unit. The method is characterized in that the plurality of types of arithmetic units can access different memory banks simultaneously.

In an embodiment of the present invention, at least one of the plurality of types of arithmetic units is a fuzzy arithmetic unit, and the corresponding memory bank is a memory area defined to store fuzzy data.

[Effect]

When performing various data processing using multiple computing units,
The bus switching means switches the bus connection according to a signal from the switching control means so that writing or reading from the arithmetic unit is performed in a memory bank determined according to the type of data handled by the arithmetic unit.

The type of data in the memory bank is specified, for example, by a control means that provides arithmetic instructions to the device. The designated data type is held in a table set in the bus switching control means and used as information necessary for bus connection.

When each arithmetic unit accesses a memory bank of the same data type as itself, the access can be made only by arbitration between the arithmetic units of the same type. Therefore, in this case, a plurality of different types of arithmetic units can access the memory simultaneously.

The bus switching control means resolves memory access conflicts in response to requests issued from the arithmetic unit and enables the arithmetic unit to access memory.

〔Example] FIG. 1 shows the configuration of an embodiment of the present invention.

In the figure, a plurality of (eight in this case) arithmetic units 11 to 18
are classified according to the type of data they each handle. Examples of data types include integer types, floating point types, fixed point types, and fuzzy types. In this embodiment, the computing unit 1
Numbers 1 to 18 are classified into four types, two each.

Integer arithmetic units 11 and 1 of the same type, that is, the same data type
2. For floating point arithmetic units 13 and 14, fixed point arithmetic units 15 and 16, and fuzzy arithmetic units 17 and 18, four bus controllers 31 to 28 are connected to each other via buses 21 to 28 for each arithmetic unit. 34 are connected. These bus controllers each consist of a hash arbiter having a bus arbitration function that controls bus connections between arithmetic units of the same data type.

The bus controllers 31 to 34 are connected to a bus switch 50, which will be described later, via arithmetic unit type hashes 41 to 44 corresponding to each data type.
Memory bank bus 60t corresponding to data types 1 to 18
~60. .

It is connected to the memory 70 via.

The memory 70 has a plurality of banks 70. It is divided into ~70 i. Each bank consists of memory areas defined to store data of a corresponding type. In this way, each arithmetic unit has the same data type as itself, such as an integer type, a floating point type, a fixed point type, or a fuzzy type memory bank 70° to 70°.
can be accessed only by arbitration between arithmetic units of the same type. Therefore, in this case, a plurality of different types of arithmetic units can access the memory simultaneously.

Next, the bus switch 50 will be explained.

Figure 2 shows that there are 16 memory banks for four types of arithmetic units.
The configuration of the bus switch 50 in the case of 1 is shown.

The bus switch 50 includes a 4×4 crossbar switch 51 connected to the arithmetic unit type lotuses 41 to 44, and four IX4 crossbars connected to the crossbar switch 51 via buses 52 and 524, respectively. -Switch 53~
56, the arithmetic unit type buses 41 to 44, and the memory bank bus 60. ~6016 crossbar switch 51~
56, a bank table 58 that holds the data type to be stored in the corresponding memory bank, and a bus switch controller 57 that sends signals in response to access requests from each arithmetic unit 11 to 18. It consists of a bus switch arbiter 59 that sends data.

In the bus switch 50 having the above configuration, the bank table 58 includes a memory control unit (not shown) that manages memory.
The type of data exchanged between the arithmetic unit and memory is written.

On the other hand, the path switch arbiter 59
When the bus switch controller 8 accesses data of a data type other than its own, the bus switch controller 5
Sends a connection request to 7.

The head switch controller 57 is connected to the bank table 5.
8 and the signal from the path switch arbiter 59, the crossbar switches 51 to 8
For example,
The result of the fuzzy operation performed by the fuzzy arithmetic unit 17 is stored in the memory bank 70 as an integer. Make the bus connection so that it is stored in the

In the above embodiment, the crossbar switches 51 to 56 constitute a bus switching means for switching the connection of the data transfer bus between the arithmetic unit and the memory, and the bus switch controller 57, the bank table 58, and the hash switch arbiter 59 , constitutes a switching control means for controlling the bus switching means.

Although the embodiments have been described above, the present invention is not limited thereto. For example, the number and type of computing units, the configuration of the bus switching means, and the switching control means are not limited to those shown in the figure.
Any circuit can be used as long as it achieves a similar function.

〔Effect of the invention〕

As described above, according to the present invention, the memory is divided into banks according to the type of data handled by the arithmetic units, and each arithmetic unit is connected to the memory bank by a bus dedicated to that data type. , buses are provided in the same number as the types of data types, speeding up data transfer between a plurality of types of arithmetic units and memory, and providing a data processing device suitable for fuzzy information processing.

Furthermore, since the memory is divided into banks according to the data type, data can be easily stored by simply attaching a tag indicating the data type to each bank.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of the lotus switch section in FIG. 1, and FIGS. 3 and 4 are block diagrams showing the configuration of the lotus switch section in FIG. 1 is a diagram showing a conventional data processing method. 11-18... Arithmetic unit, 21-28... Bus, 31-34... Bus controller, 41-44... Arithmetic unit type lotus, 50...
・Bus switch, 601-60.・・・・・・Memory bank bus, 70・
...Memory, 701-70. l...Memory bank. FIG, 2 Access request FIG, 3 FIG, 4

Claims (2)

[Claims] (1) A plurality of types of arithmetic units each classified according to the type of data they handle, a memory divided into banks of a plurality of data types corresponding to the types of the arithmetic units, and between the arithmetic units and the memory. a bus for data transfer; a bus switching unit interposed between the arithmetic unit and the memory to switch the connection of the bus; and a switch for controlling the bus switching unit in response to an access request from the arithmetic unit. 1. A data processing device, comprising: a control means, the plurality of types of arithmetic units being able to access different memory banks simultaneously. (2) At least one of the plurality of types of arithmetic units is a fuzzy arithmetic unit, and the corresponding memory bank is a memory area determined to store fuzzy data. ) data processing device.